JPH09205367A - Integration a/d conversion method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To convert an analog signal into a digital signal with high accuracy in a short conversion time by obtaining each count for a 3rd integration period so as to obtain the digital signal corresponding to a converted voltage. SOLUTION: A 1st reference voltage Vr (with opposite polarity to a converted voltage) inputted by an input terminal 2 is integrated by an integration device 4 via a buffer 3 for a 2nd integration period. A 2nd reference voltage -Vr of the same level as and different from the polarity to a 1st reference voltage Vr used for a 2nd integration period is applied to the input terminal 2 to conduct integration toward an integration start point from a trigger point of time of a counter 9 after zero crossing point for a 3rd integration period. The count for the 3rd integration period obtained in this way is proportional to a conversion error generated for the 2nd integration period, then A/D conversion with high accuracy is conducted by calculating the count for the 2nd integration period and the count for the 3rd integration period.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention integrates an input voltage to be converted for a fixed time, inversely integrates the integrated voltage with a reference voltage, and based on the count number of the inverse integration period,
The present invention relates to an integral type A / D conversion method for performing / D conversion, and particularly to an A / D conversion method in which the conversion time is short and the conversion error is reduced.

[0002]

2. Description of the Related Art Integral A / D converters are widely used in fields requiring high accuracy such as digital voltmeters, digital panel meters, and digital multimeters. A circuit configuration of a conventional double integration type A / D converter is shown in FIG.

Reference numeral 1 is an input terminal for inputting a converted voltage Vin, 2 is an input terminal for inputting a reference voltage Vr, 3 is a buffer consisting of a voltage follower composed of an operational amplifier, 20
Is an integrator composed of a resistor R3, capacitors C1 and C2, and an operational amplifier 5, 6 is a comparator using an operational amplifier,
Reference numeral 8 is a control circuit, and 9 is a counter. S1-S4, S6
Is an analog switch, which is controlled by the control circuit 8. In addition to the output of the comparator 6, the clock CLK is also input to the control circuit 8.

In this A / D converter, as shown in FIG. 6, one conversion cycle is constituted by the auto-zero period, the first integration period, and the second integration period.

During the first auto-zero period, switch S1
~ Only switches S3 and S6 of S4 and S6 (or switch S4 is temporarily turned on and off, then switch S3
(3, S6 only) is turned on, and the offset is removed and initialized. That is, the zero voltage is input to initialize the whole, and the offset voltage of the operational amplifier of the buffer 3, the operational amplifier 5 of the integrator 20, the comparator 6, etc. appearing at that time is canceled by the auto-zero capacitor C2.

In the first integration period, only the switch S1 is turned on, and the converted voltage Vin applied to the input terminal 1 passes through the buffer 3 and is integrator 20 for a predetermined period of time to set the threshold voltage ( 0V) to the converted voltage Vi
It is integrated with the voltage of the opposite polarity of n. As a result, at the end of the first integration period, the integrated voltage Vo corresponding to the level of the input converted voltage Vin appears on the output side of the integrator 20.

In the second integration period, only the switch S2 is turned on, and the first reference voltage Vr applied to the input terminal 2 is applied.
The (inverted polarity of the converted voltage Vin) is integrated (inverse integration) by the integrator 20 via the buffer 3 until it reaches 0V. At this time, the integrated voltage Vo of the integrator 20 is attenuated at a constant attenuation rate according to the level of the first reference voltage Vr and reaches 0V.

Therefore, by counting the number of clocks CLK input to the counter 9 via the control circuit 8 during the second integration period which is the inverse integration period, the input converted voltage Vin becomes a digital signal. To be converted. The larger the level of the converted voltage Vin, the larger the count value.

[0009]

However, in the A / D converter shown in FIG. 5, noise appears at the apparent zero point (threshold value) when the offset compensation voltage is charged in the auto-zero capacitor C2 during the auto-zero period. Therefore, it is not affected by the low resolution A / D converter, but could not be used in the field requiring a resolution of several tens of μV.

Further, the accurate period of the second integration period is a period from the time point when the reverse integration is started to the time point when the output voltage Vo of the integrator 20 crosses the voltage (0V) at the time point when the integration is started. Actually, since the count value of the counter 9 is determined by the trigger of the clock CLK that first occurs after the zero crossing and the second integration period is measured, a conversion error (count error) occurs.

Therefore, in order to improve the conversion accuracy, the first and second integration times are lengthened or the clock C is used.
Although improvements such as increasing the frequency of LK have been made,
The former requires a longer conversion time, and the latter has a problem that the clock frequency is limited by the response speed of the analog circuit.

The present invention has been made in view of the above points, and an object thereof is to provide an integration type A / D conversion method capable of converting an analog signal into a digital signal with high accuracy in a short conversion time. .

[0013]

According to a first aspect of the present invention, a voltage to be converted is input, first integration is performed with a predetermined integration constant for a preset period from a zero level, and the first integration is obtained. The first reference voltage is input to the integrated voltage, the second integration is performed in the opposite direction until the zero level is crossed by the integration constant, and the clock in the second integration period is counted by the counting means. In the integration type A / D conversion method for obtaining a digital signal corresponding to the converted voltage, the second integration is made steeper than before when a zero level of the integration voltage is detected while the integration is in progress. And then progresses to the point at which the counting means is first triggered, and from the point at which the counting means is first triggered of the second integration, to a second polarity opposite to the first reference voltage. Standard electricity Third toward zero level by entering
Of the second integration period and the third integration period are obtained by the counting means, and both count numbers are calculated to obtain a digital signal corresponding to the converted voltage. , And is configured as an integral type A / D conversion method.

In a second aspect based on the first aspect, the calculation is performed by subtracting the count number in the third integration period from a value obtained by multiplying the count number in the second integration period by a predetermined number. It is configured as an integral type A / D conversion method characterized by being performed.

According to a third aspect of the present invention, the first voltage is input from the zero level with a predetermined integration constant for a preset period from the zero level.
Is performed, the first reference voltage is input to the integrated voltage obtained by the first integration, the second integration is performed in the opposite direction until the zero level is crossed by the integration constant, and the second integration is performed. In the integration type A / D conversion method for obtaining a digital signal corresponding to the voltage to be converted by counting the clock of the integration period by the counting means, the second integration is performed while the integration is in progress. Is detected, the integration is made steeper than before, and then the counting means is advanced to a time point at which the counting means is first triggered, and from the time point when the counting means is first triggered in the second integration, A second reference voltage having a polarity opposite to that of the first reference voltage is input to perform a third integration toward a zero level, and when a zero level is detected, the integration is changed to a steeper integration than before and then Is A fourth step of advancing the counting means to the first trigger point and inputting the first reference voltage toward the zero level from the first trigger point of the third integration. Of the second integration period, the third integration period, and the fourth integration period are obtained by the counting means, and the count numbers are calculated to calculate the count numbers. It is configured as an integral type A / D conversion method characterized by obtaining a digital value corresponding to the voltage to be converted.

In a fourth aspect based on the third aspect, the third integration is continuously performed a plurality of times by alternately switching between the first reference voltage and the second reference voltage, and the fourth integration is performed. At a reference voltage opposite to the first or second reference voltage used in the third integration immediately before, and a period of the second integration, a period of the plurality of third integrations, and The present invention is configured as an integral type A / D conversion method characterized in that each counting number in the fourth integration period is obtained by the counting means and the calculation is performed.

In a fifth aspect based on the first to fourth aspects, in order to change the steep integration, the integration constant is changed to a small value, or the first or second reference voltage is changed. It is configured as an integral type A / D conversion method characterized by changing to another reference voltage having the same polarity and a higher level.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION

[First Embodiment] The first embodiment of the present invention will be described below. FIG. 1 is a diagram showing a circuit configuration of an A / D converter to which the integral type A / D conversion method of the present invention is applied. The same components as those described with reference to FIG. 5 are designated by the same reference numerals, and detailed description thereof will be omitted. Reference numeral 4 denotes an integrator, which includes resistors R1 and R2, a capacitor C1, an operational amplifier 5, and an analog switch S5. The analog switch S5 is controlled by the control circuit 8. 1
Reference numeral 0 is a calculator for calculating the output value of the counter 9. Since the gain is small in this circuit, the comparator 7 is added to the output side of the comparator 6.

In this A / D converter, as shown in FIG. 2, one conversion cycle is constituted by the zero integration period, the first integration period, the second integration period, and the third integration period. First, in the zero integration period, only the switch S4 is turned on, the input terminals 1 and 2 are disconnected from the circuit, and the internal setting of the circuit is performed.

In the first integration period, only the switch S1 is turned on and the converted voltage Vin is input to the input terminal 1. The converted voltage Vin is integrated by the integrator 4 via the buffer 3 with a polarity opposite to that of the converted voltage Vin for a predetermined period of time, and the converted voltage Vin is converted.
The integrated voltage Vo having a level corresponding to is obtained.

In the second integration period, only the switch S2 is turned on, and the first reference voltage Vr (reverse polarity to the converted voltage) input to the input terminal 2 is passed through the buffer 3 to the integrator 4. It is integrated (inverse integration). As a result, the integrated voltage Vo of the integrator 4 is attenuated at a constant attenuation rate according to the level of the first reference voltage Vr. This inverse integration is performed until the zero crossing point where the integration start point (threshold voltage: 0 V) is crossed, but as described above, the count value of the counter 9 is actually determined by the trigger of the clock first generated after the zero crossing. Since the second integration period is determined, a conversion error (count error) occurs.

Therefore, in the present invention, the control circuit 8 detects the timing t1 (the timing at which the comparator 6 is inverted) at which the output of the integrator 4 exceeds the zero cross point in the second integration period, and the switch S is detected at the timing t1.
5 is turned on to short-circuit the resistor R2, and the integration constant of the integrator 4 is changed to a small value (for example, changed to about 1/10 of the original value) to increase the rate of change of the integration voltage Vo, and this integration constant is zero-crossed. The counter integration is continued until the timing t2 of the transition of the counter 9 triggered by the clock CLK first generated later, and the inverse integration is continued. By this operation, the error voltage that is the conversion error is amplified, and the third integration period that can be counted by the counter 9 again can be obtained thereafter.

In the third integration period, from the trigger time (timing t2) of the counter 9 after the zero crossing, the second reference having the same level as the first reference voltage Vr used in the second integration period but having the different polarity is used. A voltage -Vr is applied to the input terminal 2 to perform integration toward the integration start point. Since the count value of the third integration period obtained by this is proportional to the conversion error generated in the second integration period, the count value of the second integration period and the count value of the third integration period are calculated. By doing so, it becomes possible to perform highly accurate A / D conversion. The above will be described in detail later.

Since the second integration period is before the count value is updated (until the timing t2), the second integration period is not extended as compared with the conventional method described with reference to FIGS. Therefore, since the conversion time is extended only for the third integration period, there is almost no increase in the conversion time due to the increase in accuracy.

Since the auto-zero capacitor C2 is not used, it is not affected by noise generated during the auto-zero period. However, since an auto zero capacitor is not used, an offset occurs, but regarding this,
The switch S3 is turned on in advance to make a zero input, and the count value at that time is used as an offset A / D conversion value to obtain the operation unit
It can be canceled by storing it in 0 and subtracting it from the A / D conversion value of the converted voltage measured thereafter.

FIG. 3 is a waveform diagram showing the timing in the vicinity of the zero cross for explaining the essential points of the present invention in detail. The count value of the second integration period treated as the A / D converted value is determined by the first rising timing t2 of the clock CLK after the timing t1 at which the output of the comparator 6 is inverted.

In the conventional A / D converters shown in FIGS. 5 and 6, even after the integrated voltage Vo has dropped below the threshold value, it is attenuated at the previous inverse integration attenuation rate. Therefore, the broken line in FIG. 3 is used. As shown by, an error voltage of Va occurs at the timing t2. The comparator 6 is inverted at the timing t2.
Although the previous count value is "A-1", since the counter 9 is updated at the timing t2, the actual count value becomes "A", and an error occurs during the period from t1 to t2 of the timing.

On the other hand, in the present invention, the comparator 6
The integration constant is switched at a timing t1 at which is inverted, and a steep integration is performed with a small time constant, and an error voltage of "Va + Vb" is obtained at a timing t2. That is, the error voltage of Va is amplified to "Va + Vb" (amplified about 10 times).

Therefore, with respect to this error voltage "Va + Vb", a third reference voltage -Vr having a polarity opposite to that of the first reference voltage Vr and having the same level as that of the second reference voltage -Vr
Is performed, the count value in the third integration period (the count value at the first rising edge of the clock CLK after exceeding the zero-cross point) becomes the count value corresponding to the error voltage “Va + Vb”.

Therefore, the count value of the second integration period is A, and the count value of the third integration period is X (= B-
A), multiplying A by 10, and calculating by the calculation unit 10 as N = 10A−X (1), the error voltage “Va + V
The count value N obtained by canceling "b" is obtained, and the accuracy can be increased by one digit. At this time, the conversion time becomes longer by the third integration time, but the third integration time becomes the second integration time.
The conversion time is slightly increased, since the time is equal to or less than the minimum digit counting time (for example, the time for counting 10 in decimal) of the integration time. As an example, the second integration period is about 4000 counts in full scale.

[Second Embodiment] FIGS. 1 to 3 described above.
Although the conversion error (count error) of the second integration period is canceled by the count value of the third integration period in the contents of the first embodiment described in Section 3, the same applies to this third integration period. A count error occurs at the final part.

Therefore, as shown in FIG. 4, from the third integration period to the (M + 2) th integration period (when the third integration period is the first time for error correction, up to the Mth time), the conversion error component is similarly calculated. By repeating the operation of amplifying and integrating the contents next, the conversion error can be further reduced and the accuracy can be improved. The reference voltage used at this time is alternately switched to −Vr in the third integration period, Vr in the fourth integration period, and −Vr in the fifth integration period. Therefore, since the odd-numbered integration has a different polarity of the obtained integrated voltage from the even-numbered integration, the arithmetic unit 10 subtracts the count value of the integration period in the odd-numbered integration and the count value in the even-numbered integration. to add. Furthermore, by weighting the count value of each integration for each digit number, the precision for M digits can be improved. Even in this case, the decimal number is 10
The count of xM only increases, and the conversion time increases only slightly. Although the error is not corrected in the final (M + 2) th integration period, the error can be ignored by increasing the value of M.

The above integration operation is repeated three times (M =
3), the calculation in the case of performing up to the fifth integration period will be described. N = 1000A-100X + 10Y where A is the count value of the second integration period, X is the count value of the third integration period, Y is the count value of the fourth integration period, and Z is the count value of the fifth integration period. It is possible to obtain a conversion value N such that -Z ... (2).

[Other Embodiments] In the above, the second reference voltage −Vr applied to the input terminal 2 of FIG. 1 is used.
Has a voltage that differs from the first reference voltage Vr only in polarity, but may have a different level. Further, in the above, the switching method of the integration characteristic is adopted in which the resistor R2 in the integrator 4 is short-circuited by the switch S5 to amplify the error voltage and the integration constant is reduced by about 1/10, but the capacitor C1 is used. The value of the reference voltage Vr or −Vr applied to the terminal 2 may be switched midway. Further, here, since the integration constant is switched to about 1/10 for counting the error voltage, the weighting difference between adjacent digits is made 10 times, but the invention is not limited to this, and the slope of the integration characteristic is switched. 4 times depending on
Of course, it can be set arbitrarily such as 6 times and 16 times.

[0035]

As described above, according to the integral type A / D conversion method of the present invention, it becomes possible to improve the conversion accuracy without making the conversion time too long.
It is suitable for fields requiring high precision such as digital panel meters and digital multimeters.

[Brief description of drawings]

FIG. 1 shows an integral type A / which shows a first embodiment of the present invention.
It is a circuit diagram which shows the structure of a D converter.

FIG. 2 is an operation waveform diagram of the A / D converter according to the first embodiment.

FIG. 3 is an enlarged waveform diagram of a part of the waveform diagram of FIG.

FIG. 4 is an operation waveform diagram showing a second embodiment.

FIG. 5 is a circuit diagram showing a configuration of a conventional integral A / D converter.

FIG. 6 is an operation waveform diagram of a conventional A / D converter.

[Explanation of symbols]

1: Input terminal for converted voltage, 2: Input terminal for reference voltage,
3: buffer, 4: integrator, 5: operational amplifier, 6, 7:
Comparator, 8: control circuit, 9: counter, 10: arithmetic unit, 20: integrator, S1 to S6: analog switches.

Claims (5)

[Claims] 1. A first reference voltage is applied to an integrated voltage obtained by the first integration by inputting a voltage to be converted and performing a first integration with a predetermined integration constant for a preset period from a zero level. Is input and second integration is performed in the reverse direction until the zero level is crossed by the integration constant, and the clock in the second integration period is counted by the counting means to obtain a digital signal corresponding to the converted voltage. Integral type A / D
In the conversion method, the second integration is changed to a steeper integration than before when a zero level of the integration voltage is detected during the progress of integration, and thereafter until the time when the counting means is first triggered. From the time when the counting means is first triggered of the second integration, the second reference voltage having a polarity opposite to that of the first reference voltage is input and the third integration is performed toward a zero level. And obtaining each count number of the second integration period and the third integration period by the counting means, and calculating both count numbers to obtain a digital signal corresponding to the converted voltage. An integral type A / D conversion method characterized by: 2. The calculation is performed by subtracting the count number of the third integration period from a value obtained by multiplying the count number of the second integration period by a predetermined number.
The integral type A / D conversion method described in 1. 3. A converted voltage is input, a first integration is performed with a predetermined integration constant for a preset period from a zero level, and a first reference voltage is obtained with respect to the integrated voltage obtained by the first integration. Is input and second integration is performed in the reverse direction until the zero level is crossed by the integration constant, and the clock in the second integration period is counted by the counting means to obtain a digital signal corresponding to the converted voltage. Integral type A / D
In the conversion method, the second integration is changed to a steeper integration than before when a zero level of the integration voltage is detected during the progress of integration, and thereafter until the time when the counting means is first triggered. From the time when the counting means is first triggered of the second integration, the second reference voltage having a polarity opposite to that of the first reference voltage is input and the third integration is performed toward a zero level. When the zero level is detected, the integration is made steeper than before, and then the counting means is advanced to the point of time when the counting is first triggered. From the time of being triggered, the first reference voltage is input to perform a fourth integration toward the zero level, the counting means performs the second integration period, the third integration period, and An integral type A / D conversion method, wherein each count number in the fourth integration period is obtained, and the count numbers are calculated to obtain a digital value corresponding to the converted voltage. 4. The third integration is continuously performed a plurality of times by alternately switching the first reference voltage and the second reference voltage, and the fourth integration is performed immediately before the third integration. Of the first or second reference voltage used in the above, and the second integration period, the plurality of third integration periods, and the fourth integration period. 4. The integral type A / D conversion method according to claim 3, wherein each count number is obtained by the counting means and the calculation is performed. 5. In order to change to the steep integration, the integration constant is changed to a small value, or the first or second reference voltage is changed to another reference voltage having the same polarity and a larger level. The integral type A / D conversion method according to any one of claims 1 to 4, wherein