CN113852372B - Reference charge compensation method and device for integral analog-to-digital converter - Google Patents
Reference charge compensation method and device for integral analog-to-digital converter Download PDFInfo
- Publication number
- CN113852372B CN113852372B CN202111014320.9A CN202111014320A CN113852372B CN 113852372 B CN113852372 B CN 113852372B CN 202111014320 A CN202111014320 A CN 202111014320A CN 113852372 B CN113852372 B CN 113852372B
- Authority
- CN
- China
- Prior art keywords
- program
- time
- voltage
- reference source
- controlled
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 36
- 239000003990 capacitor Substances 0.000 claims abstract description 42
- 230000010354 integration Effects 0.000 claims abstract description 38
- 238000006243 chemical reaction Methods 0.000 description 7
- 238000005259 measurement Methods 0.000 description 7
- 238000003491 array Methods 0.000 description 6
- 238000013139 quantization Methods 0.000 description 3
- 229920006395 saturated elastomer Polymers 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910002056 binary alloy Inorganic materials 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/0602—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic
- H03M1/0604—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic at one point, i.e. by adjusting a single reference value, e.g. bias or gain error
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/50—Analogue/digital converters with intermediate conversion to time interval
- H03M1/52—Input signal integrated with linear return to datum
Abstract
The invention provides a reference charge compensation method of an integral analog-to-digital converter, which comprises the following steps: step 1, a voltage signal to be measured is connected into a first integrating circuit to charge a first integrating capacitor, wherein the charging time is a fixed time T 1 The method comprises the steps of carrying out a first treatment on the surface of the Step 2, the measured voltage signal is connected to a second integrating circuit to charge a second integrating capacitor, wherein the charging time is a fixed time T 2 Simultaneously, a program-controlled voltage reference source is connected into a first integrating circuit to carry out charge compensation on a first integrating capacitor, and the compensation time T is recorded a Wherein the T is 2 ≥T a The method comprises the steps of carrying out a first treatment on the surface of the Step 3, the measured voltage signal is connected into a first integrating circuit to charge a first integrating capacitor, wherein the charging time is a fixed time T 1 Simultaneously, a program-controlled voltage reference source is connected into a second integrating circuit to carry out charge compensation on a second integrating capacitor, and the compensation time T is recorded b Wherein the T is 1 ≥T b The method comprises the steps of carrying out a first treatment on the surface of the And 4, repeatedly executing the step 2 and the step 3 for a plurality of times, and ending the first integration stage.
Description
Technical Field
The present invention relates to an integrating analog-to-digital converter, and more particularly, to a method and apparatus for compensating reference charge of an integrating analog-to-digital converter.
Background
In the field of electronics, reference charge compensation methods are common methods for improving the measurement resolution of integrating analog-to-digital converters. The invention mainly solves the problems that the analog-to-digital conversion precision and stability are affected by the resistor proportion drift faced by the traditional method for realizing reference charge compensation by using a resistor network, and the compensation rate is not adjustable.
The basic working principle of the integrating analog-digital converter is to convert the average value of the measured voltage signal in a fixed integration time into a time interval proportional to the average value for measurement. The integrator saturation margin is a major factor limiting the improvement in its measurement resolution, among other things. The saturation margin of the integrator, which is generally equal to the output voltage peak-to-peak value of the operational amplifier in the integrating circuit, determines the maximum time the measured voltage signal is allowed to be integrated in the first integration phase. For input signals of larger amplitude, the integrator can be saturated in a very short time. Thus, limited by the timing resolution of the time counter, a shorter total integration time will mean a lower analog-to-digital conversion resolution.
The reference charge compensation method is a method for effectively prolonging the integration time of the first integration stage, namely improving the measurement resolution of the integrated analog-to-digital converter, and the core idea of the method is to periodically input compensation charges into the integrator by utilizing a reference voltage signal in the first integration stage so that the charge quantity in the integrator never reaches a saturated state. Since the amount of reference charge input is known, i.e. equivalent to the completion of the higher order digital quantization of the input voltage signal, only the lower order digital quantization of the remaining difference charge has to be completed in the subsequent second integration stage. Therefore, the purpose of improving the measurement resolution is achieved.
The traditional reference charge compensation method is realized by constructing a resistor network. As shown in fig. 1, in the first integration stage, when the switch Sa is closed, the measured voltage signal Vi is converted into the current signal Ia through the resistor Ra to charge the integrator J1, and meanwhile, the switches Sb and Sc are sequentially closed or opened according to a predetermined logic, so that the reference voltage signals Vref and-Vref are respectively converted into the current signals through the resistors Rb and Rc to perform charge compensation on the integrator J1, so as to ensure that the output voltage Vo of the integrator J1 always does not exceed the saturation tolerance. In the reference charge compensation process, the total amount of the compensated charge is determined by the magnitudes of the reference voltage signals Vref and the closing time of the switches Sb and Sc.
The traditional reference charge compensation implementation method based on the resistor network can improve the measurement resolution of analog-to-digital conversion, but has the following two problems:
first: on the assumption that the second integration phase is completed through the resistor Rd (Rd may also be any one of Ra, rb and Rc), the resistance ratios Ra/Rd, rb/Rd and Rc/Rd will be contained in the quantization result of the analog-to-digital conversion, so that the resistance change caused by factors such as the load factor and the temperature coefficient of the resistor element will directly affect the accuracy and the stability of the analog-to-digital conversion.
Second,: the magnitudes of the resistive elements Rb and Rc determine the rate of reference charge compensation and cannot be dynamically adjusted as desired.
Disclosure of Invention
In order to overcome the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a reference charge compensation method and apparatus for an integrating analog-to-digital converter with an adjustable reference charge compensation rate without affecting the accuracy and stability of the final result of the analog-to-digital conversion
In order to achieve the above object, the present invention provides a reference charge compensation method for an integral analog-to-digital converter, comprising the steps of:
step 1, a voltage signal to be measured is connected into a first integrating circuit to charge a first integrating capacitor, wherein the charging time is a fixed time T 1 ；
Step 2, the measured voltage signal is connected to a second integrating circuit to charge a second integrating capacitor, wherein the charging time is a fixed time T 2 Simultaneously, a program-controlled voltage reference source is connected into a first integrating circuit to carry out charge compensation on a first integrating capacitor, and the compensation time T is recorded a Wherein the T is 2 ≥T a ；
Step 3, the measured voltage signal is connected into a first integrating circuit to charge a first integrating capacitor, wherein the charging time is a fixed time T 1 Simultaneously, a program-controlled voltage reference source is connected into a second integrating circuit to carry out charge compensation on a second integrating capacitor, and the compensation time T is recorded b Wherein the T is 1 ≥T b ；
And 4, repeatedly executing the step 2 and the step 3 for a plurality of times, and ending the first integration stage.
Further, the specific step of charge compensation in step 2 includes:
a1: setting an initial voltage amplitude of a program-controlled voltage reference source through a controller and enabling the polarity of the program-controlled voltage reference source to be opposite to that of the measured voltage signal;
a2: the reference source of the programmable power supply is connected into a first integrating circuit to carry out charge compensation on a first integrating capacitor, and the output level change of a first zero-crossing comparator and the count value of a first time counter are detected at the same time, if the compensation time T a ＝T 2 Ending the charge compensation, proceeding to step 3, if the compensation time T a ＜T 2 And the output level of the first zero-crossing comparator changes, and then the step A3 is continuously executed;
a3: and (3) reducing the amplitude of the output voltage of the program-controlled voltage reference source by a fixed multiplying power x, changing the polarity, and then returning to the step A2.
Further, step A3 may further be: reducing the amplitude of the output voltage of the program-controlled voltage reference source by a fixed multiplying power x and changing the polarity, if the amplitude of the output voltage of the program-controlled voltage reference source is larger than or equal to |V at the moment ref And I, returning to execute A2, otherwise, disconnecting the program-controlled voltage reference source signal and waiting for the charging time of the second integrating capacitor to be T 2 Step 3 is then continued, wherein V ref The l is characterized as the reference voltage corresponding to the minimum reference charge compensation rate.
Further, the specific step of charge compensation in step 3 includes:
b1: setting an initial voltage amplitude of a program-controlled voltage reference source through a controller and enabling the polarity of the program-controlled voltage reference source to be opposite to that of the measured voltage signal;
b2: the reference source of the programmable power supply is connected into a second integrating circuit to carry out charge compensation on a second integrating capacitor, and the output level change of a second zero-crossing comparator and the count value of a second time counter are detected at the same time, if the compensation time T b ＝T 1 Ending the charge compensation, proceeding to step 4, if the compensation time T b ＜T 1 And the output level of the second zero-crossing comparator changes, and then the step B3 is continuously executed;
b3: and (2) reducing the amplitude of the output voltage of the program-controlled voltage reference source by a fixed multiplying power x, changing the polarity, and then returning to the step (B2).
Further, the step B3 may be: reducing the amplitude of the output voltage of the program-controlled voltage reference source by a fixed multiplying power x and changing the polarity, if the amplitude of the output voltage of the program-controlled voltage reference source is larger than or equal to |V at the moment ref And (3) returning to the step B2, otherwise, disconnecting the program-controlled voltage reference source signal and waiting for the charging time of the second integrating capacitor to be T 1 Step 4 is then continued, wherein V ref The l is characterized as the reference voltage corresponding to the minimum reference charge compensation rate.
Further, the fixed charging time T is described in the step 1 and the step 3 1 And a fixed charging time T as described in step 2 2 Are set equal.
Further, the method further comprises an initialization step before executing the step 1: and clearing residual charge release in the first integrating capacitor and the second integrating capacitor through the first charge release circuit and the second charge release circuit.
Based on the above object, the present invention further provides a reference charge compensation device for an integral analog-to-digital converter, which is characterized by comprising:
the first integrating circuit comprises a first program-controlled multi-way switch, a first integrator and a first zero-crossing comparator which are sequentially connected in series, wherein the first program-controlled multi-way switch comprises at least two input ends and an output end;
the second integrating circuit comprises a second program-controlled multi-way switch, a second integrator and a second zero-crossing comparator which are sequentially connected in series, wherein the second program-controlled multi-way switch comprises at least two input ends and an output end;
the program-controlled voltage reference source is used for outputting adjustable reference voltages to the first integrating circuit and the second integrating circuit, and is electrically connected with the first input end of the first program-controlled multi-way switch and the first input end of the second program-controlled multi-way switch at the same time;
the tested voltage signal input end is electrically connected with the second input end of the first program-controlled multi-way switch and the second input end of the second program-controlled multi-way switch at the same time;
a timing module for measuring the integration time T of the first and second integration circuits 1 And T 2 And the actual time T of reference charge compensation a And T b ；
A controller configured to control operation of the programmable voltage reference source, the first programmable multiplexing switch, the second programmable multiplexing switch, and the timing module based on the first and second zero-crossing comparator output signals.
Further, the two ends of the first integrating capacitor are connected with a first charge release circuit in parallel, the first charge release circuit comprises a first power resistor and a first program-controlled single-way switch which are connected in series, the two ends of the second integrating capacitor are connected with a second charge release circuit in parallel, the second charge release circuit comprises a second power resistor and a second program-controlled single-way switch which are connected in series, and the controller is electrically connected with the control ends of the first program-controlled single-way switch and the second program-controlled single-way switch at the same time.
Further, the timing module includes:
for measuring the integration time T of the measured voltage of the first integrating circuit 1 Reference charge compensation time T a And for measuring the measured voltage integration time T of the second integrating circuit 2 Reference charge compensation time T b Is a second time counter of (a); or (b)
For measuring the integration time T of the measured voltage signal 1 、T 2 Is used for measuring the reference charge compensation time T a 、T b Is provided for the first time counter.
Compared with the prior art, the invention has the beneficial effects that: the two sets of integrating circuits are adopted to carry out integration charging and charge compensation on the measured voltage simultaneously, so that the continuous integration of the measured voltage signal is ensured, the charge compensation is carried out on the integrating circuits through a program-controlled voltage reference source with adjustable output voltage, the integration time of a first integration stage is prolonged, and the measurement resolution of an integrating analog-digital converter is improved; meanwhile, the program-controlled voltage reference source with adjustable output voltage is used for replacing the technical scheme of combining a fixed voltage source and a resistor network in the prior art, so that the influence of resistance value change of the resistor network caused by factors such as load factors, temperature coefficients and the like on the charge compensation process is eliminated, and the rate of reference charge compensation can be adjusted by adjusting the voltage change multiplying power and the change times of the program-controlled voltage reference source, so that the integrated analog-to-digital converter reference charge compensation method and device have extremely high stability, accuracy and applicability.
Drawings
Fig. 1 is a schematic circuit diagram of a prior art reference charge compensation device.
Fig. 2 is a schematic block diagram of a reference charge compensation device according to an embodiment of the present invention.
FIG. 3 is a flowchart of a reference charge compensation method according to an embodiment of the present invention.
Fig. 4 is a flow chart of a first integrator charge compensation subroutine of an embodiment of the present invention.
Fig. 5 is a flow chart of a second integrator charge compensation subroutine of an embodiment of the present invention.
Wherein, the reference numerals are as follows: 1: a program controlled voltage reference source; 2: a controller; 3: a first time counter; 4: a second time counter; 5: a first power resistor; 6: a first program controlled one-way switch; 7: a first integrating capacitor; 8: a first zero-crossing comparator; 9: a first operational amplifier; 10: a first current limiting resistor; 11: a first voltage buffer; 12: a first program controlled multi-way switch; 13: a second power resistor; 14: a second program-controlled one-way switch; 15: a second integrating capacitor; 16: a second zero-crossing comparator; 17: a second operational amplifier; 18: a second current limiting resistor; 19: a second voltage buffer; 20: the second program-controlled multi-way switch; 21: the voltage signal input end is measured.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments. Embodiments of the present invention are described below with reference to the accompanying drawings.
As shown in fig. 2, an integrated analog-to-digital converter reference charge compensation apparatus includes: the device comprises a first integrating circuit, a second integrating circuit, a program-controlled voltage reference source 1, a controller 2, a timing module and a measured voltage signal input end 21, wherein the timing module comprises a first time counter 3 and a second time counter 4.
The first integrating circuit comprises a first programmable multiplexing switch 12, a first integrator and a first zero-crossing comparator 8 which are sequentially connected in series, the first integrator comprises a first current limiting resistor 10, a first operational amplifier 9 connected in series with the first current limiting resistor 10 and a first integrating capacitor 7 connected in parallel with the two ends of the first operational amplifier 9, a first voltage buffer 11 is further connected in series between the first programmable multiplexing switch 12 and the first current limiting resistor 10, the two ends of the first integrating capacitor 7 are further connected in parallel with a first charge releasing circuit, the first charge releasing circuit comprises a first power resistor 5 and a first programmable multiplexing switch 6 which are mutually connected in series, the first programmable multiplexing switch 6 comprises an input end, an output end and a control end, the first programmable multiplexing switch 12 comprises a first input end, a second input end, an output end and a control end, the control end of the first programmable multiplexing switch 6 and the control end of the first programmable multiplexing switch 12 are electrically connected with the controller 2 and are controlled to be on-off by the controller 2, and the first programmable multiplexing switch 12 is connected with the first input end or the second input end of the first programmable multiplexing switch 2 or the second input end of the first programmable multiplexing switch is connected with the first input end of the programmable multiplexing switch 2.
The second integrating circuit comprises a second programmable multiplexing switch 20, a second integrator and a second zero-crossing comparator 16 which are sequentially connected in series, the second integrator comprises a second current limiting resistor 18, a second operational amplifier 17 connected in series with the second current limiting resistor 18 and a second integrating capacitor 15 connected in parallel with two ends of the second operational amplifier 17, a second voltage buffer 19 is further connected in series between the second programmable multiplexing switch 20 and the second current limiting resistor 18, two ends of the second integrating capacitor 15 are further connected in parallel with a second charge releasing circuit, the second charge releasing circuit comprises a second power resistor 13 and a second programmable multiplexing switch 14 which are mutually connected in series, the second programmable multiplexing switch 14 comprises an input end, an output end and a control end, the second programmable multiplexing switch 20 comprises a first input end, a second input end, an output end and a control end, the control end of the second programmable multiplexing switch 14 and the control end of the second programmable multiplexing switch 20 are electrically connected with the controller 2 and are controlled to be on-off by the controller 2, and the second programmable multiplexing switch 20 is connected with the second input end or the second input end of the second programmable multiplexing switch 2.
A programmable voltage reference source 1, wherein the programmable voltage reference source 1 is configured to output an adjustable reference voltage to the first integrating circuit and the second integrating circuit, and the programmable voltage reference source 1 is electrically connected to a first input terminal of the first programmable multi-way switch 12 and a first input terminal of the second programmable multi-way switch 20 at the same time; in the embodiment, the programmable Josephson quantum voltage reference device is selected as the range control voltage reference source 1, and the adjustable range of the output voltage of the programmable Josephson quantum voltage reference device (PJVS) is wide (the current maximum capability is +/-10V) and has 10 -9 Accuracy and stability of magnitude. The programmable Josephson junction array (also called PJVS chip) is formed from several Josephson sub-junction arrays which are serially connected, in which the number of Josephson junctions contained in different Josephson sub-junction arrays can be arranged according to a certain principle, such as binary system, ternary system, etc. The basic principle of adjusting the quantum voltage output by the PJVS chip is that different sub-arrays work on different Charpy steps by changing the direction and the amplitude of direct current driving current flowing in different sub-arrays, and at the moment, the quantum voltages at two ends of the different sub-arrays are positive, negative, large and small, and the sum of the quantum voltages at two ends of all the sub-arrays is the quantum voltage output by the whole PJVS chip. The application process of the PJVS system in the invention is as follows: after receiving the target voltage parameter sent by the controller 2, the PJVS system automatically calculates the sub-junction array driving current matched with the target voltage and outputs the sub-junction array driving current through a driver in the sub-junction array driving current, and the PJVS chip immediately generates quantum voltage after receiving the driving current signal.
The measured voltage signal input end 21, the measured voltage signal input end 21 is electrically connected with the second input end of the first program-controlled multi-way switch 12 and the second input end of the second program-controlled multi-way switch 20 at the same time.
The timing module in this embodiment includes: for measuring the integration time T of the measured voltage of the first integrating circuit 1 Reference charge compensation time T a And a measured voltage integration time T for measuring the second integration circuit 2 And reference charge compensation time T b Is provided for the second time counter 4. As another implementation, it can also be set to measure the integration time T of the measured voltage signal 1 、 T 2 And for measuring a reference charge compensation time T a 、T b Is provided for the second time counter 4.
The controller 2 is configured to control the amplitude and the polarity of the output voltage of the programmable voltage reference source 1, the conduction branch of the first programmable multiplexer 12, the conduction branch of the second programmable multiplexer 20 and the timing module to work normally based on the output signals of the first zero-crossing comparator 8 and the second zero-crossing comparator 16.
As shown in fig. 3, a reference charge compensation method of an integrated analog-to-digital converter includes the following steps:
(1) Initializing a circuit and setting parameters x=b, y=n, z=m; wherein the initial voltage amplitude of the program-controlled voltage reference source 1 is set to x y ×|V ref I, the variable z is used to characterize the number of program cycles, then the effective integration time of the measured voltage signal t=z (T 1 +T 2 ) For convenience of explanation, the embodiment sets the first integrating circuit and the second integrating circuit as circuits with identical parameters, and makes the fixed integration time T 1 ＝T 2 。
(2) The first program-controlled single-way switch 6 and the second program-controlled single-way switch 14 are closed under the control of the controller 2, residual charges in the first integrating capacitor 6 and the second integrating capacitor 14 are respectively released and cleared rapidly through the first power resistor 5 and the second power resistor 13, and then the first program-controlled single-way switch 6 and the second program-controlled single-way switch 14 are opened. The residual charge in the first integration capacitance 6 and the second integration capacitance 14 is prevented from affecting the analog-to-digital conversion process.
(3) The variable z=z-1 is started to time the first time counter 3, the first program controlled multi-way switch 12 closes the channel A, the measured voltage signal is buffered by the first voltage buffer 11 and then converted into charging current through the first current limiting resistor 10, and the charging current is input into the integrator formed by the first operational amplifier 9 and the first integrating capacitor 7 for charging until the first time counter 3 is full of T 1 After a while, stopping.
(4) The second time counter 4 starts timing, the second program controlled multi-way switch 20 closes the channel B, the measured voltage signal is buffered by the second voltage buffer 19, and then converted into charging current through the first current limiting resistor 18, and the charging current is input into the second integrator formed by the second operational amplifier 17 and the second integrating capacitor 15 for charging until the second time counter 4 is full of T 2 Stopping after the time; the controller simultaneously controls the first integrating circuit to execute the charge compensation subroutine while executing the above-described process in this step, including:
the first program-controlled multi-way switch 12 closes the channel B, and after the reference voltage signal is buffered by the first voltage buffer 11, the reference voltage signal is converted into charging current through the first current limiting resistor 10 and is input into the first integrator;
let variable y=y-1, and let the amplitude of the output of the programmable voltage reference source 1 be x by detecting the polarity of the output level of the first zero-crossing comparator 8 and the value of variable y y ×|V ref The voltage of opposite polarity to the measured voltage signal (if the measured voltage is positive voltage, and the initial x and y are respectively set to 10 and 4, the program-controlled voltage reference source 1 outputs 1000|V ref Negative voltage, described below as this parameter), the first time counter 3 starts to count time while the first programmable multiplexer 12 closes channel B until the output level of the first zero-crossing comparator 8 changes, and the integration time t is recorded 3 ；
The previous step is repeated, and after the variable y=y-1 (in fact, x is the multiplying factor, the output voltage of the program-controlled voltage reference source 1 is reduced) is executed once per cycle and the polarity of the output voltage is changed (at this time, the program-controlled voltage reference source 1 outputs 100|v) ref Positive voltage) continues to charge the second integrating capacitor until the first zero-crossing comparator 8 output level againWhen the change occurs, the integration time t is recorded 2 Until y=0, the subroutine is terminated, let variable y=n, and control the first multiplexing switch 12 to reset, at which time T a ＝t 3 +t 2 +t 1 +t 0 ，T a ＜T 2 If T appears in the execution process of the subprogram a ＝T 2 (since the first counter 3 and the second counter 4 are clocked simultaneously, if T occurs a ＝T 2 It is explained that the second time counter 4 has counted up to T 2 ) The charge compensation is immediately ended.
(5) The variable z=z-1 is started to time the first time counter 3, the first program controlled multi-way switch 12 closes the channel A, the measured voltage signal is buffered by the first voltage buffer 11 and then converted into charging current through the first current limiting resistor 10, and the charging current is input into the integrator formed by the first operational amplifier 9 and the first integrating capacitor 7 for charging until the first time counter 3 is full of T 1 Stopping after the time; the controller simultaneously controls the second integrating circuit to execute the charge compensation subroutine while executing the above-described process in this step, including:
the second program-controlled multi-way switch 20 closes the channel A, and after the reference voltage signal is buffered by the second voltage buffer 19, the reference voltage signal is converted into charging current through the second current limiting resistor 18 and is input into the first integrator;
let variable y=y-1, and let the output amplitude of the programmable voltage reference source 1 be x by detecting the polarity of the output level of the second zero-crossing comparator 16 and the value of variable y y ×|V ref The voltage of opposite polarity to the measured voltage signal (if the measured voltage is positive voltage, and the initial x and y are respectively set to 10 and 4, the program-controlled voltage reference source 1 outputs 1000|V ref Negative voltage, described below as this parameter), the second time counter 4 starts to count while the second programmable multiplexer 20 closes channel a until the output level of the second zero-crossing comparator 16 changes, and the integration time t is recorded 3 ；
The previous step is circulated again, and after the variable y=y-1 (in fact, the output voltage of the program-controlled voltage reference source 1 is reduced by x as the multiplying factor) is executed once every cycle, the polarity of the output voltage is changed(at this time, the program-controlled voltage reference source 1 outputs 100|V ref Positive voltage) continues to charge the second integrating capacitor until the output level of the second zero-crossing comparator 16 changes again, then the integration time t is recorded 2 Until y=0, the subroutine is terminated, the variable y=n is set, and the second multiplexing switch 20 is controlled to be reset, at which time T b ＝t 3 +t 2 +t 1 +t 0 ，T b ＜T 1 If T appears in the execution process of the subprogram b ＝T 1 (since the first counter 3 and the second counter 4 are clocked simultaneously, if T occurs b ＝T 1 It is explained that the first time counter 3 has counted up to T 1 ) The charge compensation is immediately ended and the next step is performed.
(6) And (5) repeating the step (4) and the step (5) for Z-2 times, and stopping the first integration stage.
In summary, the reference charge compensation method of the integrating analog-to-digital converter prolongs the time of the first integrating stage by inputting the reference voltage in the first integrating stage so that the integrator is not saturated all the time.
While the invention has been described in conjunction with specific embodiments, it should be understood that the foregoing description is intended to illustrate the invention and should not be construed in any way as a limitation on the scope of the invention. Other embodiments of the invention, or equivalents thereof, will suggest themselves to those skilled in the art without undue burden from the present disclosure, based on the explanations herein.
Claims (5)
1. An integrated analog-to-digital converter reference charge compensation method employing an integrated analog-to-digital converter reference charge compensation apparatus comprising:
the first integrating circuit comprises a first program-controlled multi-way switch, a first integrator and a first zero-crossing comparator which are sequentially connected in series, wherein the first program-controlled multi-way switch comprises at least two input ends and an output end;
the second integrating circuit comprises a second program-controlled multi-way switch, a second integrator and a second zero-crossing comparator which are sequentially connected in series, wherein the second program-controlled multi-way switch comprises at least two input ends and an output end;
the program-controlled voltage reference source is used for outputting adjustable reference voltages to the first integrating circuit and the second integrating circuit, and is electrically connected with the first input end of the first program-controlled multi-way switch and the first input end of the second program-controlled multi-way switch at the same time;
the tested voltage signal input end is electrically connected with the second input end of the first program-controlled multi-way switch and the second input end of the second program-controlled multi-way switch at the same time;
a timing module for measuring the integration time T of the first and second integration circuits 1 And T 2 And the actual time T of reference charge compensation a And T b ；
A controller configured to control operation of the programmable voltage reference source, the first programmable multiplexing switch, the second programmable multiplexing switch, and the timing module based on the first and second zero-crossing comparator output signals;
the method is characterized by comprising the following steps of:
step 1, a voltage signal to be measured is connected into a first integrating circuit to charge a first integrating capacitor, wherein the charging time is a fixed time T 1 ；
Step 2, the measured voltage signal is connected to a second integrating circuit to charge a second integrating capacitor, wherein the charging time is a fixed time T 2 Simultaneously, a program-controlled voltage reference source is connected into a first integrating circuit to carry out charge compensation on a first integrating capacitor, and the compensation time T is recorded a Wherein the T is 2 ≥T a ；
Step 3, the measured voltage is signaledThe number is connected into the first integrating circuit to charge the first integrating capacitor, and the charging time is fixed time T 1 Simultaneously, a program-controlled voltage reference source is connected into a second integrating circuit to carry out charge compensation on a second integrating capacitor, and the compensation time T is recorded b Wherein the T is 1 ≥T b ；
Step 4, repeatedly executing the step 2 and the step 3 for a plurality of times, and ending the first integration phase, thereby prolonging the integration time of the first integration phase;
the specific steps of charge compensation in step 2 include:
a1: setting an initial voltage amplitude of a program-controlled voltage reference source through a controller and enabling the polarity of the program-controlled voltage reference source to be opposite to that of the measured voltage signal;
a2: the reference source of the programmable power supply is connected into a first integrating circuit to carry out charge compensation on a first integrating capacitor, and the output level change of a first zero-crossing comparator and the count value of a first time counter are detected at the same time, if the compensation time T a ＝T 2 Ending the charge compensation, proceeding to step 3, if the compensation time T a ＜T 2 And the output level of the first zero-crossing comparator changes, and then the step A3 is continuously executed;
a3: reducing the amplitude of the output voltage of the program-controlled voltage reference source by a fixed multiplying power x, changing the polarity, and then returning to the step A2;
the specific steps of the charge compensation in the step 3 include:
b1: setting an initial voltage amplitude of a program-controlled voltage reference source through a controller and enabling the polarity of the program-controlled voltage reference source to be opposite to that of the measured voltage signal;
b2: the reference source of the programmable power supply is connected into a second integrating circuit to carry out charge compensation on a second integrating capacitor, and the output level change of a second zero-crossing comparator and the count value of a second time counter are detected at the same time, if the compensation time T b ＝T 1 Ending the charge compensation, proceeding to step 4, if the compensation time T b ＜T 1 And the output level of the second zero-crossing comparator changes, and then the step B3 is continuously executed;
b3: and (2) reducing the amplitude of the output voltage of the program-controlled voltage reference source by a fixed multiplying power x, changing the polarity, and then returning to the step (B2).
2. The method of claim 1, wherein the step A3 further comprises: reducing the amplitude of the output voltage of the program-controlled voltage reference source by a fixed multiplying power x and changing the polarity, if the amplitude of the output voltage of the program-controlled voltage reference source is larger than or equal to iV ref And I, returning to execute A2, otherwise, disconnecting the program-controlled voltage reference source signal and waiting for the charging time of the second integrating capacitor to be T 2 Step 3 is then continued, wherein |V ref The l is characterized as the reference voltage corresponding to the minimum reference charge compensation rate.
3. The method of claim 1, wherein the step B3 further comprises: reducing the amplitude of the output voltage of the program-controlled voltage reference source by a fixed multiplying power x and changing the polarity, if the amplitude of the output voltage of the program-controlled voltage reference source is larger than or equal to iV ref And (3) returning to the step B2, otherwise, disconnecting the program-controlled voltage reference source signal and waiting for the charging time of the second integrating capacitor to be T 1 Step 4 is then continued, wherein |V ref The l is characterized as the reference voltage corresponding to the minimum reference charge compensation rate.
4. The method of claim 1, wherein the fixed time T in step 1 and step 3 1 And the fixed time T of step 2 2 Are set equal.
5. The method of claim 1, further comprising the step of initializing prior to performing step 1: and clearing residual charge release in the first integrating capacitor and the second integrating capacitor through the first charge release circuit and the second charge release circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111014320.9A CN113852372B (en) | 2021-08-31 | 2021-08-31 | Reference charge compensation method and device for integral analog-to-digital converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111014320.9A CN113852372B (en) | 2021-08-31 | 2021-08-31 | Reference charge compensation method and device for integral analog-to-digital converter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113852372A CN113852372A (en) | 2021-12-28 |
| CN113852372B true CN113852372B (en) | 2024-02-02 |
Family
ID=78976808
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111014320.9A Active CN113852372B (en) | 2021-08-31 | 2021-08-31 | Reference charge compensation method and device for integral analog-to-digital converter |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113852372B (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5897919A (en) * | 1981-12-05 | 1983-06-10 | Advantest Corp | Calibrating method of multi-slope integrating ad converter |
| JPS58107721A (en) * | 1981-12-22 | 1983-06-27 | Yokogawa Hokushin Electric Corp | Analog-to-digital converter |
| US4771265A (en) * | 1986-05-12 | 1988-09-13 | Minolta Camera Kabushiki Kaisha | Double integration analog to digital converting device |
| JPH09205367A (en) * | 1996-01-29 | 1997-08-05 | New Japan Radio Co Ltd | Integration a/d conversion method |
| JP2012114501A (en) * | 2010-11-19 | 2012-06-14 | Panasonic Corp | Double integral a/d converter |
| JP2013187784A (en) * | 2012-03-08 | 2013-09-19 | Panasonic Corp | Analog-digital conversion device |
| CN105406869A (en) * | 2014-09-10 | 2016-03-16 | 凹凸电子（武汉）有限公司 | Coulomb counting using analog-to-frequency conversion |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7038610B2 (en) * | 2001-07-19 | 2006-05-02 | Rohm Co., Ltd. | Integration type A/D converter, and battery charger utilizing such converter |
-
2021
- 2021-08-31 CN CN202111014320.9A patent/CN113852372B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5897919A (en) * | 1981-12-05 | 1983-06-10 | Advantest Corp | Calibrating method of multi-slope integrating ad converter |
| JPS58107721A (en) * | 1981-12-22 | 1983-06-27 | Yokogawa Hokushin Electric Corp | Analog-to-digital converter |
| US4771265A (en) * | 1986-05-12 | 1988-09-13 | Minolta Camera Kabushiki Kaisha | Double integration analog to digital converting device |
| JPH09205367A (en) * | 1996-01-29 | 1997-08-05 | New Japan Radio Co Ltd | Integration a/d conversion method |
| JP2012114501A (en) * | 2010-11-19 | 2012-06-14 | Panasonic Corp | Double integral a/d converter |
| JP2013187784A (en) * | 2012-03-08 | 2013-09-19 | Panasonic Corp | Analog-digital conversion device |
| CN105406869A (en) * | 2014-09-10 | 2016-03-16 | 凹凸电子（武汉）有限公司 | Coulomb counting using analog-to-frequency conversion |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113852372A (en) | 2021-12-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6243034B1 (en) | Integrating analog to digital converter with improved resolution | |
| CN103888141B (en) | Streamline gradually compares the method for self-calibrating and device of analog-digital converter | |
| US7812619B2 (en) | Capacitance measuring apparatus and capacitance measuring method | |
| US5754041A (en) | Device for measuring voltage/current characteristics with means to prevent output transients during changes in settings | |
| US4357600A (en) | Multislope converter and conversion technique | |
| JPH05196510A (en) | Method for obtaining measured quantity and circuit device for performing this method | |
| US9692434B2 (en) | Analog to digital converter | |
| US7724014B2 (en) | On-chip servo loop integrated circuit system test circuitry and method | |
| JP6270403B2 (en) | Semiconductor device and electronic control device | |
| CN104640053A (en) | Direct-current impedance detecting method of loudspeaker, circuit and D type audio frequency amplifier | |
| CN113852372B (en) | Reference charge compensation method and device for integral analog-to-digital converter | |
| GB2408808A (en) | Electric power meter with phase shift compensation | |
| US11057047B2 (en) | Ratiometric gain error calibration schemes for delta-sigma ADCs with capacitive gain input stages | |
| CN106771472A (en) | Method and apparatus for measuring the average inductor current for passing to load | |
| CN113839677B (en) | Integral analog-to-digital converter and analog-to-digital conversion method thereof | |
| US5614902A (en) | Ratiometric analog to digital converter with automatic offset | |
| US5148171A (en) | Multislope continuously integrating analog to digital converter | |
| US3745556A (en) | Analogue to digital converter | |
| US20200162071A1 (en) | Switching Circuit | |
| RU2602351C1 (en) | Voltage-to-pulse frequency converter | |
| CN219676122U (en) | Dynamic parameter testing device | |
| RU2790350C1 (en) | Method for extending the range of current measured by an analogue signal converter | |
| CN116148744B (en) | Hybrid inductive current sensor capable of being calibrated online and calibration method thereof | |
| US11417412B1 (en) | Cell trace circuit for measuring I-V property of memory cell | |
| KR20110057678A (en) | A ramp generation circuit for using a current shunt method in cmos image sensor and the image sensor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |