JP2012114501A - Double integral a/d converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a double integral A/D converter that can convert a bipolar input voltage and can prevent an outlier from being output as a digital value.SOLUTION: The double integral A/D converter capable of converting a bipolar input voltage includes correction means 8 for resetting to zero a count value of a counter 4 for counting constant period clock pulses within a second integration period of integration of a first referential voltage Vhigher than the reference voltage Vor a second referential voltage Vlower than the reference voltage Vand outputting as a digital value the count value on the return of an output voltage Vof an integrator 1 to a reference voltage V, if the counter 4 overflows, while the output voltage Vof the integrator 1 is within a range V-Vbetween a first comparative reference voltage Vhigher than the reference voltage Vand a second comparative reference voltage Vlower than the reference voltage Vjust before the end of a first integration period of integration of an input voltage V.

Description

  The present invention relates to a double integration type A / D converter.

  2. Description of the Related Art Conventionally, a double integration type A / D converter using an integrator is known as a kind of A / D converter that converts an analog value into a digital value. As a double integration type A / D converter, one capable of converting a bipolar (bipolar) input voltage into a digital value is known (for example, Patent Document 1).

  In a double integration type A / D converter capable of converting a bipolar input voltage, an integrator having a resistor, a capacitor, and an operational amplifier integrates the input voltage to be converted for a predetermined first integration period. Integrates a reference voltage that is opposite in polarity to the input voltage. Here, the integrator operates so that the output voltage returns to the reference voltage (for example, 0 V) in the second integration period in which the reference voltage is integrated. Note that the time until the output voltage of the integrator returns to the reference voltage in the second integration period is also called a discharge period.

  In addition, a double integration type A / D converter capable of converting a bipolar input voltage includes an integrator and a plurality of analog switches, and the integrator includes an input voltage, a first reference voltage, and a second reference voltage. An input switching unit that selectively inputs one of the above, a comparator (comparator) that compares the output voltage of the integrator with a reference voltage, a control unit that controls the input switching unit and the integrator, and an output of the comparator And a counter that counts clock pulses with a constant period only during the discharge period and outputs the count value as a digital value. Here, the control unit determines the polarity of the output voltage in the first integration period of the integrator based on the output of the comparator, and based on the determination result, the first reference of the polarity opposite to the input voltage is input to the integrator. The input switching unit is controlled so that the voltage or the second reference voltage is input.

  The double-integration A / D converter that can convert the input voltage of both polarities is the output of the integrator compared to the double-integration A / D converter that can convert only the unipolar (monopolar) input voltage. The wide voltage range has the advantage that the dynamic range of the input voltage can be widened, and the short discharge period in the integrator has the advantage that the conversion rate can be increased.

JP 2002-271203 A

  In the double integration type A / D converter capable of converting a bipolar input voltage, the inventors of the present application may generate an abnormal value as a digital value when the input voltage of the integrator is near the reference voltage. I got the knowledge that there is.

  The present invention has been made in view of the above-described reasons, and an object of the present invention is to convert bipolar input voltages and to prevent output of abnormal values as digital values. An object of the present invention is to provide a double integration type A / D converter.

  The double integration type A / D converter of the present invention is a double integration type A / D converter capable of converting a bipolar input voltage, immediately before the end of the first integration period for integrating the input voltage. A first reference voltage in which the output voltage of the integrator is in a range between a first comparison reference voltage higher than a reference voltage and a second comparison reference voltage lower than the reference voltage and higher than the reference voltage. Alternatively, in a second integration period in which a second reference voltage lower than the reference voltage is integrated, clock pulses having a constant period are counted, and a count value until the output voltage of the integrator returns to the reference voltage is output as a digital value. When the counter overflows, there is provided correction means for resetting the count value of the counter to zero.

  In the double integration type A / D converter, a plurality of analog switches are provided, and any one of the input voltage, the first reference voltage, and the second reference voltage is input to the integrator. An input switching unit to be used; a comparator that compares the output voltage of the integrator with the reference voltage; and whether or not the output voltage of the integrator is within the range immediately before the end of the first integration period. A window comparator, and a control unit that controls at least the input switching unit and the counter, wherein the control unit is configured to adjust an output voltage of the integrator based on an output of the comparator immediately after the first integration period ends. A function of determining the polarity based on the magnitude of the reference voltage and controlling the input switching unit according to the polarity of the determination result; and the second integration period after the start of the second integration period A function of stopping the counting operation of the counter when the output of the comparator is inverted, and a function of adding a sign representing a polarity opposite to the polarity of the determination result to the count value of the counter, The correction means resets the count value of the counter to zero when the output voltage of the integrator is determined to be within the range by the window comparator and the overflow flag of the counter is set. Is preferred.

  In the double integration type A / D converter, the window comparator includes a first comparator that compares an output voltage of the integrator with the first comparison reference voltage, an output voltage of the integrator, and the first comparator. It is preferable to have a second comparator that compares the two comparison reference voltages.

  The double integration type A / D converter includes a first analog switch for turning on and off the input of the reference voltage to a reference voltage input terminal of the comparator, and the window comparator includes the comparator and the comparator. A second analog switch for turning on / off the input of the first comparison reference voltage to the reference voltage input terminal, and a third analog switch for turning on / off the input of the second comparison reference voltage to the reference voltage input terminal of the comparator It is preferable that the control unit has a function of controlling the window comparator and alternatively turns on the first to third analog switches.

  In the double integration type A / D converter, the control unit includes the first analog switch, the third analog switch, and the first analog switch in order of the first analog switch during an operation period of the comparator. The third analog switch is turned on alternatively, or the first analog switch, the second analog switch, and the first analog switch in this order. Is preferably turned on alternatively.

  In the double integration type A / D converter, it is preferable that the first reference voltage is also used as the first comparison reference voltage and the second reference voltage is also used as the second comparison reference voltage. .

  In the double integration type A / D converter, when the first integration period is T1, and the time from the start of the first integration period to just before the end of the first integration period is T12, the first integration period The difference between the reference voltage of each of the comparison reference voltage and the reference voltage of the second comparison reference voltage is not more than (T12 / T1) times the output voltage of the integrator corresponding to the preset maximum output value of the counter. It is preferable that it is set.

  In the double integration type A / D converter, it is preferable that the first comparison reference voltage and the second comparison reference voltage are generated from the reference voltage.

  In the double integration type A / D converter of the present invention, it is possible to convert bipolar input voltages and prevent an abnormal value from being output as a digital value.

FIG. 3 is a circuit diagram of the double integration A / D converter according to the first embodiment. It is operation | movement explanatory drawing same as the above. It is operation | movement explanatory drawing same as the above. 6 is a circuit diagram of a double integration type A / D converter of Embodiment 2. FIG. It is operation | movement explanatory drawing same as the above.

(Embodiment 1)
Hereinafter, the double integration type A / D converter of this embodiment will be described with reference to FIGS.

Double integral type A / D converter of the present embodiment is capable of converting both polarities of input voltage V _in analog (bipolar) into a digital value.

The double integration type A / D converter of the present embodiment includes an integrator 1 and an input switching unit 2 that switches an input to the integrator 1. The double integration type A / D converter includes a comparator 3 that compares the output voltage V _out of the integrator 1 with a reference voltage V _AGND, and a counter that counts clock pulses with a constant period and outputs the count value as a digital value. 4 is provided. Further, the double integration type A / D converter includes a control unit 5 having a function of controlling the integrator 1, the input switching unit 2, and the counter 4. The control unit 5 may be configured by a microcomputer equipped with an appropriate program, or may be configured by a combination of a timing control circuit and a plurality of circuits each designed to realize a desired function. Also good.

The integrator 1 includes an operational amplifier OP1, a resistor (input resistance) R is connected to the inverting input terminal of the operational amplifier OP1, and a capacitor C is connected between the inverting input terminal and the output terminal of the operational amplifier OP1. ing. Here, the integrator 1 is configured such that the potential of the non-inverting input terminal of the operational amplifier OP1 is set to the reference voltage V _AGND . In short, the integrator 1 has a configuration of an inverting integrator using the operational amplifier OP1, the resistor R, and the capacitor C, and has a series circuit of the resistor R and the capacitor C.

In contrast, the input switching section 2, either the input voltage V _in and the first opposite polarity from that of the input voltage V _in of the reference voltage V _{REF +} or the second reference voltage V _REF- the integrator 1 It has a configuration that can be alternatively input. Here, the first reference voltage V _{REF +} is a voltage higher than the reference voltage V _AGND by a predetermined voltage V _ref , and is V _{REF +} = V _AGND + V _ref , and the second reference voltage V _REF− is the reference voltage The voltage is lower than the voltage V _AGND by a predetermined voltage V _ref , and V _REF− = V _AGND −V _ref .

Input switching unit 2, the first input voltage V _in is an analog switch SW1 provided between the input terminal of the input (not shown) and the integrator 1, the first reference voltage V _{REF +} is input An analog switch SW2 provided between a reference voltage terminal (not shown) and the integrator 1, a second reference voltage terminal (not shown) to which the second reference voltage V _REF− is input, and the integrator 1 And an analog switch SW3 provided between the two. In short, the input switching unit 2 includes a plurality of analog switches SW1 to SW3.

The input voltage V _in applied to the input terminal of the above, for example, a sensor (not shown) (e.g., an infrared sensor, etc.) (not shown) the output voltage of the preamplifier is a voltage signal obtained by amplifying the like. Further, a reference voltage source (not shown) that outputs a reference voltage V _AGND is connected to a reference voltage terminal to which a non-inverting input terminal of the operational amplifier OP1 is connected. Further, a first reference voltage source (not shown) that outputs a first reference voltage V _{REF +} is connected to the first reference voltage terminal, and a second reference is connected to the second reference voltage terminal. A second reference voltage source (not shown) that outputs the voltage V _REF− is connected. Here, it is preferable that the first reference voltage V _{REF +} and the second reference voltage V _REF− are generated from the reference voltage V _AGND . That is, the first reference voltage source and the second reference voltage source generate the first reference voltage V _{REF +} and the second reference voltage V _REF− from the reference voltage V _AGND output from the reference voltage source. preferable. For example, a reference voltage generation circuit is preferably used as the reference voltage source.

Integrator 1 described above, the input voltage V _in the first integration period T1 (see FIGS. 2 and 3) after integration by the first reference opposite polarity to the input voltage V _in the reference voltage V _AGND The voltage V _{REF +} or the second reference voltage V _REF− is integrated. Here, the integrator 1 discharges the capacitor C during the second integration period T2 (see FIGS. 2 and 3) in which the first reference voltage V _{REF +} or the second reference voltage V _REF− is integrated. .

Control unit 5, the first integration period T1, the input voltage V _in via the resistor R to the inverting input terminal of the operational amplifier OP1 is inputted to the second integration period T2, the inverting input terminal of the operational amplifier OP1 The input switching unit 2 is controlled so that the first reference voltage V _{REF +} or the second reference voltage V _REF− is input via the resistor R. Here, the control unit 5 outputs control signals S1 to S3 for controlling on / off of the analog switches SW1 to SW3. The control unit 5 determines the polarity based on the magnitude of the output voltage V _out of the integrator 1 with _respect to the reference voltage V _AGND based on the output V ₃ of the comparator 3 immediately after the end of the first integration period T1, and the polarity of the determination result The input switching unit 2 is controlled according to the function. Here, the control unit 5 determines the polarity of the output voltage V _out of the integrator 1 based on the output V _{3 of the} comparator 3. Specifically, the control unit 5, immediately after the first integration period T1 is finished, the output voltage V _out of the integrator 1 when the output V ₃ of the comparator 3 is at the H level plus (the input voltage V _in determining the polarity negative) and determines the polarity of the output voltage V _out of the integrator 1 minus (the input voltage V _in when the output V ₃ of the comparator 3 is at the L level plus) and. Then, the control unit 5 applies either one of the first reference voltage V _{REF +} and the second reference voltage V _REF− to the integrator 1 according to the polarity determination result for the output voltage V _out of the integrator 1. Is controlled so as to be input. In short, the control unit 5 causes the integrator 1 to input the first reference voltage V _{REF +} when the output V ₃ of the comparator ₃ is at the H level immediately after the end of the first integration period T 1, and outputs the output of the comparator 3. When V ₃ is at L level, the second reference voltage V _REF− is input to the integrator 1.

Thus, the first integration period T1 of the integrator 1, the capacitor C is charged first current determined by the capacitance value of the input voltage V _in a capacitor C and the resistance value of the resistor R flows, the second integration In the period T2, a second current determined by the first reference voltage V _{REF +} or the second reference voltage V _REF− , the capacitance value of the capacitor C, and the resistance value of the resistor R flows, and the charge of the capacitor C is discharged. The

  In the integrator 1, a reset analog switch SW4 is connected in parallel to the capacitor C. Therefore, the integrator 1 can provide a reset period T0 (see FIG. 3) for discharging the residual charge of the capacitor C by turning on the reset analog switch SW4. On / off of the analog switch SW4 is controlled by the control signal S4 from the control unit 5 described above. The count value of the counter 4 is read in a reading period T3 (see FIGS. 2 and 3) after the second integration period T2.

  The controller 5 controls the on / off timings of the analog switches SW1 to SW4 so that the reset period T0, the first integration period T1, the second integration period T2, and the readout period T3 are cyclically repeated. Therefore, the conversion rate of the double integration type A / D converter of this embodiment is determined by the total time of the reset period T0, the first integration period T1, the second integration period T2, and the readout period T3. Each of the analog switches SW1 to SW4 is preferably configured by an n-channel MOS transistor, which can reduce the on-resistance and enable high-speed operation as compared with the case where the analog switches SW1 to SW4 are configured by a p-channel MOS transistor.

The above-described counter 4 counts clock pulses from the clock pulse generator 6 that outputs clock pulses having a constant period. The counter 4 is reset by a reset signal from the control unit 5 during the reset period T0 of the integrator 1, and operates simultaneously with the start of the second integration period T2 of the integrator 1 (counting) by the count start signal from the control unit 5. The operation (counting operation) is ended when the output V _{3 of the} comparator 3 changes (inverts) thereafter. Therefore, the counter 4 counts clock pulses only during the discharge period T4 until the output voltage _Vout of the integrator 1 returns to the reference voltage V _AGND in the second integration period T2, and outputs the count value as a digital value. Here, the control unit 5 has a function of adding a sign representing the polarity of the determination result to the count value of the counter 4. Specifically, for example, a sign addition circuit for adding a sign (+, −) indicating polarity to the count value of the counter 4 is provided in the subsequent stage of the counter 4, and the count value is controlled by the control unit 5 controlling the sign addition circuit. A code may be added to.

The absolute value of the output voltage V _out of the integrator 1 increases with a slope proportional to the value of the input voltage Vin _in the first integration period T1, and decreases with a constant slope in the second integration period T2, so that the discharge the length of the period T4 is proportional to the input voltage V _in. More specifically, when the output voltage _Vout of the integrator 1 at the end of the first integration period T1 is Va,
Va = − (T1 · V _in ) / (C · R) (Formula 1)
It becomes. Therefore, the first integration period T1 is
T1 = (C · R) · Va / V in ( Equation 2)
It becomes. On the other hand, the discharge period T4 is
T4 = (CR) Va / _Vref (Formula 3)
It becomes. From Equation 2 and Equation 3,
V _in = (T4 / T1) · V _ref
It becomes. Accordingly, the count value of the counter 4, a value proportional to the input voltage V _in. The second integration period T2 of the integrator 1 may be determined based on a time constant determined by the capacitance value of the capacitor C of the integrator 1 and the resistance value of the resistor R.

  As the counter 4, a 12-bit counter is used. Here, when the count value overflows (when the count value is saturated with FFFh), the counter 4 has an overflow flag set (becomes H level). The counter 4 is not limited to a 12-bit counter, and for example, an 8-bit counter or a 16-bit counter may be used. Further, the clock pulse generation unit 6 may be constituted by, for example, an oscillator or a clock pulse generation circuit.

The full scale of the output voltage V _out of the integrator 1 corresponds to the full scale (maximum output value) of the digital value output from the double integration type A / D converter (in this embodiment, output from the counter 4). This is the output voltage width of the integrator 1.

Double integral type A / D converter of this embodiment includes a first comparison reference voltage V _H higher than the output voltage V _out and the reference voltage V _AGND of the integrator 1 immediately before the first integration period T1 ends range of the reference voltage V _AGND second comparison reference voltage V _L is lower than (hereinafter, referred to as the specified range) is within V _H ~V _L, and the count of clock pulses with a constant period in the second integration period T2 When the counter 4 that outputs the count value as a digital value overflows, the correction means 8 is provided for resetting the count value of the counter 4 to zero. The correction means 8 will be described later.

  By the way, the inventor of the present application has obtained the following knowledge when conducting research and development on a basic example in which the control unit 5 does not have the above-described correction function in the double integration type A / D converter of this embodiment. .

An input voltage V _in of the double integral type A / D converter basic example the output voltage of the infrared sensor for detecting the temperature of an object is amplified by a preamplifier, a double integral type A / D converter of the basic example It has been found that an abnormal value may occur when the temperature of an object is obtained by calculation using an appropriate arithmetic expression using the output digital value. That the temperature obtained by this calculation is an abnormal value means that the digital value obtained by the double integration type A / D converter is an abnormal value.

  Here, as the infrared sensor, a sensor provided with a thermopile having a negative characteristic in which the output voltage decreases as the temperature of the object rises is used as the temperature sensing unit. And when this inventor changes the temperature of the black body as an object continuously, the relationship between the temperature of a black body and the output voltage of the infrared sensor converted from the temperature calculated | required by the said computing equation is shown. As a result of the investigation, it was found that there is a case where a value jump may occur in the output voltage of the converted infrared sensor. That is, it has been found that the converted output voltage of the infrared sensor may cause a jump in the middle of the continuous change of the temperature of the black body.

The inventors have further conducted extensive studies and repeated experiments, the value of the input voltage V _in with various changes were comparing the count value of the value and the counter 4 of the input voltage V _in, the abnormal value occurs the input voltage V _in of the integrator 1 is near the reference voltage V _AGND, and the overflow flag counter 4 to the second integration period T2 is if it was set to obtain a finding that. Further, the output voltage V _out of the integrator 1, the reference voltage V _AGND, output V ₃ of the comparator 3, the results obtained by measuring the respective waveform by an oscilloscope, when the input voltage V _in of the integrator 1 is near the reference voltage V _AGND the output voltage V _out of the integrator 1, the output V ₃ chattering has occurred in each of the waveform of the comparator 3, the second integration period T2, the output voltage V _out of the integrator 1 is, first integration period T1 It was found that a phenomenon may occur in which the output voltage V _out of the integrator 1 has the same polarity as that of the average value at the end of the period and changes from the reference voltage V _AGND with time. However, since the output voltage V _out of the integrator 1 and the reference voltage V _AGND fluctuate randomly due to thermal noise, it is assumed that the same phenomenon may occur due to thermal noise even without chattering. . Therefore, the present inventor has for the cause of abnormal value occurs, in other words the control unit 5 is determined polarity of the output voltage V _out of the integrator 1 is false (the polarity of the input voltage V _in of the integrator 1 misjudgment It was estimated that this was due to a phenomenon that the count value of the counter 4 overflowed.

In contrast, in the double integration type A / D converter of the present embodiment, the output voltage _Vout of the integrator 1 is within the specified range _{VH to VL} immediately before the end of the first integration period T1. A window comparator 7 for determining whether or not and the correction means 8 described above are provided. Thereby, in the double integration type A / D converter of the present embodiment, the correcting means 8 determines that the output voltage V _out of the integrator 1 is within the specified range V _{H to} V _L by the window comparator 7. When the overflow flag of the counter 4 is set, the count value of the counter 4 is reset to zero. That is, the correction unit 8 resets the counter 4 by giving a reset signal to the counter 4 during the readout period T3, and outputs the count value of the counter 4 as zero.

The window comparator 7 has an operation start timing controlled by the rising edge of the trigger signal from the control unit 5, and the output voltage V _out of the integrator 1 is set to the specified range V just before the end of the first integration period T 1 of the integrator 1. It is determined whether it is within _{H to} V _L.

The window comparator 7 includes a first comparator 71 that compares the output voltage V _out of the integrator 1 with the first comparison reference voltage V _H, and the output voltage V _out of the integrator 1 and the second comparison reference voltage V _L. And a second comparator 72 for comparing the two. Further, the window comparator 7 is provided with a logic circuit 73 which receives the output V ₇₁ of the first comparator 71 and an output V ₇₂ of the second comparator 72. Here, as shown in the truth table of Table 1 below, the logic circuit 73 is only in the case where the output V ₇₁ of the first comparator ₇₁ is L level and the output V ₇₂ of the second comparator ₇₂ is H level. What is necessary is just to comprise so that the output V73 (output _{V7 of the} window comparator ₇ ) of the logic circuit 73 may become H level.

Correcting means 8, for example, the output V ₇ is H-level window comparator 7, and the overflow flag of the counter 4 when the H-level, can be constituted by a logic circuit to output a reset signal of H level. The correction unit 8 may be provided in the control unit 5. Further, the above-described clock pulse generation unit 6 may also be provided in the control unit 5.

  An example of the basic operation of the double integration type A / D converter of this embodiment will be described with reference to FIG.

Figure 2 is an explanatory view of a case where the polarity is negative the input voltage V _in of the integrator 1, the operation example in which the polarity of the output voltage V _out of the integrator 1 is determined normally (1) - (3 ) And an operation example (4) when the polarity of the output voltage V _out of the integrator 1 is erroneously determined.

The operation example (1) is an example when the output voltage V _out of the integrator 1 at the time when the first integration period T1 ends is higher than the first comparison reference voltage V _H and does not reach full scale. is there. In this operation example (1), the output V ₇ of the window comparator 7 immediately before the end of the first integration period T1 is L level, and the overflow flag of the counter 4 is L level in the reading period T3. Therefore, the correction unit 8 does not output a reset signal. As a result, the count value of the counter 4 is counted in a period (corresponding to the discharge period T4) until the output V3 of the comparator ₃ is inverted in the second integration period T2 after the start of the second integration period T2. The number of pulses.

Further, in the operation example (2), when the output voltage V _out of the integrator 1 at the time when the first integration period T1 ends is lower than the first comparison reference voltage V _H and higher than the reference voltage V _AGND. It is an example. In this operation example (2), the output V ₇ of the window comparator 7 immediately before the end of the first integration period T1 is H level, and the overflow flag of the counter 4 is L level in the reading period T3. Therefore, the correction unit 8 does not output a reset signal. As a result, the count value of the counter 4 is the clock counted during the period (corresponding to the discharge period T4) until the output V3 of the comparator ₃ is inverted in the second integration period T2 after the start of the second integration period T2. The number of pulses.

The operation example (3) is an example when the output voltage _Vout of the integrator 1 exceeds the full scale at the time when the first integration period T1 ends. In this operation example (3), the output V ₇ of the window comparator 7 immediately before the end of the first integration period T1 is L level, and the overflow flag of the counter 4 is H level in the reading period T3. Therefore, the correction unit 8 does not output a reset signal. As a result, the count value of the counter 4 becomes the number of clock pulses counted in the second integration period T2.

Further, the operation example (4), the output voltage V _out of the integrator 1 at the time the first integration period T1 is finished, is higher than and the reference voltage V _AGND lower than the first comparison reference voltage V _H It is an example. In this operation example (4), the output V ₇ of the window comparator 7 immediately before the end of the first integration period T1 is H level, and the overflow flag of the counter 4 is H level in the reading period T3. Therefore, the correction means 8 outputs a reset signal. As a result, the count value of the counter 4 is reset to zero from the number of clock pulses counted in the second integration period T2.

Incidentally, FIG. 3 shows a more detailed time chart for the operation example (4), and the count value of the counter 4 is zero by the reset signal (see FIG. 3 (j)) given from the correction means 8 to the counter 4 in the reading period T3. Reset to. By the way, in the double integration type A / D converter of this embodiment, the correction means 8 is used when the output V ₇ of the window comparator ₇ is at the H level and the overflow flag of the counter 4 is at the H level as described above. And a logic circuit that outputs an H level reset signal. Here, the operation of the window comparator 7 is started by a trigger signal from the control unit 5 (see FIG. 3G). In this embodiment, the output V ₇₃ of the logic circuit 73 is latched as the output V ₇ of the window comparator 7 (see FIG. 3 (h)) when the trigger signal falls. However, the output V ₇₃ of the logic circuit 73 may be latched as the output V ₇ of the window comparator 7 when the trigger signal rises. In any case, the logic circuit 73 may be configured by a latch circuit that satisfies the truth table of Table 1 above.

2 and 3, the polarity of the input voltage V _in of the integrator 1 is an explanatory diagram in the case of a negative, when the polarity of the input voltage V _in is positive behavior of the output voltage V _out of the integrator 1 Others are the same except that the polarity is reversed.

By the way, in this embodiment, although the reference voltage V _AGND is set to 1.2V, it is not limited to this and may be 0.6V, for example. Further, in the double-integrating A / D converter of the basic example above, due to chattering of the output voltage V _out of the integrator 1 when the input voltage V _in the output voltage of the infrared sensor described above is amplified by a preamplifier The fluctuation range was about ± 40 mV. Therefore, when the double integration type A / D converter of the present embodiment is used in the same usage pattern as the basic example described above, for example, the predetermined voltage V _ref is appropriately set within a range of, for example, about 50 mV to 150 mV. You can set it. In this case, for example, the reset period T0 is 0.3 msec, the first integration period T1 is 2 msec, the second integration period T2 is 0.8 msec, the readout period T3 is 0.1 msec, and immediately before the end of the first integration period T1. However, these values are merely examples and are not particularly limited.

The above-described double integrating A / D converter of this embodiment, the integrator first output voltage V _out is the specified range V _H ~ immediately before the first integration period T1 for integrating an input voltage V _in is completed A counter 4 that is within _VL and outputs a count value until the output voltage _Vout of the integrator 1 returns to the reference voltage V _AGND as a digital value after counting clock pulses with a constant period in the second integration period T2. when overflows, due to the provision of the correction means 8 for resetting the count value of the counter 4 to zero, while the structure to allow converting an input voltage V _in bipolar, outliers as a digital value It is possible to prevent the output (reducing the possibility that an abnormal value is output).

The correcting means 8 in the double integration type A / D converter of the present embodiment determines that the output voltage V _out of the integrator 1 is within the specified range V _{H to} V _L by the window comparator 7, and When the overflow flag of the counter 4 is set, the count value of the counter 4 is reset to zero, so that it is constituted by a logic circuit that receives the output V ₇ of the window comparator 7 and the output of the overflow flag of the counter 4 as inputs. can do.

In the double integration type A / D converter of the present embodiment, the window comparator 7 includes a first comparator 71 that compares the output voltage V _out of the integrator 1 and the first comparison reference voltage V _H ; Since the second comparator 72 that compares the output voltage V _out of the integrator 1 and the second comparison reference voltage V _L is provided, the comparator 3 for A / D conversion and the window comparator 7 are separated. Since it is configured by a circuit, it is possible to reduce the influence of the window comparator 7 on the A / D conversion operation.

The reference voltage V _AGND used in the double integration type A / D converter of the present embodiment is generated by a reference voltage generation circuit, and the first comparison reference voltage V _H and the second comparison reference voltage V _L are: It is generated from the reference voltage V _AGND . Therefore, even when the reference voltage V _AGND , the first comparison reference voltage V _H , and the second comparison reference voltage V _L vary with time and temperature, the first comparison reference voltage V _H and the second comparison reference The voltage V _L varies with the same tendency as the reference voltage V _AGND . Thus, regardless of the variation of the reference voltage V _AGND, it is possible to keep the voltage difference between the first reference voltage V _H and the second comparison reference voltage V _L respective reference voltages V _AGND substantially constant .

Further, it is preferable that the first reference voltage V _{REF +} is also used as the first comparison reference voltage V _H , and the second reference voltage V _REF− is also used as the second comparison reference voltage V _L. Thereby, the reference voltage generation circuit for generating the first comparison reference voltage V _H and the second comparison reference voltage V _L can be omitted.

In addition, when the time from the start of the first integration period T1 to immediately before the end of the first integration period T1 (when the polarity determination is performed) is T12 (see FIG. 2), the first comparison reference voltage V _H and the first The difference between the reference voltage V _{AGND of} each of the two comparison reference voltages V _{L and} the reference voltage V _AGND is set to (T12 / T1) times or less of the output voltage V _out of the integrator 1 corresponding to the preset maximum output value of the counter 4. It is preferable to do. Thereby, after determining whether or not the output voltage V _out of the integrator 1 is within the specified range V _{H to} V _L by the window comparator 7, the output voltage of the integrator 1 is saturated in the first integration period T1. It is possible to prevent this from happening, and it is possible to prevent the counter 4 from being corrected to zero even though it is not necessary to correct the count value of the counter 4 to zero. However, it is preferable that the voltage difference is smaller.

  As the above-described infrared sensor, for example, a plurality of pixel portions including a temperature sensing portion and a MOS transistor for taking out an output voltage of the temperature sensing portion are arranged in a two-dimensional array on one surface side of the semiconductor substrate. It is conceivable to use one that can read out the outputs of all the temperature sensing parts in time series. In this case, a multiplexer (analog multiplexer) may be provided between the infrared sensor and the preamplifier. In addition, when using an infrared sensor whose temperature sensing part is composed of a thermopile as a temperature sensor, if a Peltier element that keeps the temperature of the cold junction constant by keeping the temperature of the semiconductor substrate constant is used, the infrared sensor The temperature can be calculated using a digital value obtained by A / D conversion after the output voltage is amplified by a preamplifier. If the temperature of the cold junction fluctuates depending on the ambient temperature without using a Peltier element, the temperature of the cold junction is measured with a thermistor, and the output voltage of the infrared sensor and the output voltage of the thermistor are preamplified. What is necessary is just to calculate temperature using each digital value obtained by A / D conversion after amplifying in (4).

  Moreover, although the infrared sensor was illustrated as a sensor, it is not restricted to an infrared sensor, For example, another physical quantity sensor, a chemical quantity sensor, etc. may be sufficient.

(Embodiment 2)
The basic configuration of the double integration type A / D converter of this embodiment is substantially the same as that of the first embodiment. As shown in FIG. 4, the reference voltage V _AGND input to the reference voltage input terminal of the comparator 3 is turned on / off. The first analog switch SW11 is provided, and the configuration of the window comparator 7 is different. In addition, the same code | symbol is attached | subjected to the component similar to Embodiment 1, and description is abbreviate | omitted suitably.

In the present embodiment, the comparator 3 described in the first embodiment is also used as a component of the window comparator 7. That is, the window comparator 7 in this embodiment includes the comparator 3, the second analog switch SW 12 that turns on and off the input of the first comparison reference voltage V _H to the reference voltage input terminal of the comparator 3, and the reference voltage of the comparator 3. And a third analog switch SW13 for turning on and off the input of the second comparison reference voltage V _L to the input terminal. Further, the window comparator 7 is configured such that the output V ₃ (V ₃₁₂ ) of the comparator 3 when the second analog switch SW12 is on is at the L level and the comparator 3 when the third analog switch SW13 is on. Only when the output V ₃ (V ₃₁₃ ) is at the H level, the logic circuit 74 having the output V ₇₄ at the H level is provided. The output V ₇₄ of the logic circuit 74 becomes the output V ₇ of the window comparator 7. It is constituted as follows.

The first analog switch SW11 is provided between the reference voltage input terminal of the comparator 3 and the first terminal 21 to which the reference voltage V _AGND is input, and the second analog switch SW12 is the reference voltage input of the comparator 3. The third analog switch SW13 is provided between the terminal and the second terminal 22 to which the first comparison reference voltage V _H is input. The third analog switch SW13 is connected to the reference voltage input terminal of the comparator 3 and the second comparison reference voltage V _L. Is provided between the third terminal 23 and the third terminal 23.

In the double integration type A / D converter of the present embodiment, the control unit 5 controls the on / off timing of the first analog switch SW11, the second analog switch SW12, and the third analog switch SW13. have. Here, the control unit 5 switches the first to third analog switches SW11 to SW13 in the order of the second analog switch SW12, the third analog switch SW13, and the first analog switch SW11 during the operation period of the comparator 3. Alternatively, the first to third analog switches SW11 to SW13 are alternatively turned on in the order of the third analog switch SW13, the second analog switch SW12, and the first analog switch SW11. . Thereby, in the double integration type A / D converter of the present embodiment, the first to third analog switches SW11 to SW13 are switched in a time division manner, and the voltage V _REF at the reference voltage input terminal of the comparator 3 is time division. Therefore, noise due to on / off of the first to third analog switches SW11 to SW13 can be reduced. Here, the second analog switch SW12 and the third analog switch SW13 are sequentially turned on immediately before the end of the first integration period T1 in the first integration period T1, and the first analog switch SW1 is connected to the second analog switch SW1. It is turned on except when the switch SW2 and the analog switch SW3 are turned on. In short, the control unit 5 includes the first to third analog switches so that the first analog switch SW1 is turned on except during a period in which the second analog switch SW12 and the third analog switch SW13 are alternatively turned on. SW1 to SW3 are turned on.

  An operation example of the double integration type A / D converter of this embodiment will be described based on an operation explanatory diagram (time chart) shown in FIG.

In the operation example shown in FIG. 5, the polarity of the input voltage V _in of the integrator 1 is negative, and the output voltage V _out of the integrator 1 at the end of the first integration period T1 is the first comparison reference. This is an example when the voltage is lower than the voltage V _H and higher than the reference voltage V _AGND .

In this operation example, the output V ₇ of the window comparator 7 is at the H level, and the overflow flag of the counter 4 is at the H level in the reading period T3. Therefore, the correction means 8 outputs a reset signal. As a result, the count value of the counter 4 is reset to zero from the number of clock pulses counted in the second integration period T2.

In the double integration type A / D converter of the present embodiment described above, the output voltage _Vout of the integrator 1 is just before the end of the first integration period T1 for integrating the input voltage Vin as _{in the} first embodiment. The count value until the output voltage _Vout of the integrator 1 returns to the reference voltage V _AGND after counting clock pulses with a fixed period within the specified range V _{H to} V _L and in the second integration period T2 is a digital value. when the counter 4 to output overflows as, by that it comprises a correction means 8 for resetting the count value of the counter 4 to zero, while the structure to allow converting an input voltage V _in bipolar, It is possible to prevent an abnormal value from being output as a digital value (reduce the possibility of an abnormal value being output).

  In the double integration type A / D converter of this embodiment, it is not necessary to add the first comparator 71 and the second comparator 72 for configuring the window comparator 7 described in the first embodiment. Compared with the case where the window comparator 7 is configured using the first comparator 71 and the second comparator 72 formed separately from the comparator 3, the circuit area and the power consumption can be reduced.

1 integrator 2 the input switching section 3 Comparator 4 counter 5 control unit 6 a clock pulse generation circuit 7 window comparator 8 correcting unit 71 first comparator 72 a second comparator 73 the logic circuit T1 first integration period T2 second integration period V _in input voltage V _out output voltage V _AGND reference voltage V _{REF +} first reference voltage V _REF- second reference voltage V _H first comparison reference voltage V _L the second comparison reference voltage SW1 analog switch SW2 analog switch SW3 analog switch SW11 First analog switch SW12 Second analog switch SW13 Third analog switch

Claims (8)

  A double integration type A / D converter capable of converting a bipolar input voltage, wherein the output voltage of the integrator is higher than the reference voltage immediately before the end of the first integration period for integrating the input voltage. Integrate a first reference voltage that is within the range of the comparison reference voltage and a second comparison reference voltage that is lower than the reference voltage and that is higher than the reference voltage or a second reference voltage that is lower than the reference voltage When a counter that outputs a count value until the output voltage of the integrator returns to the reference voltage overflows in the second integration period, and the counter value overflows, the count value of the counter is reduced to zero. A double-integrating A / D converter, comprising a correction means for resetting the power supply.   An input switching unit that includes a plurality of analog switches and selectively inputs any one of the input voltage, the first reference voltage, and the second reference voltage to the integrator; and an output voltage of the integrator A comparator for comparing the reference voltage with the reference voltage, a window comparator for determining whether the output voltage of the integrator is within the range immediately before the end of the first integration period, at least the input switching unit and the counter And a control unit that determines polarity based on the magnitude of the output voltage of the integrator with respect to the reference voltage based on the output of the comparator immediately after the end of the first integration period. The function of controlling the input switching unit according to the polarity of the result, and the output of the comparator is reversed in the second integration period after the start of the second integration period. A function to stop the counting operation of the counter and a function to add a sign representing a polarity opposite to the polarity of the determination result to the count value of the counter, and the correction means includes the window comparator 2. When the output voltage of the integrator is determined to be within the range and the counter overflow flag is set, the count value of the counter is reset to zero. The double integral A / D converter described.   The window comparator compares a first comparator that compares the output voltage of the integrator with the first comparison reference voltage, and a second comparator that compares the output voltage of the integrator and the second comparison reference voltage. The double integration type A / D converter according to claim 2, further comprising a comparator.   A first analog switch for turning on and off the input of the reference voltage to the reference voltage input terminal of the comparator; and the window comparator includes the comparator and the first comparison reference to the reference voltage input terminal of the comparator. A second analog switch that turns on and off the voltage input; and a third analog switch that turns on and off the input of the second comparison reference voltage to the reference voltage input terminal of the comparator. 3. The double integration type A / D converter according to claim 2, wherein the double integration type A / D converter has a function of controlling the window comparator and selectively turns on the first to third analog switches.   The controller alternatively selects the first to third analog switches in the order of the second analog switch, the third analog switch, and the first analog switch during an operation period of the comparator. Or turning on the third analog switch, the second analog switch, and the first analog switch in order of the third analog switch, the second analog switch, and the first analog switch. The double integration type A / D converter according to claim 4.   6. The device according to claim 1, wherein the first reference voltage is also used as the first comparison reference voltage, and the second reference voltage is also used as the second comparison reference voltage. 2. The double integration type A / D converter according to item 1.   When the first integration period is T1, and the time from the start of the first integration period to the time immediately before the end of the first integration period is T12, the first comparison reference voltage and the second comparison reference voltage The voltage difference from each of the reference voltages is set to (T12 / T1) times or less of an output voltage of the integrator corresponding to a preset maximum output value of the counter. The double integration type A / D converter according to any one of claims 1 to 6.   The double integration type A according to any one of claims 1 to 7, wherein the first comparison reference voltage and the second comparison reference voltage are generated from the reference voltage. / D converter.

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