JP2012124589A - A/d converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a more precise A/D converter.SOLUTION: A control circuit (control means) 5 has the function of controlling an input switch section 2 such that an integrator 1 selectively performs a first double integration of integrating an input voltage Vover a first integration period and then integrating a reference voltage Vover a second integration period and a second double integration of integrating a first base voltage (ground voltage) Vover the first integration period and then integrating the reference voltage Vover the second integration period. A digital circuit 7 is provided to receive a first count value comprising a count value corresponding to the second integration period in the first double integration and a second count value comprising a count value corresponding to the second integration period in the second double integration. The digital circuit 7 has the function of computing and outputting as a digital value, upon every first count value, a difference value resulting from the subtraction of an average value of the two second count values that precede and succeed the first count value from the first count value.

Description

  The present invention relates to an A / D converter.

  2. Description of the Related Art Conventionally, a sensor device includes a sensor, an amplifier circuit (preamplifier) that amplifies the output voltage of the sensor, and an A / D converter that converts an output voltage (analog value) output from the amplifier circuit into a digital value. It has been proposed (for example, Patent Document 1).

  Conventionally, a quadruple integration type A / D converter is known as a kind of A / D converter for converting an analog value into a digital value (for example, Patent Documents 2 and 3).

  In general, the quadruple integration type A / D converter includes an integrator having an operational amplifier, a resistor, and a capacitor, and includes a first period for integrating a ground voltage, a second period for integrating a reference voltage, and an input. The input of the integrator is controlled so that the third period for integrating the voltage and the fourth period for integrating the reference voltage appear cyclically. In the quadruple integration type A / D converter, the offset voltage of the operational amplifier and low frequency noise are canceled by subtracting the count value of the second period from the count value of the fourth period.

  Although the quadruple integration type A / D converter has the disadvantage that the conversion time is longer than the double integration type A / D converter, it can reduce the influence of the offset error of the operational amplifier and has low noise characteristics. There is a merit that it can be obtained.

JP 2010-237117 A U.S. Pat. No. 3,872,466 JP 2009-38433 A

  However, even the above-described quadruple integration type A / D converter may be required to have higher accuracy.

  The present invention has been made in view of the above-described reasons, and an object thereof is to provide an A / D converter capable of further improving the accuracy.

  An A / D converter according to the present invention includes an integrator having an operational amplifier, a resistor, and a capacitor, and an input voltage, a reference voltage having a polarity opposite to the input voltage, and a ground voltage are selected for the integrator. An input switching unit for inputting the input voltage, a comparator for comparing the output voltage of the integrator with a reference voltage, and integrating the input voltage in the integrator for a first integration period and then integrating the reference voltage for a second integration period. The first double integration to be performed and the second double integration to integrate the reference voltage for the second integration period after the ground voltage is integrated for the first integration period. A control unit having a function of controlling the switching unit, a counter that counts a clock pulse of a constant period and outputs a count value until the output of the comparator is inverted every second integration period; The second count value consisting of the first count value corresponding to the second integration period in the double integration and the count value corresponding to the second integration period in the second double integration. For each of the first count values, the digital circuit calculates an average value of the second count values before and after the first count value for each of the first count values. It has a function of obtaining a difference value obtained by subtracting from the count value and outputting it as a digital value.

  In this A / D converter, the control means switches the input switching so that the first double integration is performed a plurality of times during the second double integration that is arranged in time series. It is preferable to control the part.

  In the A / D converter according to the present invention, it is possible to achieve higher accuracy.

It is a circuit diagram of the A / D converter of an embodiment. It is operation | movement explanatory drawing of an A / D converter same as the above. It is a state diagram of an A / D converter same as the above. It is operation | movement explanatory drawing of the other structural example of an A / D converter same as the above. It is a state diagram of the other structural example of an A / D converter same as the above.

  As shown in FIG. 1, the A / D converter of the present embodiment includes an integrator 1, an input switching unit 2 that switches an input to the integrator 1, a comparator 3, a counter 4, and a clock pulse generator 6. And a digital circuit 7. Further, the A / D converter includes a control circuit 5 which is a control unit having a function of controlling the input switching unit 2. The control circuit 5 may be configured by a microcomputer equipped with an appropriate program, or may be configured by a combination of a timing control circuit and a plurality of circuits each designed to realize a desired function. Also good.

The integrator 1 includes an operational amplifier OP1, a resistor (input resistance) R is connected to the inverting input terminal of the operational amplifier OP1, and a capacitor C is connected between the inverting input terminal and the output terminal of the operational amplifier OP1. ing. Here, the integrator 1 is configured such that the potential of the non-inverting input terminal of the operational amplifier OP1 is set to the first reference voltage V _AGND . In short, the integrator 1 has a configuration of an inverting integrator using the operational amplifier OP1, the resistor R, and the capacitor C, and has a series circuit of the resistor R and the capacitor C. In the present embodiment, the first reference voltage V _AGND is set to the ground voltage, and the non-inverting input terminal of the operational amplifier OP1 is grounded.

In contrast, the input switching section 2, the integrator 1, alternatively any one of the input voltage V _in and the input voltage V _in is the opposite polarity of the reference voltage V _REF and the first reference voltage _AGND It is the structure which can be made to input automatically.

The input switching unit 2 includes an analog switch SW1 provided _in the input path of the input voltage Vin to the integrator 1, an analog switch SW2 provided in the input path of the reference voltage _VREF to the integrator 1, and an integrator 1 and an analog switch SW3 provided in the input path of the first reference voltage V _{AGND to} 1. Each of the analog switches SW1 to SW3 is preferably composed of an n-channel MOS transistor, which can reduce the on-resistance and enable high-speed operation as compared with the case where it is composed of a p-channel MOS transistor.

The input voltage V _in the above, for example, a sensor (not shown) (e.g., an infrared sensor, etc.) (not shown) the output voltage of the preamplifier is a voltage signal obtained by amplifying the like. The sensor is not limited to the infrared sensor, and may be a physical quantity sensor other than the infrared sensor, a chemical quantity sensor, or the like.

As shown in FIG. 2, the control circuit 5 integrates the input voltage Vin _in the integrator 1 for the first integration period T1, and then integrates the reference voltage _VREF for the second integration period T2. The output voltage V _out at this time is indicated by a solid line) and the first reference voltage (here, ground voltage) V _AGND is integrated for the first integration period T1, and then the reference voltage V _REF is integrated for the second integration period T2. It has a function of controlling the input switching unit 2 so that the second double integration (the output voltage V _out at this time is indicated by a one-dot chain line) is selectively performed. Here, the input switching unit 2 includes the above-described three analog switches SW <b> 1 to SW <b> 3, and each of the analog switches SW <b> 1 to SW <b> 3 is controlled by control signals S <b> 1 to S <b> 3 from the control circuit 5. Here, as shown in FIG. 2, the control circuit 5 has a function of controlling the input switching unit 2 so that the first double integration and the second double integration are alternately repeated in the integrator 1. Have.

  Incidentally, in the integrator 1, a reset analog switch SW4 is connected to the capacitor C in parallel. Therefore, the integrator 1 can provide the reset period T3 (see FIG. 2) in which the residual charge of the capacitor C is discharged by turning on the reset analog switch SW4. On / off of the analog switch SW4 is controlled by the control signal S4 from the control circuit 5 described above. The analog switch SW4 is preferably composed of an n-channel MOS transistor, whereby the on-resistance can be reduced and high-speed operation is possible as compared with the case where it is composed of a p-channel MOS transistor.

The above-described comparator 3 compares the output voltage V _out of the integrator 1 with the second reference voltage V _SS . The above-mentioned counter 4 counts the clock pulses from the above-mentioned clock pulse generator 6 that outputs clock pulses with a constant period, and outputs a count value. The counter 4 starts operating (counting operation) simultaneously with the start of the second integration period T2 of the integrator 1 by the count start signal from the control circuit 5, and thereafter the output of the comparator 3 changes (inverts). The operation (counting operation) is terminated. Therefore, the counter 4 counts the clock pulse only during the discharge period T4 (see FIG. 2) until the output voltage _Vout of the integrator 1 returns to the first reference voltage V _AGND in the second integration period T2, and the count value is described above. To the digital circuit 7. Here, the count value of the counter 4 is reset by a reset signal given from the control circuit 5 before the count start signal. Therefore, the counter 4 counts clock pulses with a constant period and outputs a count value until the output of the comparator 3 is inverted every second integration period T2. On the other hand, the digital circuit 7 receives the count value of the counter 4.

Accordingly, a control circuit 5 controls the input switching section 2 as described above, the first double integration first integration period T1, the resistance of the capacitance value and the resistance R of the input voltage V _in a capacitor C The first current determined by the value flows and the capacitor C is charged, and the second current determined by the reference voltage V _REF , the capacitance value of the capacitor C, and the resistance value of the resistor R flows during the second integration period T2. The electric charge of the capacitor C is discharged. The absolute value of the output voltage V _out of the integrator 1 during the first double integration increases with a slope proportional to the value of the input voltage Vin _in the first integration period T1, and in the second integration period T2. since decreases with a constant slope, the length of the discharging period T4 is proportional to the input voltage V _in. More specifically, when the output voltage _Vout of the integrator 1 at the end of the first integration period T1 in the first double integration is Va,

となる。したがって、第１の二重積分の際の第１積分期間Ｔ１は、

It becomes. Therefore, the first integration period T1 in the first double integration is

となる。一方、第１の二重積分の際の放電期間Ｔ４をＴ４_sとすると、

It becomes. On the other hand, when the discharge period T4 in the first double integration is T4 _s ,

となる。そして、（２）式および（３）式から、

It becomes. From the formulas (2) and (3),

となる。したがって、第１の二重積分における第２積分期間Ｔ２に対応するカウンタ４のカウント値（第１のカウント値）は、入力電圧Ｖ_inに比例した値となる。なお、積分器１の第２積分期間Ｔ２は、積分器１のコンデンサＣの容量値と抵抗Ｒの抵抗値とで決まる時定数に基づいて決定すればよい。

It becomes. Accordingly, the count value of the first counter 4 which corresponds to the second integration period T2 in the double integration (first count value) is a value proportional to the input voltage V _in. The second integration period T2 of the integrator 1 may be determined based on a time constant determined by the capacitance value of the capacitor C of the integrator 1 and the resistance value of the resistor R.

Further, in the first integration period T1 of the second double integration, it is determined by the noise voltage _Vos including the offset voltage of the operational amplifier OP1 and the low-frequency noise voltage, the capacitance value of the capacitor C, and the resistance value of the resistor R. The first current flows to charge the capacitor C, and in the second integration period T2, a second current determined by the reference voltage V _REF , the capacitance value of the capacitor C, and the resistance value of the resistor R flows to charge the capacitor C. Is discharged. The absolute value of the output voltage V _out of the integrator 1 during the second double integration increases with a slope proportional to the value of the noise voltage _Vos in the first integration period T1, and in the second integration period T2. Since it decreases with a constant slope, the length of the discharge period T4 is proportional to the noise voltage V _os . More specifically, when the output voltage _Vout of the integrator 1 at the end of the first integration period T1 in the second double integration is Va,

となる。したがって、第２の二重積分の際の第１積分期間Ｔ１は、

It becomes. Therefore, the first integration period T1 in the second double integration is

となる。一方、第２の二重積分の際の放電期間Ｔ４をＴ４_nとすると、

It becomes. On the other hand, when the discharging period T4 during the second double integral and T4 _n,

となる。そして、（６）式および（７）式から、

It becomes. From the equations (6) and (7),

となる。したがって、第２の二重積分における第２積分期間Ｔ２に対応するカウンタ４のカウント値（第２のカウント値）は、雑音電圧Ｖ_osに比例した値となる。

It becomes. Therefore, the count value (second count value) of the counter 4 corresponding to the second integration period T2 in the second double integration is a value proportional to the noise voltage _Vos .

  In the present embodiment, each of the first integration period T1, the second integration period T2, and the reset period T3 is a fixed value set separately. As a specific example, the first integration period T1 is set to 2 msec, the second integration period T2 is set to 0.8 msec, and the reset period T3 is set to 0.3 msec. However, these values are merely examples and are not particularly limited.

  As the counter 4, a 12-bit counter is used. The counter 4 is not limited to a 12-bit counter, and for example, an 8-bit counter or a 16-bit counter may be used. Further, the clock pulse generation unit 6 may be constituted by, for example, an oscillator or a clock pulse generation circuit. Further, the clock pulse generator 6 may be provided in the control circuit 5.

  The digital circuit 7 includes a first count value consisting of a count value corresponding to the second integration period T2 in the first double integration and a count value corresponding to the second integration period T2 in the second double integration. A count value of 2 is input.

  For each first count value, the digital circuit 7 obtains a difference value obtained by subtracting the average value of the second count values one before and after the first count value from the first count value as a digital value. It has a function to output. Here, the digital circuit 7 includes a memory 8 that appropriately stores a first count value and a second count value, and an arithmetic unit 9 that calculates an average value and a difference value. Therefore, the first count value and the second count value are appropriately stored in the memory 8 and read from the memory 8 when the arithmetic unit 9 performs an operation. The computing unit 9 obtains the above average value by dividing the addition value obtained by the adder by 2 with an adder (not shown) for adding the second count values before and after the above. A divider (not shown) and a subtracter (not shown) for subtracting the average value from the first count value are provided.

  Each time the read timing signal from the control circuit 5 is input, the digital circuit 7 performs an operation for obtaining the above-described difference value in the computing unit 9 and outputs the obtained difference value as a digital value. In short, the digital circuit 7 outputs the above-described digital value every time the read timing signal from the control circuit 5 is input. The state where the first count value is obtained by performing the first double integration is “signal sample”, and the state where the second count value is obtained by performing the second double integration is “offset low frequency noise”. If the state for obtaining the average value is called “average value calculation”, and the state for outputting the digital value is called “signal output”, the state diagram of the A / D converter is as shown in FIG. Become.

  By the way, the second count value is smaller than the first count value, and there is a high possibility that the error is larger than the first count value.

On the other hand, in the A / D converter of the present embodiment, the digital circuit 7 calculates the average value of the second count values before and after the first count value for each first count value. Since it has a function of obtaining a difference value obtained by subtracting from the count value of 1 and outputting it as a digital value, it is possible to further reduce the influence of the noise voltage V _os that determines the second count value, and further increase the accuracy. Can be achieved.

  In the above example, as shown in FIG. 2, the control circuit 5 sets the input switching unit 2 so that one first double integration and one second double integration are alternately performed. However, the present invention is not limited to this. For example, as shown in FIG. 4, the control circuit 5 performs the first double integration between two second double integrations arranged in time series. You may comprise so that it may have a function which controls the input switching part 2 so that it may be performed in multiple times (it is 3 times in the example of illustration, but it may be 2 times or more). Also in this case, the digital circuit 7 obtains a difference value obtained by subtracting the average value of the second count values one before and after the first count value from the first count value for each first count value. The point of having the function of outputting as a digital value is the same. Therefore, in the digital circuit 7, the average value of the second count value corresponding to the second integration period T2 in each of the two second double integrations arranged in time series is calculated as the second second double integration. Each difference value is output as a digital value by subtracting it separately from the first count value corresponding to the second integration period T2 in each of the multiple first double integrations performed during the integration. . The first double integration is performed three times between two second double integrations arranged in time series, and the first count value is obtained by performing the first double integration. Are called “signal sample (1)”, “signal sample (2)”, and “signal sample (3)”, respectively, and the state of obtaining the second count value by performing the second double integration is “offset low offset”. The frequency noise sample ”, the state for obtaining the above average value is called“ average value calculation ”, and the state for outputting three digital values is called“ signal (1)-(3) output ”. The state diagram of the vessel is as shown in FIG.

  In such an A / D converter, when the output of each sensor element unit is amplified by a preamplifier from a sensor having a plurality of sensor element units and sequentially input by an analog multiplexer, the accuracy of A / D conversion is improved. In spite of this, it is possible to shorten the time required to obtain digital values corresponding to the outputs of all the sensor element units. Therefore, for example, if the sensor is the infrared array sensor disclosed in Patent Document 1, the frame rate can be shortened. In the infrared array sensor disclosed in Patent Document 1, each of a plurality of pixel units including a temperature sensing unit and a MOS transistor for taking out an output voltage of the temperature sensing unit constitutes a sensor element unit.

DESCRIPTION OF SYMBOLS 1 Integrator 2 Input switching part 3 Comparator 4 Counter 5 Control circuit (control means)
6 clock pulse generator 7 digital circuit 8 memory 9 calculator T1 first integration period T2 second integration period V _in input voltage V _out output voltage V _AGND first reference voltage (ground voltage)
V _REF reference voltage V _ss second reference voltage

Claims (2)

  An integrator having an operational amplifier, a resistor, and a capacitor; and an input switching unit that causes the integrator to alternatively input one of an input voltage, a reference voltage having a polarity opposite to the input voltage, and a ground voltage; A comparator that compares the output voltage of the integrator with a reference voltage; a first double integration that integrates the reference voltage for a second integration period after integrating the input voltage in the integrator for a first integration period; and the ground Control means having a function of controlling the input switching unit so that the second double integration in which the reference voltage is integrated for the second integration period after the voltage is integrated for the first integration period is selectively performed. A counter that counts clock pulses at a constant period and outputs a count value until the output of the comparator is inverted every second integration period, and the counter in the first double integration A digital circuit to which a first count value composed of the count value corresponding to two integration periods and a second count value composed of the count values corresponding to the second integration period in the second double integration are inputted The digital circuit includes, for each of the first count values, a difference obtained by subtracting an average value of the second count values one before and after the first count value from the first count value. An A / D converter having a function of obtaining a value and outputting it as a digital value.   The control means controls the input switching unit so that the first double integration is performed a plurality of times during the two second double integrations arranged in time series. The A / D converter according to claim 1.

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