JP2017011358A - Time digital converter, analog to digital converter, and image sensor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a time digital converter capable of controlling operation timing.SOLUTION: According to an embodiment, the time digital converter includes a first converter, a holding circuit, a second converter, a time quantizer, and a control circuit. The first converter converts a first time signal into an intermediate signal having information in a form different from time. The holding circuit holds the intermediate signal. The second converter converts the intermediate signal held by the holding circuit into a second time signal. The time quantizer generates the digital signal by quantizing the second time signal using a multiphase clock signal. The control circuit controls the timing at which the intermediate signal is input to the second converter and the timing at which the multiphase clock signal is input to the time quantizer.SELECTED DRAWING: Figure 1

Description

  Embodiments relate to signal conversion.

  A column parallel readout circuit is typically used for readout of a CMOS (Complementary Metal Oxide Semiconductor) image sensor. In the column parallel readout circuit, an analog-digital converter is prepared for each column of the pixel array of the CMOS image sensor. These analog-to-digital converters operate in parallel, whereby the sensor signals for one row are converted into digital pixel data at a time.

  Although the column parallel readout circuit can realize high-speed readout, the total number of necessary analog-digital converters increases in proportion to the number of columns of the pixel array of the CMOS image sensor. Therefore, a small-area ADC (Analog-to-Digital Converter) (for example, SS (Single Slope) ADC) is preferred as the analog-digital converter mounted in the column parallel readout circuit. SSADC has a small area but is inferior in conversion speed as compared to SAR (Successive Application Register) ADC or Cyclic ADC.

  The SSADC conversion speed can be improved by increasing the frequency of the reference clock signal. However, the power consumption of the counter circuit that performs the counting operation using the reference clock signal and the clock buffer for supplying the reference clock signal to the counter circuit increases in proportion to the frequency of the reference clock signal.

  On the other hand, it is also possible to shorten the conversion time (that is, improve the conversion speed) by reducing the resolution of SSADC. For example, the resolution of SSADC can be reduced according to the resolution of TDC by allowing SSDC and a time-to-digital converter (TDC) to share the conversion of the upper bit value and the lower bit value. . However, the power consumption related to the multiphase clock signal supplied to the TDC increases according to the resolution of the TDC.

Japanese Patent No. 4389981

  An embodiment aims to provide a time digital converter capable of controlling operation timing. Alternatively, the embodiment aims to reduce power consumption when a plurality of time digital converters are operated in parallel.

  According to the embodiment, the time digital converter includes a first converter, a holding circuit, a second converter, a time quantizer, and a control circuit. The first converter converts the first time signal into an intermediate signal having information in a format different from time. The holding circuit holds the intermediate signal. The second converter converts the intermediate signal held by the holding circuit into a second time signal. The time quantizer generates a digital signal by quantizing the second time signal using the multiphase clock signal. The control circuit controls the timing at which the intermediate signal is input to the second converter and the timing at which the multiphase clock signal is input to the time quantizer.

  According to another embodiment, the time digital converter includes a first sub-digital converter and a second sub-digital converter. The first sub-digital converter converts the first time signal into a first digital signal corresponding to the upper bit value. The second sub time digital converter converts the conversion residual in the first sub time digital converter into a second digital signal corresponding to the lower bit value. The second sub time digital converter includes a detection circuit, a first converter, a holding circuit, a second converter, a time quantizer, and a control circuit. The detection circuit detects a residual time signal corresponding to the conversion residual based on the first time signal. The first converter converts the residual time signal into an intermediate signal having information in a format different from time. The holding circuit holds the intermediate signal. The second converter converts the intermediate signal held by the holding circuit into a second time signal. The time quantizer generates a second digital signal by quantizing the second time signal using the multiphase clock signal. The control circuit controls the timing at which the intermediate signal is input to the second converter and the timing at which the multiphase clock signal is input to the time quantizer.

The block diagram which illustrates the time digital converter concerning a 1st embodiment. The block diagram which illustrates the time digital converter concerning a 2nd embodiment. The block diagram which illustrates the analog-digital converter concerning a 3rd embodiment. The block diagram which illustrates the analog-digital converter concerning a 4th embodiment. FIG. 10 is a block diagram illustrating an analog-digital converter according to a fifth embodiment. The block diagram which illustrates the analog-digital converter concerning a 6th embodiment. The block diagram which illustrates the analog-digital converter concerning a 7th embodiment. FIG. 8 is a circuit diagram illustrating the charge pump circuit of FIG. 7. FIG. 9 is a diagram illustrating an operation phase of the charge pump circuit of FIG. 8 and time changes of signals related to the charge pump circuit. FIG. 8 is a circuit diagram illustrating the charge pump circuit of FIG. 7. 11 is a timing chart illustrating an operation phase of the charge pump circuit of FIG. 10 and time changes of signals related to the charge pump circuit. FIG. 10 is a circuit diagram illustrating a charge pump circuit, a ramp wave generation circuit, and a comparator included in an analog-digital converter according to an eighth embodiment. FIG. 4 is a circuit diagram illustrating the residual time detection circuit of FIG. 3. 14 is a timing chart illustrating time variation of each signal related to the residual time detection circuit of FIG. FIG. 2 is a block diagram illustrating a latch circuit in FIG. 1. FIG. 16 is a timing chart illustrating time changes of signals related to the latch circuit of FIG. 15; FIG. 20 is a block diagram illustrating an image sensor according to a ninth embodiment. The timing chart which illustrates the operation | movement phase of the time digital converter for the low-order bit signals of FIG. 3, and the time change of each signal regarding this time digital converter. The timing chart which illustrates the operation | movement phase of the time digital converter for the low-order bit signals of FIG. 3, and the time change of each signal regarding this time digital converter.

  Hereinafter, embodiments will be described with reference to the drawings. Hereinafter, the same or similar elements as those already described are denoted by the same or similar reference numerals, and redundant description is basically omitted. In the following description, the time signal is converted into a voltage signal and held. However, the time signal may be converted into an intermediate signal having information of a format different from time such as frequency, and held. Good.

(First embodiment)
The time digital converter according to the first embodiment can control the operation timing. Specifically, the time digital converter performs a conversion operation at a desired timing regardless of the input timing of the time signal, and generates a digital signal corresponding to the time signal. For example, when there is another circuit (which may be a time digital converter) that operates intermittently using a multiphase clock signal common to the time digital converter according to the present embodiment, this time The digital converter can align (synchronize) the operation timing with other circuits. According to such control, compared with the case where the multiphase clock signal is generated and supplied to the time digital converter and other circuits at different timings, the period during which the multiphase clock signal needs to be generated and supplied is shortened. Therefore, it is possible to reduce power consumption related to generation and supply of multiphase clock signals.

  As illustrated in FIG. 1, the time digital converter according to the first embodiment includes a time / voltage converter 110, a voltage holding circuit 120, a voltage / time converter 130, a timing control circuit 140, A multi-phase clock generation circuit 150 and a latch circuit 160 are included.

  The time / voltage converter 110 receives the time signal 10 from a preceding circuit (not shown). The time / voltage converter 110 then converts the time signal 10 into a voltage signal. Here, the time signal 10 is a signal having time information represented by, for example, a pulse width. The voltage signal is a signal having a voltage having a magnitude depending on the time information of the time signal 10. The time / voltage converter 110 outputs a voltage signal to the voltage holding circuit 120.

  The voltage holding circuit 120 receives the voltage signal from the time / voltage converter 110 and holds the voltage signal. Then, the voltage holding circuit 120 outputs the held voltage signal to the voltage / time converter 130 according to the timing instructed by the timing control circuit 140. The voltage holding circuit 120 may be a sample / hold circuit, for example.

  The voltage / time converter 130 receives the voltage signal from the voltage holding circuit 120 according to the timing indicated by the timing control circuit 140. The voltage / time converter 130 then converts the voltage signal into a time signal. The voltage / time converter 130 outputs a time signal to the latch circuit 160. Here, in the time signal generated by the voltage / time converter 130, substantially the same time information as that of the time signal 10 is restored.

  In the timing control circuit 140, the output timing of the voltage signal held by the voltage holding circuit 120 (in other words, the input timing of the voltage signal in the voltage / time converter 130), and the multiphase clock generation circuit 150 are described later. The timing for supplying the multiphase clock signal to the latch circuit 160 is controlled. Note that the timing control circuit 140 may be shared by the time digital converter of FIG. 1 and other circuits not shown.

The multiphase clock generation circuit 150 generates a multiphase clock signal. The multiphase clock generation circuit 150 starts supplying the multiphase clock signal to the latch circuit 160 according to the timing instructed by the timing control circuit 140. Similarly, the multiphase clock generation circuit 150 ends the supply of the multiphase clock signal to the latch circuit 160 according to the timing instructed by the timing control circuit 140. Note that the number of phases of the multiphase clock signal depends on the resolution of the time digital converter of FIG. When this resolution is M (M is a natural number), the number of phases of the multiphase clock signal is 2 ^M−1 . The multiphase clock generation circuit 150 may be shared by the time digital converter of FIG. 1 and other circuits not shown.

  The latch circuit 160 receives a time signal from the voltage / time converter 130 and receives a multiphase clock signal from the multiphase clock generation circuit 150. The latch circuit 160 generates a digital signal by quantizing the time signal using the multiphase clock signal. Note that the latch circuit 160 can also be called a time quantizer. Specifically, the latch circuit 160 holds the value of the multiphase clock signal at the timing specified by the time signal (for example, the falling edge or the rising edge of the time signal). Then, the latch circuit 160 generates the digital signal 11 by converting the value of the multiphase clock signal into a corresponding digital value.

  A specific example of the latch circuit 160 is depicted in FIG. 15 includes a latch circuit 161-1, a latch circuit 161-2, a latch circuit 161-3, a latch circuit 161-4, and a code conversion circuit 162.

  In the example of FIG. 15, as shown in FIG. 16, the multiphase clock signal corresponds to a four-phase clock signal having a duty ratio of about 50%. Since the signal value of the multiphase clock signal changes in eight stages during one cycle of a reference clock signal (not shown), time information is converted (quantized) into a 3-bit value using the multiphase clock signal. Is possible. In other words, the resolution of the time digital converter of FIG. 1 is 3 bits.

The latch circuit 161-1 receives the time signal (VTOUT) from the voltage / time converter 130, and receives the clock signal (CLK ₀ ) included in the multiphase clock signal from the multiphase clock generation circuit 150. The latch circuit 161-1 holds the value of the clock signal (CLK ₀ ) at the timing specified by the time signal (VTOUT) and outputs the value to the code conversion circuit 162.

The latch circuit 161-2 receives the time signal (VTOUT) from the voltage / time converter 130, and receives the clock signal (CLK ₄₅ ) included in the multiphase clock signal from the multiphase clock generation circuit 150. The latch circuit 161-2 holds the value of the clock signal (CLK ₄₅ ) at the timing specified by the time signal (VTOUT) and outputs the value to the code conversion circuit 162.

The latch circuit 161-3 receives a time signal (VTOUT) from the voltage / time converter 130 and receives a clock signal (CLK ₉₀ ) included in the multiphase clock signal from the multiphase clock generation circuit 150. The latch circuit 161-3 holds the value of the clock signal (CLK ₉₀ ) at the timing specified by the time signal (VTOUT) and outputs the value to the code conversion circuit 162.

The latch circuit 161-4 receives the time signal (VTOUT) from the voltage / time converter 130 and receives the clock signal (CLK ₁₃₅ ) included in the multiphase clock signal from the multiphase clock generation circuit 150. The latch circuit 161-4 holds the value of the clock signal (CLK ₁₃₅ ) at the timing specified by the time signal (VTOUT) and outputs it to the code conversion circuit 162.

The code conversion circuit 162 is a multi-phase clock at a timing specified by a 1-bit digital value (time signal (VTOUT)) from the latch circuit 161-1, the latch circuit 161-2, the latch circuit 161-3, and the latch circuit 161-4. Signal value). As illustrated in FIG. 16, the input signal of the code conversion circuit 162 corresponds to a thermometer code, and the code conversion circuit 162 converts the input signal into a corresponding digital signal (D _{OUT_TDC} ). Note that the digital signal (D _{OUT_TDC} ) corresponds to a binary code.

  As described above, the time digital converter according to the first embodiment holds the time signal in a state of being converted into a voltage format, restores the time signal in a timely manner, and converts it into a digital signal. Therefore, according to this time digital converter, a time signal can be converted into a digital signal at a desired timing. In other words, for example, when there is another circuit that operates intermittently using a multiphase clock signal common to the time digital converter, it is possible to reduce power consumption related to generation and supply of the multiphase clock signal. It becomes.

(Second Embodiment)
The time digital converter according to the second embodiment includes a first sub time digital converter for an upper bit signal and a second sub time digital converter for a lower bit signal. That is, the first sub time digital converter performs time digital conversion on the time signal with coarse accuracy, and the second sub time digital converter performs conversion residual (quantization error) in the first sub time digital converter. Time digital conversion is performed on the time signal corresponding to) with fine accuracy. Since the two sub-time digital converters perform the sharing work, high-resolution time digital conversion can be performed in a short time.

  As illustrated in FIG. 2, the time digital converter according to the second embodiment is a time digital converter 300 corresponding to the first sub time digital converter and the second sub time digital converter described above. And a time digital converter 200.

  The time digital converter 300 generates the upper bit signal 22 by converting the time signal 20 with coarse accuracy. For example, the time digital converter 300 may generate the upper bit signal 22 by quantizing the time information of the time signal 20 using the reference clock signal.

  On the other hand, the time digital converter 200 detects a residual time signal corresponding to the conversion residual in the time digital converter 300 using the reference clock signal common to the time signal 20 and the time digital converter 300, and The lower order bit signal 21 is generated by converting the residual time signal with fine accuracy.

  Specifically, the time digital converter 200 includes a residual time detection circuit 270, a time / voltage converter 110, a voltage holding circuit 120, a voltage / time converter 130, a timing control circuit 140, a polyphase. A clock generation circuit 150 and a latch circuit 160 are included. That is, the time digital converter 200 corresponds to a configuration in which a residual time detection circuit 270 is added to the time digital converter of FIG.

  Residual time detection circuit 270 receives time signal 20 and receives a reference clock signal from time digital converter 300. Residual time detection circuit 270 detects a residual time signal corresponding to the conversion residual in time digital converter 300 using time signal 20 and the reference clock signal. Residual time detection circuit 270 outputs a residual time signal to time / voltage converter 110.

  As described above, the time digital converter according to the second embodiment includes two sub time digital converters, and the first sub time digital converter converts the time signal with coarse accuracy, The sub time digital converter detects a residual time signal corresponding to the conversion residual in the first sub time digital converter, and converts the residual time signal with fine accuracy. The second sub time digital converter corresponds to the time digital converter according to the first embodiment. Therefore, according to this time digital converter, the resolution of the time digital converter according to the first embodiment can be improved.

(Third embodiment)
The analog-digital converter according to the third embodiment corresponds to a combination of SSADC and time digital converter, generates a digital signal corresponding to an upper bit value using SSADC, and uses lower-order bits using the time digital converter. A digital signal corresponding to the value is generated. That is, after SSADC converts an analog (voltage) signal into a time signal, time digital conversion is performed with coarse accuracy, and the time digital converter is fine with respect to the time signal corresponding to the conversion residual (quantization error) in SSADC. Perform time digital conversion with accuracy. The SSADC and the time digital converter perform the sharing work, so that high-resolution analog-digital conversion can be performed in a short time.

  As illustrated in FIG. 3, the analog-digital converter according to the third embodiment includes a comparator 410, a ramp wave generation circuit 420, a time digital converter 200, and a time digital converter 300. The comparator 410, the ramp wave generation circuit 420, and the time digital converter correspond to SSADC.

  The ramp wave generation circuit 420 generates a ramp wave signal and outputs the ramp wave signal to the comparator 410. The voltage of the ramp wave signal drops (or rises) with a substantially constant slope in proportion to the elapsed time. The ramp wave generation circuit 420 may be shared by the analog-digital converter of FIG. 3 and other circuits not shown.

  The comparator 410 receives the analog signal 23 from a preceding circuit (not shown) and receives the ramp wave signal from the ramp wave generation circuit 420. The comparator 410 compares the voltage of the analog signal 23 and the ramp wave signal, and generates the time signal 20 based on the comparison result. As described above, the voltage of the ramp signal changes in proportion to the elapsed time. On the other hand, the voltage of the analog signal 23 is normally held by the previous circuit. Therefore, if a time proportional to the voltage of the analog signal 23 elapses, the voltages of the analog signal 23 and the ramp signal match. Therefore, since the output signal of the comparator 410 is inverted from the high level (“1”) to the low level (“0”) before and after the timing when the two voltages coincide with each other, the output signal is the magnitude of the voltage of the analog signal 23. This corresponds to a pulse having an ON period length proportional to. The comparator 410 outputs the time signal 20 to the time digital converter 200 and the time digital converter 300.

  The comparator 410 and the ramp wave generation circuit 420 can also be regarded as a converter that converts the analog signal 23 into the time signal 20.

  The time digital converter 300 of FIG. 3 generates the upper bit signal 22 by converting the time signal 20 with coarse accuracy. Specifically, the time digital converter 300 includes a counter clock generation circuit 310, an AND gate 320, and a counter circuit 330.

  The counter clock generation circuit 310 generates a counter clock signal (also referred to as a reference clock signal) used for quantizing the time signal 20 with coarse accuracy. The frequency of the counter clock signal is the same as the frequency of the multiphase clock signal. The counter clock generation circuit 310 outputs the counter clock signal to the time digital converter 200 and the AND gate 320. The counter clock generation circuit 310 may be shared by the analog-digital converter of FIG. 3 and other circuits not shown.

  The AND gate 320 receives the time signal 20 from the comparator 410 and receives the counter clock signal from the counter clock generation circuit 310. The AND gate 320 calculates the logical product of the time signal 20 and the counter clock signal. The logical product coincides with the counter clock signal over a period in which the time signal 20 is at the high level, but always becomes the low level when the time signal 20 transits to the low level. The AND gate 320 outputs a logical product signal to the counter circuit 330.

  The counter circuit 330 receives the logical product signal from the AND gate 320. The counter circuit 330 generates the upper bit signal 22 by performing a count-up (or count-down) operation based on the logical product signal. Specifically, the counter circuit 330 performs a counting operation according to the rising edge (or falling edge) of the logical product signal. Here, since the edge of the logical product signal appears in synchronization with the edge of the counter clock signal over a period in which the time signal 20 is at the high level, the counter circuit 330 counts according to the edge of the logical product signal. By doing so, the time signal 20 can be quantized.

  3 uses the time signal 20 from the comparator 410 and the counter clock signal from the counter clock generation circuit 310 to generate a residual time signal corresponding to the conversion residual in the time digital converter 300. The residual time detection circuit 270 in FIG. To detect.

  Specifically, the residual time detection circuit 270 of FIG. 3 can include a D flip-flop and an XOR gate, as illustrated in FIG.

  The D flip-flop receives a time signal 20 (CMPOUT_ADC) and a counter clock signal (CLK). The D flip-flop holds the value of the time signal 20 (CMPOUT_ADC) in accordance with the rising edge (or falling edge) of the counter clock signal (CLK). The value held in the D flip-flop is output to the XOR gate.

  The XOR gate receives the time signal 20 (CMPOUT_ADC) and the output signal (CMPOUT_ADC ') of the D flip-flop. The XOR gate generates a residual time signal (TRES) by calculating an exclusive OR of both input signals.

  The time information held by the time signal 20 (CMPOUT_ADC) does not include a quantization error due to the counter clock signal (CLK). On the other hand, the time information of the output signal (CMPOUT_ADC ′) of the D flip-flop includes a quantization error due to the counter clock signal (CLK). Therefore, it is possible to derive the conversion residual of the time digital converter 300 of FIG. 3 from the time difference between the two.

As illustrated in FIG. 14, since the two input signals of the XOR gate coincide with each other over a period in which the time signal 20 (CMPOUT_ADC) is at a high level, the residual time signal (TRES) is at a low level. On the other hand, even if the time signal 20 (CMPOUT_ADC) is inverted from the High level to the Low level, the output signal (CMPOUT_ADC ′) of the D flip-flop does not immediately become the Low level but remains High until the counter clock signal (CLK) rises again. Maintain level. Therefore, the residual time signal (TRES) becomes High level over the time (T _RESX ) from the time signal 20 (CMPOUT_ADC) inversion to the next rising edge of the counter clock signal (CLK).

Note that the ON period (T _RESX ) of the residual time signal corresponds to a time obtained by subtracting the conversion residual (T _RES ) of the time digital converter 300 in FIG. 3 from the period (T _CLK ) of the counter clock signal (CLK). To do. Since the length of the period (T _CLK ) is known, the digital value corresponding to the conversion residual can be derived from the digital value obtained by converting the residual time signal using, for example, bit inversion.

  As described above, the analog-digital converter according to the third embodiment corresponds to a combination of SSADC and time-digital converter, and includes the time-digital converter according to the above-described second embodiment. Therefore, according to this analog-to-digital converter, high-resolution and high-speed analog-to-digital conversion is realized by supplementing the resolution of SSADC with the time digital converter.

  Further, the analog-digital converter is suitable for an application that performs parallel operations such as a column parallel readout circuit of an image sensor, as will be described below.

In general, since the sensor signals of each column of the pixel array do not match each other, when the SSADC converts the sensor signals in parallel, the conversion times of each SSADC also do not match each other. Considering a comparative example in which a time digital converter in the same column operates at the end of SSADC conversion (when a conversion residual is generated), the time digital converters in each column can be operated at any timing. It is necessary to supply the phase clock signal over the entire cycle. Note that the SSADC operable period (maximum conversion time length) is 2 ^N / f _clk (N represents the resolution of the SSADC, and f _clk represents the frequency of the counter clock signal), so the resolution of the SSADC is 1. As the number of bits increases, the power consumption associated with the generation and supply of multiphase clock signals approximately doubles.

  On the other hand, according to the analog-digital converter according to the third embodiment, as illustrated in FIG. 18, the operation timings of the temporal digital converters of all the columns are set to the SSADC operable period regardless of the conversion time of each SSADC. Can be aligned after the end of. Therefore, since the supply period of the multiphase clock signal is only one cycle as illustrated in FIG. 19, power consumption related to generation and supply of the multiphase clock signal (for example, power consumption of the multiphase clock generator and the clock buffer). Can be reduced.

  In addition, according to the analog-digital converter which concerns on 3rd Embodiment, compared with the said comparative example, a residual time detection circuit, a time / voltage converter, a voltage holding circuit, and a voltage / time converter are additionally required. Become. However, the residual time detection circuit, the time / voltage converter, and the voltage / time converter are limited to the period in which the SSADC conversion residual occurs and the period in which the time digital conversion is performed after the SSADC conversion ends. The power consumption is very small compared to the power consumption of SSADC. Furthermore, the voltage holding circuit consumes little power if the voltage is held using, for example, a capacitor.

(Fourth embodiment)
The analog-digital converter according to the fourth embodiment is different from the analog-digital converter according to the third embodiment in the configuration of the time digital converter for lower-order bit signals. Specifically, as illustrated in FIG. 4, the analog-digital converter according to the present embodiment includes a comparator 410, a ramp wave generation circuit 420, a time digital converter 500, and a time digital converter 300. Including.

  The time digital converter 500 includes a residual time detection circuit 270, a time / voltage converter 110, an amplifier 580, a voltage holding circuit 120, a voltage / time converter 130, a timing control circuit 140, and a multi-phase clock. A generation circuit 150 and a latch circuit 160 are included.

  The time / voltage converter 110 in FIG. 4 outputs the voltage signal to the amplifier 580 instead of the voltage holding circuit 120. The voltage holding circuit 120 also receives the (amplified) voltage signal from the amplifier 580 instead of the time / voltage converter 110.

  Amplifier 580 receives the voltage signal from time / voltage converter 110. The amplifier 580 amplifies the voltage signal (voltage thereof) and outputs the amplified voltage signal to the voltage holding circuit 120. The amplifier 580 may be implemented by various amplifiers such as a switched capacitor amplifier using an operational amplifier, for example.

  As described above, in the analog-digital converter according to the fourth embodiment, an amplifier is inserted between the time / voltage converter and the voltage holding circuit included in the time digital converter for the lower-order bit signal. . By the action of this amplifier, the voltage of the voltage signal (the magnitude depends on the time information of the time signal) is amplified. Therefore, compared to the case where no amplifier is used, the influence on the time information due to noise (error) added by the voltage holding circuit and the voltage / time converter is suppressed. Therefore, according to the analog-digital converter, it is possible to relax the required accuracy regarding noise of the voltage holding circuit and the voltage / time converter.

(Fifth embodiment)
The analog-digital converters according to the third embodiment and the fourth embodiment described above incorporate a separate counter circuit. On the other hand, in the fifth embodiment, for example, when a plurality of analog-digital converters are operated in parallel like the above-described column parallel readout circuit, one counter circuit is shared between the plurality of analog-digital converters. Make it possible.

  As illustrated in FIG. 5, the analog-digital converter according to the fifth embodiment includes a comparator 410, a ramp wave generation circuit 420, a time digital converter 200, and a time digital converter 600.

  The time digital converter 600 includes a counter clock generation circuit 610, a counter circuit 630, and a latch circuit 640. Note that the counter clock generation circuit 610 and the counter circuit 630 may be shared with other analog-digital converters not shown.

  The counter clock generation circuit 610 generates a counter clock signal (also referred to as a reference clock signal) that is used to quantize the time signal 20 with coarse accuracy. The frequency of the counter clock signal is the same as the frequency of the multiphase clock signal. The counter clock generation circuit 610 outputs a counter clock signal to the time digital converter 200 and the counter circuit 630. Further, the counter clock generation circuit 610 may output the counter clock signal to another analog / digital converter (not shown).

  The counter circuit 630 receives a counter clock signal from the counter clock generation circuit 610. The counter circuit 630 generates a counter signal by performing a count-up (or count-down) operation based on the counter clock signal. Specifically, the counter circuit 630 performs a counting operation in accordance with the rising edge (or falling edge) of the counter signal. Therefore, the value of the counter signal is counted up or down at a substantially constant period. The counter circuit 630 outputs a counter signal to the latch circuit 640.

  Further, the counter circuit 630 may output the counter signal to another analog-digital converter (not shown). Other analog-digital converters can convert a time signal into a digital signal using a counter signal as an external input signal.

  The latch circuit 640 receives the time signal 20 from the comparator 410 and receives the counter signal from the counter circuit 630. The latch circuit 640 holds the value of the counter signal at the timing specified by the time signal 20 (for example, the timing at which the time signal 20 is inverted from the High level to the Low level), and outputs this value as the upper bit signal 22.

  As described above, the analog-digital converter according to the fifth embodiment shares a counter circuit with other analog-digital converters. Therefore, according to this analog-digital converter, when applied to, for example, a column parallel readout circuit of an image sensor, analog-digital conversion of all columns can be realized using one counter circuit regardless of the number of columns of the pixel array. it can. That is, power consumption by the counter circuit can be reduced.

(Sixth embodiment)
The analog-to-digital converter according to the sixth embodiment corresponds to an analog-to-digital converter according to each of the above-described embodiments added with a mechanism for offset suppression (or offset removal). As illustrated in FIG. 6, the analog-digital converter according to the present embodiment includes a comparator 410, a ramp wave generation circuit 420, a time digital converter 200, a time digital converter 300, a memory 730, and an arithmetic operation. Circuit 740.

  The memory 730 stores a reference digital signal generated by analog-digital conversion of a predetermined reference analog signal in advance by the comparator 410, the ramp wave generation circuit 420, the time digital converter 200, and the time digital converter 300. The This reference digital signal corresponds to, for example, an offset error caused by offset voltage variation, delay variation, etc. of the comparator 410. Further, in the memory 730, a target digital signal (upper bit signal 22) generated by analog-to-digital conversion of the analog signal 23 by the comparator 410, the ramp wave generation circuit 420, the time digital converter 200, and the time digital converter 300 is stored. And a low-order bit signal 21 combined digital signal) is stored.

  The arithmetic circuit 740 reads the reference digital signal and the target digital signal from the memory 730. The arithmetic circuit 740 generates a final digital signal 24 corresponding to the analog signal 23 by subtracting the reference digital signal from the target digital signal. In the digital signal 24, the above-described offset error is suppressed.

  As described above, the analog-digital converter according to the sixth embodiment includes a memory that stores a reference digital signal corresponding to an offset error, and an arithmetic circuit that performs offset suppression using the reference digital signal. Therefore, according to the analog-digital converter, it is possible to generate a digital signal whose offset is suppressed. Furthermore, if this analog-digital converter is applied to, for example, a column parallel readout circuit of an image sensor, these can be appropriately suppressed even when different offset errors occur between the columns of the pixel array.

(Seventh embodiment)
The analog-digital converter according to the seventh embodiment is the same as the analog-digital conversion according to each of the above-described embodiments in that the time / voltage converter, the voltage holding circuit, and the voltage / time conversion circuit are implemented using a charge pump circuit. It is different from the vessel. As illustrated in FIG. 7, the analog-digital converter according to the present embodiment includes a comparator 410, a ramp wave generation circuit 420, a time digital converter 800, and a time digital converter 300.

  Time digital converter 800 includes a residual time detection circuit 270, a charge pump circuit 880, a timing control circuit 140, a multiphase clock generation circuit 150, and a latch circuit 160.

  The charge pump circuit 880 receives the residual time signal from the residual time detection circuit 270. Then, the charge pump circuit 880 converts the residual time signal into a voltage signal and holds it. Here, the voltage signal is a signal having a voltage whose magnitude depends on the time information of the residual time signal. Further, the charge pump circuit 880 converts the voltage signal into a time signal in accordance with the timing instructed by the timing control circuit 140, and outputs the time signal to the latch circuit 160. Here, in the time signal generated by the charge pump circuit 880, time information substantially the same as the time information of the residual time signal is restored.

A first specific example of the charge pump circuit 880 is shown in FIG. The charge pump circuit 880 shown in FIG. 8 includes a current source I _CP1 , a switch SW ₁ , a switch SW ₂ , a current source I _CP2 , a switch SW ₃ , a capacitor C _CP , a comparator 881, and an AND gate 882. Including.

Capacitor _{C CP} has one end connected to the inverting input terminal of the comparator 881, the switch SW _1, switch SW _2, in common to the switch SW _3, the other end is grounded. Voltage applied across the capacitor _{C CP} is represented by _{V X.}

Switch SW ₁ is shorted or opened according to a control signal between the one end of the output terminal and the capacitor _{C CP} of the current source _{I CP1.} ON period of the control signal supplied to the switch SW ₁ is approximately equal to the ON period of the residual time signal described above. When the switch SW ₁ is shorted between the one end of the output terminal and the capacitor _{C CP} of the current source _{I CP1,} capacitor _{C CP} is charged.

Switch SW ₂ is short-circuited or open according to the control signals between the one end of the input terminal and the capacitor _{C CP} of the current source _{I CP2.} Control signal of the switch SW ₂ is supplied from the timing control circuit 140, at the timing for converting the voltage signal from the charge pump circuit 880 is held to the time signal. When the switch SW ₂ is short-circuited between one end of the input terminal and the capacitor _{C CP} of the current source _{I CP2,} capacitor _{C CP} is discharged.

Switch SW ₃ is short-circuited or open according to the control signals between the one end of the power _{V COM} and the capacitor _{C CP.} When the switch SW ₃ is short-circuited between one end of the power supply _{V COM} and the capacitor _{C CP,} an initial voltage is applied to the capacitor _{C CP} (reset).

The comparator 881 has a non-inverting input terminal connected to the power supply V _COM and an inverting input terminal connected to one end of the capacitor _CP . The comparator 881 compares the voltage V _COM applied to the non-inverting input terminal with the voltage Vx applied to the inverting input terminal. The comparator 881 outputs a digital signal (CMPOUT) indicating the comparison result to the AND gate. The digital signal (CMPOUT) _becomes Low level when the High _{level, V COM} ≦ _{V X} when the _V COM> _{V X.}

AND gate 882 receives the digital signal (CMPOUT) from the comparator 881 receives a control signal supplied to the switch SW _2. The AND gate 882 generates a time signal (V _TOUT ) by calculating a logical product of both input signals.

  Specifically, the charge pump circuit 880 in FIG. 8 operates as illustrated in FIG. The operation phase of the charge pump circuit 880 can be broadly divided into (1) time → voltage conversion period, (2) voltage holding period, and (3) voltage → time conversion period.

The charge pump circuit 880, before (1) Time → voltage conversion period, a reset process of the voltage V _X. Specifically, the switch SW ₃ is changed from the OFF state to the ON state, the voltage _{V X} is equal to the voltage _{V COM.} Then, the switch SW ₃ is returned again to the OFF state.

Subsequently, the operation phase of the charge pump circuit 880 transitions from (1) time → voltage conversion period. (1) The time → voltage conversion period starts and ends in accordance with the ON period of the control signal of the switch SW ₁ (that is, the ON period of the residual time signal). (1) Time → over voltage conversion period, capacitor C _CP so is charged with a constant current, the increase in voltage V _X is proportional to the ON period length of the residual time signal. Note that (1) The derivative of the voltage V _X during the time-to-voltage conversion period can be expressed by the following mathematical formula (1).

Here, I _CP1 represents the amount of current generated by the current source I _CP1 , and C _CP represents the capacitance of the capacitor C _CP . Therefore, when the ON period length of the residual time signal is T _RES , and (1) the increase in voltage V _X in the time → voltage conversion period is V _RES , the following equation (2) can be derived.

Subsequently, the operation phase of the charge pump circuit 880 transitions to (2) voltage holding period. (2) In the voltage holding period, since the switch SW ₁ , the switch SW ₂ and the switch SW ₃ are all in the OFF state, the voltage V _X is held.

Subsequently, the operation phase of the charge pump circuit 880 transitions from (3) voltage → time conversion period. (3) Voltage → time conversion period, for example after the end conversion of all SSADC operating in parallel, starting with the control signal of the switch SW ₂ rises. (3) Since the capacitor _CP is discharged with a constant current over the voltage → time conversion period, the decrease of the voltage V _X is proportional to the elapsed time from the start of the (3) voltage → time conversion period, Eventually, the voltage V _X will coincide with the initial voltage V _COM . (3) The derivative of the voltage V _X during the voltage → time conversion period can be expressed by the following mathematical formula (3).

Here, I _CP2 represents the amount of current generated by the current source I _CP2 . Therefore, if (3) T ′ _RES is the time from the start of the voltage → time conversion period until the voltage V _X matches the voltage V _COM , the following equations (4) to (6) can be derived.

When the voltage V _X drops to the voltage V _COM , the output signal (CMPOUT) of the comparator 881 is inverted from the high level to the low level. In other words, the output signal (CMPOUT) of the comparator 881 maintains the high level for the time T ′ _RES from the start point of (3) voltage → time conversion period.

Therefore, the logical product for a period of time of the output signal of the comparator 881 (CMPOUT) and the control signal of the switch SW ₂ (VTOUT) is, ON period length corresponds to equal pulse T _'RES. Then, 'since the _RES proportional to _{T RES,} time signal (VTOUT) is time information that depends on the time information of the residual time signal _{(T RES)} (T' from T Equation (6) will have a _RES) . According to the equation (6), T ′ _RES = T _RES is designed when I _CP1 = I _CP2, and T ′ _RES = A _T * T _RES is designed when I _CP1 = A _T * I _CP2 .

A second specific example of the charge pump circuit 880 is shown in FIG. The charge pump circuit 880 of Figure 10 includes a current source _{I CP1,} and the switch SW _1, switch _{SW 2a, 1} and switches _{S 2a, 2} (hereinafter, also referred to switch _{SW 2a} group) and the switch _{SW 2b, 1} And switch S _{2b, 2} (hereinafter also referred to as switch SW _2b group), switch SW ₃ , capacitor C _CP , comparator 883, and AND gate 884.

The capacitor _CP has a terminal a connected to the switches SW _{2a, 1} and SW _{2b, 1} , and a terminal b connected to the switches SW _{2a, 2} and S _{2b, 2} .

Switch SW ₁ shorts or opens between the output terminal of current source I _CP1 and the inverting input terminal of comparator 883 according to the control signal. Voltage applied to the inverting input terminal of the comparator 883 is represented by V _X. The ON period of the control signal supplied to the switch SW ₁ is substantially equal to the ON period of the residual time signal and the period of converting the voltage signal held by the charge pump circuit 880 into a time signal. When the switch SW ₁ short-circuits between the output terminal of the current source I _CP1 and the inverting input terminal of the comparator 883, the current from the current source I _CP1 depends on the ON / OFF state of the switch SW _2a group and the switch SW _2b group. Thus, the capacitor _CP is charged so that the potential of either the terminal a or the terminal b rises through different paths.

The switch SW _{2a, 1} shorts or opens between the terminal a of the capacitor _CP and the inverting input terminal of the comparator 883 according to the control signal. The switches SW _{2a and 2} short or open between the terminal b of the capacitor _CP and the power source V _COM according to a control signal. When the switch SW _2a group is turned on during the ON period of the switch SW ₁ , the capacitor _CCP is charged so that the potential at the terminal a increases.

A common control signal for the switch SW _2a group is supplied from the timing control circuit 140, and rises at an appropriate timing after the charging of the capacitor C _CP is completed (that is, the rise in the potential at the terminal a of the capacitor C _CP is stopped). Go down. Such timing may be during the operation of SSADC or may be after the operation is completed.

The switches SW _{2b and 1} short or open between the terminal b of the capacitor _CP and the power source V _COM according to a control signal. The switches SW _{2b, 2} short or open between the terminal a of the capacitor _CP and the inverting input terminal of the comparator 883 according to the control signal.

Common control signal of the switch SW _2b group corresponds to the inverted signal of the common control signal of the switch SW _2a group. That is, the common control signal of the switch SW _2b group is supplied from the timing control circuit 140, and rises at substantially the same timing as the fall of the common control signal of the switch SW _2a group.

When the switch SW _2b group is turned on during the OFF period of the switch SW ₁ and the switch SW ₃ , the voltage V _X is 2V _RES (V _RES represents the increment of the voltage V _X due to charging through the switch SW _2a group. ) Descent. Further, when the switch _{SW 2b} group is ON state to the ON period of the switch SW _1, the capacitor _{C CP} is the potential of the terminal b is charged to rise.

The switch SW ₃ shorts or opens between the power supply V _COM and the inverting input terminal of the comparator 883 according to the control signal. When the switch _{SW 2a, 1} (or switch _{SW 2b, 2)} switch SW ₃ is turned ON period becomes ON state, the initial voltage (reset) is applied to one end and the other end of the capacitor _{C CP.}

The comparator 883 has a non-inverting input terminal connected to the power supply V _COM , and an inverting input terminal connected to the switch SW ₁ , the switch SW _{2a, 1} , the switch SW _{2b, 2} and the switch SW ₃ . The comparator 883 compares the voltage V _COM applied to the non-inverting input terminal with the voltage Vx applied to the inverting input terminal. The comparator 883 outputs a digital signal (CMPOUT) indicating the comparison result to the AND gate. The digital signal (CMPOUT) _becomes Low level when the High _{level, V COM} ≦ _{V X} when the _V COM> _{V X.}

AND gate 884 receives digital signals (CMPOUT) were allowed to logic inversion from the comparator 883 receives a control signal supplied to the switch SW _1. The AND gate 884 generates a time signal (VTOUT) by calculating a logical product of both input signals.

  Specifically, the charge pump circuit 880 in FIG. 10 operates as illustrated in FIG. The operation phase of the charge pump circuit 880 can be broadly divided into (1) time → voltage conversion period, (2) voltage holding period, and (3) voltage → time conversion period.

The charge pump circuit 880, before (1) Time → voltage conversion period, a reset process of the voltage V _X. Specifically, the switch SW ₃ is turned ON period of the switch _{SW 2a} group is changed from the OFF state to the ON state, the voltage _{V X} is equal to the voltage _{V COM.} The voltage V _COM is applied to both the terminals a and b of the capacitor _CP . Then, the switch SW ₃ is returned again to the OFF state.

Subsequently, the operation phase of the charge pump circuit 880 transitions from (1) time → voltage conversion period. (1) Time → voltage conversion period begins and ends in accordance with the ON period of the residual time signal as a control signal of the switch SW _1. (1) Time → over voltage conversion period, capacitor C _CP so is charged with a constant current through the switch SW _2a group, the increase in voltage V _X is proportional to the ON period of the residual time signal. Note that (1) The derivative of the voltage V _X in the time-to-voltage conversion period can be expressed by the above mathematical formula (1). Therefore, also in the charge pump circuit 880 of FIG. 10, the above equation (2) is established with respect to the increment V _RES of the voltage V _X.

Subsequently, the operation phase of the charge pump circuit 880 transitions to (2) voltage holding period. (2) In the voltage holding period, the switch SW ₁ and the switch SW ₃ are in the OFF state. (2) In the middle of the voltage holding period, the switch SW _2b group changes from the OFF state to the ON state, and the switch SW _2a group changes from the ON state to the OFF state substantially simultaneously. Therefore, it is held in the state of voltage V _X = V _COM + V _RES until the control signal of the switch SW _2a group falls, and when the control signal of the switch SW _2a group rises, it is held in the state of voltage V _X = V _COM -V _RES. Is done.

Subsequently, the operation phase of the charge pump circuit 880 transitions from (3) voltage → time conversion period. (3) Voltage → time conversion period, for example after the end conversion of all SSADC operating in parallel, the control signal of the switch SW ₁ is started by rising again. (3) Since the capacitor _CP is charged with a constant current through the switch SW _2b group over the voltage → time conversion period, the increase in the voltage V _X is (3) from the start of the voltage → time conversion period. The voltage V _{X eventually} coincides with the initial voltage V _COM . Note that (3) the derivative of the voltage V _X during the voltage-to-time conversion period can be expressed by Equation (1) above. Therefore, if (3) T ′ _RES is the time from the start of the voltage → time conversion period until the voltage V _X matches the voltage V _COM , the following formulas (7) to (9) can be derived.

When the voltage V _X rises to the voltage V _COM , the output signal (CMPOUT) of the comparator 883 is inverted from the Low level to the High level. In other words, the output signal (CMPOUT) of the comparator 883 maintains the low level for the time T ′ _RES from the start point of (3) voltage → time conversion period.

Therefore, the time signal (VTOUT) that is the logical product of the logical inversion of the output signal (CMPOUT) of the comparator 883 and the control signal of the switch SW ₁ corresponds to a pulse whose ON period length is equal to T ′ _RES . Then, 'equal to the _RES is _{T RES,} time signal (VTOUT) is time information that depends on the time information of the residual time signal _{(T RES)} (T' from T Equation (9) will have a _RES).

In summary, the charge pump circuit 880 of FIG. 8 can amplify the time information (ON period) of the residual time signal with a gain _AT by adjusting the ratio of I _CP1 and I _CP2. Are better. However, when the current source I _CP1 and the current source I _CP2 are mounted using MOSFETs (MOS Field Effect Transistors), it is not always easy to design I _CP1 and I _CP2 accurately due to MOSFET variations. Therefore, calibration for reducing the error of the gain _AT may be necessary. The charge pump circuit of FIG. 10 cannot amplify time information, but is excellent in that calibration is unnecessary because it is not affected by the error of I _CP1 .

  As described above, the analog-digital converter according to the seventh embodiment includes a time / voltage converter, a voltage holding circuit, and a charge pump circuit that operates as a voltage / time converter. Therefore, according to this analog-digital converter, the time digital converter or the analog-digital converter according to each of the above-described embodiments can be mounted using this charge pump circuit.

(Eighth embodiment)
In the seventh embodiment described above, the time / voltage converter, the voltage holding circuit, and the voltage / time conversion circuit are mounted using a charge pump circuit. Both the charge pump circuit and the SSADC include a comparator. Since the comparator included in the charge pump circuit starts to operate after the operation of SSADC is completed, the operation period of the comparator does not overlap with the comparator included in SSADC. Therefore, in the eighth embodiment, the charge pump circuit and the SSADC share one comparator in a time division manner.

  Specifically, the charge pump circuit and the SSADC can share one comparator as illustrated in FIG. The example of FIG. 12 is based on the charge pump circuit 880 of FIG. 8 described above, but may alternatively be based on FIG. 10 or another charge pump circuit 880. In the example of FIG. 12, the comparator 881 is shared as a comparator for SSADC and a comparator for the charge pump circuit 880.

When the comparator 881 functions as a comparator for SSADC, the switch SW ₄ supplies the analog signal 23 (V _SIG ) to the non-inverting input terminal of the comparator 881, and the switch SW ₅ supplies the ramp wave signal to the comparator 881. To the inverting input terminal.

If the comparator 881 functions as a comparator for the charge pump circuit 880, the switch SW ₄ applies a voltage _{V COM} to the non-inverting input terminal of the comparator 881, the switch SW ₅ is a voltage _{V X} inversion of the comparator 881 Apply to the input terminal.

  As described above, in the analog-digital converter according to the eighth embodiment, the charge pump circuit and SSADC share one comparator in a time division manner. Therefore, according to the analog-digital converter, the number of comparators can be reduced as compared with the seventh embodiment, so that power consumption can be reduced.

(Ninth embodiment)
The analog-digital converter according to each of the above-described embodiments can be applied to a CMOS image sensor as illustrated in FIG. The CMOS image sensor of FIG. 17 includes a pixel array 950, and an analog-digital converter is prepared for each column of the pixel array 950.

  Each analog-digital converter corresponds to the analog-digital converter according to each of the above-described embodiments, and includes an individual comparator 410 and a time digital converter 1000. The time digital converter 1000 includes a first sub time digital converter for the upper bit signal and a second sub time digital converter for the lower bit signal. The first sub time digital converter may be the same as or similar to time digital converter 300 or time digital converter 600. The second sub time digital converter may be the same as or similar to time digital converter 200, time digital converter 500 or time digital converter 800. The timing control circuit 140, the multiphase clock generation circuit 150, and the ramp wave generation circuit 420 are shared by all analog-digital converters.

  The multiphase clock signal generated by the multiphase clock generation circuit 150 is not required before the time / voltage conversion period of the second sub time digital converter (that is, within the SSADC operable period). Therefore, the timing control circuit 140 uses the AND gate 960-1, the AND gate 960-2, the AND gate 960-3, and the AND gate 960-4 (hereinafter referred to as an AND gate 960 group) to generate a multiphase clock signal. To control the supply.

  Specifically, the timing control circuit 140 disables the supply of the multiphase clock signal by supplying a low level digital signal to the AND gates 960 within the SSADC operable period. On the other hand, the timing control circuit 140 validates the supply of the multiphase clock signal by providing a high-level digital signal to the AND gates 960 after the end of the SSADC operable period of the second sub time digital converter.

  According to the supply control of the multiphase clock signal, the power consumption of the clock buffer 970-1, the clock buffer 970-2, the clock buffer 970-3, and the clock buffer 970-4 for supplying the multiphase clock signal is reduced. be able to.

  As described above, the image sensor according to the ninth embodiment includes the analog-digital converter according to each of the above-described embodiments. Therefore, according to this image sensor, the generation and supply of the multiphase clock signal can be completed in one cycle by aligning the operation timings of the time digital converters for the low-order bit signals between the columns. That is, it is possible to reduce power consumption related to generation and supply of multiphase clock signals.

  The analog-digital converter according to each of the above-described embodiments may be applied not only to a CMOS image sensor but also to other types of image sensors such as a CCD (Charge Coupled Device) image sensor.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

10, 20 ... Time signal 11, 24 ... Digital signal 21 ... Lower bit signal 22 ... Higher bit signal 23 ... Analog signal 110 ... Time / voltage converter 120 ... Voltage Holding circuit 130 ... Voltage / time converter 140 ... Timing control circuit 150 ... Multiphase clock generation circuit 160, 161, 640 ... Latch circuit 162 ... Code conversion circuit 200, 300, 500, 600, 800, 1000 ... time digital converter 270 ... residual time detection circuit 310, 610 ... counter clock generation circuit 320, 882, 884, 960 ... AND gate 330, 630 ... counter Circuit 410, 881, 883 ... Comparator 420 ... Ramp wave generation circuit 580 ... Amplifier 730 ... Memory Li 740 ... arithmetic circuit 880 ... charge pump circuit 950 ... pixel array 970 ... clock buffer

Claims (11)

A first converter for converting the first time signal into an intermediate signal having information in a format different from time;
A holding circuit for holding the intermediate signal;
A second converter for converting the intermediate signal held by the holding circuit into a second time signal;
A time quantizer for generating a digital signal by quantizing the second time signal using a multiphase clock signal;
A time digital converter comprising: a control circuit that controls a timing at which the intermediate signal is input to the second converter and a timing at which the multiphase clock signal is input to the time quantizer.   2. The time digital converter according to claim 1, wherein the intermediate signal is a voltage signal having a voltage having a magnitude depending on time information of the first time signal. An amplifier for amplifying the intermediate signal;
The holding circuit holds the intermediate signal amplified by the amplifier;
The time digital converter according to claim 2.   The time digital converter according to claim 2, wherein the first converter, the holding circuit, and the second converter are implemented using a charge pump circuit. A first sub-time digital converter for converting the first time signal into a first digital signal corresponding to an upper bit value;
A second sub time digital converter for converting the conversion residual in the first sub time digital converter into a second digital signal corresponding to a lower bit value;
The second sub time digital converter is:
A detection circuit for detecting a residual time signal corresponding to the conversion residual based on the first time signal;
A first converter for converting the residual time signal into an intermediate signal having information in a format different from time;
A holding circuit for holding the intermediate signal;
A second converter for converting the intermediate signal held by the holding circuit into a second time signal;
A time quantizer for generating the second digital signal by quantizing the second time signal using a multiphase clock signal;
A control circuit for controlling a timing at which the intermediate signal is input to the second converter and a timing at which the multiphase clock signal is input to the time quantizer;
Time digital converter. The first sub time digital converter comprises:
The latch circuit which produces | generates a said 1st digital signal by hold | maintaining the value of the external input signal counted up or counted down by a substantially fixed period at the timing designated by the said 1st time signal. 5. The time digital converter according to 5. A time-to-digital converter according to claim 5;
A third converter for converting an analog signal into the first time signal. A reference digital signal obtained by converting a reference analog signal in advance by the third converter and the time digital converter, and a target digital signal corresponding to a combination of the first digital signal and the second digital signal are stored. Memory to
The analog-digital converter according to claim 7, further comprising: an arithmetic circuit that generates a digital signal corresponding to the analog signal by subtracting the reference digital signal from the target digital signal. The intermediate signal is a voltage signal having a voltage whose magnitude depends on time information of the residual time signal,
The first converter, the holding circuit and the second converter are mounted using a charge pump circuit,
The third converter and the charge pump circuit share a comparator in time division.
The analog-digital converter according to claim 7. A generating circuit for generating the multiphase clock signal;
A clock buffer for supplying the multi-phase clock signal to the first sub-time digital converter;
The generation circuit and the clock buffer stop operating within an operable period of the first sub time digital converter;
The analog-digital converter according to claim 7.   An image sensor comprising the analog-digital converter according to claim 7.