CN110908270A - Constant slope digital-to-time converter and control method thereof - Google Patents
Constant slope digital-to-time converter and control method thereof Download PDFInfo
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Abstract
The invention discloses a constant slope digital-to-time converter and a control method thereof, wherein the constant slope digital-to-time converter comprises: a discharge load capacitor for storing charge to discharge to generate a voltage falling edge; the discharging current source is used for determining the slope of the falling edge of the output voltage according to the discharging current of the discharging load capacitor; the switch capacitor digital-to-analog converter is used for setting the discharge starting voltage of the discharge load capacitor; a buffer for converting a voltage falling edge discharged by the discharge load capacitor into a rising edge and providing a stable output rising edge slew rate; a clock and control signal generation circuit for receiving the input delay control word dcw and the input clock in and outputting the actual delay control word dcw _ act and a plurality of different clock phases. The invention realizes high linearity in a larger time delay range, has the characteristics of low noise and low power consumption, has high linearity and is very suitable for being applied to a fractional-frequency phase-locked loop.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a constant slope digital-to-time converter and a control method thereof.
Background
The sub-sampling phase-locked loop directly samples the high-frequency output of the oscillator under the control of the low-frequency reference clock to obtain phase error information, and then adjusts the output frequency of the oscillator through negative feedback control to realize the function of the phase-locked loop. The sub-sampling structure cannot acquire frequency error information, and theoretically, a loop can be locked at any integer multiple of the frequency of a reference clock. Since the sub-sampling structure directly samples the output of the oscillator, a frequency divider is not used, and the power consumption of the system is effectively saved, but it is also difficult to use the fractional frequency control mode realized by the traditional delta-sigma modulator (DSM) and frequency divider. In order to realize fractional frequency, the sub-sampling phase-locked loop can add delay on the reference clock to compensate the delay of fractional quantization error.
The all-digital phase-locked loop adopts a digital circuit to realize loop control, so that the all-digital phase-locked loop has high design and realization flexibility, is convenient to integrate with other systems on a chip, can obtain better performance along with the development of an integrated circuit manufacturing process, and has very wide application. However, in the fractional frequency all-digital phase-locked loop with the traditional structure, due to the existence of fractional quantization error, the phase error change range between clock signals input by the phase discriminator is very large, and the requirements on the design complexity, power consumption and error control of the time-to-digital converter are very high. In order to reduce the input phase error range of the time-to-digital converter, a delay can be added on the reference clock or the feedback clock to compensate the delay of the fractional quantization error.
The above-mentioned delay compensation method is usually implemented by a delta-sigma modulator (DSM) and a digital-to-time converter (DTC). With the phase-locked loop with the structure, the phase error between the clock signals input by the phase detector is similar to the integer frequency. The design difficulty of the digital-to-time converter is lower than that of the time-to-digital converter, so that high precision is easy to realize, and the digital-to-time converter has wide application in a fractional frequency phase-locked loop. Because the noise of the digital-to-time converter is one of the main contributions of the in-band noise of the output of the phase-locked loop, the linearity of the phase-locked loop determines the spurious performance of the output, and the high-performance phase-locked loop has high requirements on the linearity, the noise and the energy efficiency of the digital-to-time converter.
The conventional digital-to-time converter is usually implemented by using an adjustable buffer and an adjustable load, when the conversion current or the load of the buffer changes, the slope of the output conversion edge changes, and the time from the time when the input change edge crosses the threshold voltage to the time when the output change edge crosses the threshold voltage also changes, so that the adjustable delay time is realized. The common implementation of the adjustable buffer is an inverter combination with adjustable bias current, and the common implementation of the adjustable load is a voltage-controlled capacitor or a numerical control capacitor array. The basic principle of the digital-to-time converter for adjusting the delay time is to control the changing edge of the output. Because the input control and the delay variation do not have a completely linear relationship, the digital time converter of the structure has limited linearity performance, needs to depend on device matching, layout design and careful simulation data, is very sensitive to errors of manufacturing process, power supply voltage and temperature (PVT), and often needs to be calibrated to meet the design requirement.
Disclosure of Invention
The invention aims to provide a constant slope digital-to-time converter and a control method thereof, which can realize low noise and low power consumption and can realize high linearity in a larger output delay time range.
To achieve the above object, the present invention provides a constant slope digital-to-time converter, comprising:
a discharge load capacitor for storing charge to discharge to generate a voltage falling edge;
the input end of the discharging current source is connected with the output end of the discharging load capacitor and is used for determining the slope of the falling edge of the output voltage according to the discharging current of the discharging load capacitor;
the output end of the switch capacitor digital-to-analog converter is connected with the output end of the discharge load capacitor and is used for setting the discharge starting voltage of the discharge load capacitor;
the input end of the buffer is connected with the output end of the switched capacitor digital-to-analog converter, and the buffer is used for converting the voltage falling edge discharged by the discharging load capacitor into a rising edge and providing stable output rising edge conversion rate;
and the output end of the clock and control signal generating circuit is respectively connected with the discharging load capacitor and the switched capacitor digital-to-analog converter and is used for receiving the input delay control word dcw and the input clock in and outputting the actual delay control word dcw _ act and a plurality of different clock phases.
In the above constant slope digital-to-time converter, the discharge current source includes a current bias circuit, an nmos cascode current source, and a switch SW 0; the nmos cascode current source comprises an nmos common-source tube and an nmos common-gate tube; the grid electrode of the nmos common source tube is connected with a bias voltage Vbg1 provided by the current bias circuit; the grid electrode of the nmos common-grid tube is connected with a bias voltage Vbg2 provided by the current bias circuit; the source electrode input end of the nmos common-gate tube is connected with the output end of the discharge load capacitor; the source electrode output end of the nmos common-gate tube is connected with the source electrode input end of the nmos common-source tube; one end of the switch SW0 is connected with the source electrode output end of the nmos common-source tube, and the other end of the switch SW0 is grounded; the control terminal of the switch SW0 receives an input clock in.
The above constant slope digital-to-time converter, wherein the discharge load capacitance comprises a capacitor CL and a switch SW 1; one polar plate of the capacitor CL is connected with a power supply, and the other polar plate of the capacitor CL is connected with the output end of the switched capacitor digital-to-analog converter; two ends of the switch SW1 are respectively connected with two ends of the capacitor CL; the control terminal of the switch SW1 receives the clock phase ck1 output by the clock and control signal generation circuit.
The constant slope digital-to-time converter comprises a load capacitor CT, a capacitor array consisting of a plurality of capacitors C1-Cn, a switch SW2 and a switch SW 3; the load capacitor CT is connected with one end of a capacitor in the capacitor array; the other end of the load capacitor CT is connected with a power supply; the other end of the capacitor in the capacitor array receives the actual delay control word dcw _ act output by the clock and control signal generating circuit; one end of the switch SW2 is connected with the common end of the load capacitor CT and the capacitor array, and the other end of the switch SW2 is connected with the output end of the discharge load capacitor and the input end of the buffer; the control end of the switch SW2 receives the clock phase ck2 output by the clock and control signal generating circuit; two ends of the switch SW3 are respectively connected with two ends of the load capacitor CT; the control terminal of the switch SW3 receives the clock phase ck3 output by the clock and control signal generation circuit.
In the above constant slope digital-to-time converter, when the actual delay control word dcw _ act received by the switched capacitor digital-to-analog converter adopts binary input, the size of the capacitor Cn in the capacitor array is 2(n-1)Cu, where Cu is the unit capacitance magnitude in the capacitor array.
The constant slope digital-to-time converter described above, wherein the switched capacitor digital-to-analog converter uses at least two clock phases:
voltage reset phase: both ends of the load capacitor CT are connected to a power supply; the common end of the capacitor array and the load capacitor CT is also connected to the power supply, and the actual delay control word dcw _ act received by the other end is equal to the reset control word dcw _ rst; the output voltage Vda of the switched capacitor digital-to-analog converter is equal to the power supply voltage Vdd;
voltage setting phase: one end of the load capacitor CT is connected to a power supply; the common end of the capacitor array and the load capacitor CT is communicated with the output end of the discharge load capacitor and the input end of the buffer, and the actual delay control word dcw _ act received by the other end is equal to the input delay control word dcw; the output voltage Vdac of the switched capacitor digital-to-analog converter is Vdd · [ CT + (M-dcw _ rst + dcw) · Cu ]/(CT + M · Cu), where Cu is the unit capacitance of the capacitor array, and M is the total number of capacitors in the capacitor array.
The constant slope digital-to-time converter described above, wherein when the reset control word dcw _ rst used in the voltage reset phase is smaller than the input delay control word dcw, the output voltage Vdac of the switched capacitor digital-to-analog converter at the voltage set phase is > Vdd; when the reset control word dcw _ rst used in the voltage reset phase is greater than the input delay control word dcw, the output voltage Vdac < Vdd of the switched-capacitor digital-to-analog converter at the voltage set phase.
The constant slope digital-to-time converter described above, wherein, for the buffer: when the input voltage crosses its threshold voltage from high to low, a rising edge is output, whereas when the input voltage crosses its threshold voltage from low to high, a falling edge is output, which is output as the output clock out of the digital-to-time converter.
In the above constant slope digital-to-time converter, the input clock in cycle is divided into 3 clock phases, which includes:
voltage reset phase, switch SW0 open; switch SW1 is ON; switch SW2 is open; switch SW3 is on and the actual delay control word dcw _ act equals the reset control word dcw _ rst;
voltage set phase, switch SW0 open; switch SW1 is open; switch SW2 is ON; switch SW3 is open and the actual delay control word dcw _ act equals the input delay control word dcw;
discharge phase, switch SW0 is on; switch SW1 is open; switch SW2 is open.
The invention also provides a control method of the constant slope digital-to-time converter, which comprises the following steps:
(1) when the falling edge of the input clock comes, in the voltage reset phase, the switch SW0 is turned off; the switch SW1 is turned on, both ends of the discharging load capacitor are connected to the power supply, the stored charge is 0, the output voltage is pulled to the power supply, and at this time, the buffer outputs a falling edge; switch SW2 is open; the switch SW3 is turned on, and the common end of the load capacitor CT and the capacitor array in the switched capacitor digital-to-analog converter is connected to the power supply; the actual delay control word dcw _ act is equal to the reset control word dcw _ rst;
(2) after a period of time delay, before the rising edge of the input clock comes, the input clock enters a voltage setting phase, and the switch SW0 is switched off; switch SW1 is open; the switch SW2 is turned on, the discharging load capacitor is connected with the switch capacitor digital-to-analog converter, and the discharging initial voltage is set; switch SW3 is open and the actual delay control word dcw _ act equals the input delay control word dcw;
(3) when the rising edge of the input clock comes, the discharging phase starts, and the switch SW1 is switched off; the switch SW2 is disconnected, and the switched capacitor digital-to-analog converter is disconnected with the discharging load capacitor; the switch SW0 is turned on, the charge in the discharge load capacitor is discharged to ground through the discharge current source, a voltage falling edge with a constant slope is output, when the voltage is smaller than the threshold voltage of the buffer, the output clock of the buffer output generates a rising edge, and the delay between the rising edge and the rising edge of the input clock is controlled by the input delay control word dcw.
Compared with the prior art, the invention has the following beneficial effects:
the digital-to-time converter provided by the invention is applied to a switched capacitor digital-to-analog converter based on low noise and low power consumption, is used for setting the initial discharge voltage of an output change edge, and sets the output change edge with constant slope through a high-linearity current source, thereby realizing the control relation from high-linearity input control words to high-linearity output delay time. Because the switched capacitor digital-to-analog converter is used, the initial discharge voltage can be higher than the power supply voltage, and the working voltage interval of the discharge current source is expanded to a range from higher voltage to threshold voltage, so that high linearity in a larger delay time range is realized. The digital-to-time converter has the characteristics of low noise and low power consumption, has high linearity and is very suitable for being applied to a fractional-frequency phase-locked loop.
Drawings
Fig. 1 is a block diagram of a top-level structure of a digital-to-time converter according to an embodiment of the present invention;
FIG. 2 is a circuit diagram of a discharging current source according to an embodiment of the present invention;
fig. 3 is a circuit diagram of a switched capacitor digital-to-analog converter according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a conventional variable slope digital-to-time converter;
FIG. 5 is a schematic diagram of a constant slope digital-to-time converter of the present invention;
FIG. 6 is a schematic diagram of a digital-to-time converter according to an embodiment of the present invention;
fig. 7 is a timing diagram of the switched capacitor digital-to-analog converter according to the embodiment of the present invention.
Detailed Description
The invention will be further described by the following specific examples in conjunction with the drawings, which are provided for illustration only and are not intended to limit the scope of the invention.
As shown in fig. 1, the present invention provides a constant slope digital-to-time converter comprising: a discharge load capacitor 1 for storing charge to discharge to generate a voltage falling edge; the input end of the discharging current source 2 is connected with the output end of the discharging load capacitor 1 and is used for determining the slope of the falling edge of the output voltage according to the discharging current of the discharging load capacitor 1; the output end of the switched capacitor digital-to-analog converter 3 is connected with the output end of the discharge load capacitor 1 and is used for setting the discharge starting voltage of the discharge load capacitor 1; the input end of the buffer 4 is connected with the output end of the switched capacitor digital-to-analog converter 3, and the buffer is used for converting the voltage falling edge discharged by the discharge load capacitor 1 into the rising edge and providing stable output rising edge conversion rate; and the output end of the clock and control signal generating circuit 5 is respectively connected with the discharging load capacitor 1 and the switched capacitor digital-to-analog converter 3, and is used for receiving the input delay control word dcw and the input clock in and outputting an actual delay control word dcw _ act and a plurality of different clock phases.
As shown in fig. 2, the discharging current source 2 includes a current bias circuit 21, an nmos cascode current source 22, and a switch SW 0; the nmos cascode current source 22 comprises an nmos common-source tube and an nmos common-gate tube; the grid electrode of the nmos common source tube is connected with a bias voltage Vbg1 provided by the current bias circuit 21; the grid electrode of the nmos common-gate tube is connected with a bias voltage Vbg2 provided by the current bias circuit 21; the source electrode input end of the nmos common-gate tube is connected with the output end of the discharge load capacitor 1; the source electrode output end of the nmos common-gate tube is connected with the source electrode input end of the nmos common-source tube; one end of the switch SW0 is connected with the source electrode output end of the nmos common-source tube, and the other end of the switch SW0 is grounded; the control terminal of the switch SW0 receives an input clock in.
As shown in fig. 3, the discharge load capacitor 1 includes a capacitor CL and a switch SW 1; one polar plate of the capacitor CL is connected with a power supply, and the other polar plate is connected with the output end of the switched capacitor digital-to-analog converter 3; two ends of the switch SW1 are respectively connected with two ends of the capacitor CL; the control terminal of the switch SW1 receives the clock phase ck1 output by the clock and control signal generating circuit 5.
The switched capacitor digital-to-analog converter 3 comprises a load capacitor CT, a capacitor array consisting of a plurality of capacitors C1-Cn, a switch SW2 and a switch SW 3; the total capacitance of the capacitor array is CA, and the load capacitor CT is connected with one end of a capacitor in the capacitor array; the other end of the load capacitor CT is connected with a power supply; the other end of the capacitor in the capacitor array receives the actual delay control word dcw _ act output by the clock and control signal generating circuit 5; one end of the switch SW2 is connected with the common end of the load capacitor CT and the capacitor array, and the other end is connected with the output end of the discharge load capacitor 1 and the input end of the buffer 4; the control end of the switch SW2 receives the clock phase ck2 output by the clock and control signal generating circuit 5; two ends of the switch SW3 are respectively connected with two ends of the load capacitor CT; the control terminal of the switch SW3 receives the clock phase ck3 output by the clock and control signal generating circuit 5.
The input digital control word of the switched capacitor digital-to-analog converter 3 can be input by binary or other codes such as thermometer codes, and accordingly, the capacitor array is designed according to different codes. When the actual delay control word dcw _ act received by the switched capacitor digital-to-analog converter 3 adopts binary input, the sizes of the capacitor arrays C1-Cn are increased according to the power of 2, such as (1. Cu), (2. Cu), (4. Cu), …, (2. Cu) in sequence(n-1)Cu), where Cu is the unit capacitance magnitude in the capacitor array. And the coding weight can be adjusted according to the actual layout, parasitic or control words.
The switched capacitor digital to analog converter 3 uses at least two clock phases:
voltage reset phase: both ends of the load capacitor CT are connected to a power supply; the common end of the capacitor array and the load capacitor CT is also connected to the power supply, and the actual delay control word dcw _ act received by the other end is equal to the reset control word dcw _ rst; the output voltage Vda of the switched-capacitor digital-to-analog converter 3 is equal to the power supply voltage Vdd;
voltage setting phase: one end of the load capacitor CT is connected to a power supply; the common end of the capacitor array and the load capacitor CT is communicated with the output end of the discharge load capacitor 1 and the input end of the buffer 4, and the actual delay control word dcw _ act received by the other end is equal to the input delay control word dcw; the output voltage Vdac of the switched-capacitor digital-to-analog converter 3 is Vdd · [ CT + (M-dcw _ rst + dcw) · Cu ]/(CT + M · Cu), where Cu is the unit capacitance of the capacitor array, and M is the total number of capacitors in the capacitor array.
The switched capacitor digital-to-analog converter 3 uses two clock phase control modes, so that the output voltage Vdac can be higher than the power voltage Vdd. When the reset control word dcw _ rst used in the voltage reset phase is smaller than the input delay control word dcw, the output voltage Vdac > Vdd of the switched capacitor digital-to-analog converter 3 in the voltage setting phase; when the reset control word dcw _ rst used in the voltage reset phase is greater than the input delay control word dcw, the output voltage Vdac < Vdd of the switched-capacitor digital-to-analog converter 3 at the voltage set phase.
The clock and control signal generating circuit 5 may generate control signals such as a required clock signal, a reset control word, and the like through a delay and logic gate, wherein the clock signal includes three clocks ck1, ck2, and ck3 with different phases, and the control signals include a reset control word dcw _ rst having the same bit number as the input delay control word dcw, an actual delay control word dcw _ act, and a reset control word enable signal enb. The reset control word enable signal enb is an internal signal, enb is valid, and dcw _ act is dcw _ rst; enb is invalid as 1, when dcw _ act is dcw.
For the buffer 4: when the input voltage crosses its threshold voltage from high to low, a rising edge is output, whereas when the input voltage crosses its threshold voltage from low to high, a falling edge is output, which is output as the output clock out of the digital-to-time converter.
The input clock in cycle is divided into 3 clock phases, including:
voltage reset phase, switch SW0 open; switch SW1 is ON; switch SW2 is open; switch SW3 is on and the actual delay control word dcw _ act equals the reset control word dcw _ rst;
voltage set phase, switch SW0 open; switch SW1 is open; switch SW2 is ON; switch SW3 is open and the actual delay control word dcw _ act equals the input delay control word dcw;
discharge phase, switch SW0 is on; switch SW1 is open; switch SW2 is open and the other connection state can remain unchanged from the previous phase.
The invention also provides a control method of the constant slope digital-to-time converter, which comprises the following steps:
(1) when the falling edge of the input clock comes, in the voltage reset phase, the switch SW0 is turned off; the switch SW1 is turned on, both ends of the discharge load capacitor 1 are connected to the power supply, the stored charge is 0, the output voltage is pulled to the power supply, and at this time, the buffer 4 outputs a falling edge; switch SW2 is open; the switch SW3 is turned on, and the common end of the load capacitor CT and the capacitor array in the switched capacitor digital-to-analog converter 3 is connected to the power supply; the actual delay control word dcw _ act is equal to the reset control word dcw _ rst;
(2) after a period of time delay, before the rising edge of the input clock comes, the input clock enters a voltage setting phase, and the switch SW0 is switched off; switch SW1 is open; the switch SW2 is turned on, the discharging load capacitor 1 is connected with the switched capacitor digital-to-analog converter 3, and the discharging initial voltage is set; switch SW3 is open and the actual delay control word dcw _ act equals the input delay control word dcw;
(3) when the rising edge of the input clock comes, the discharging phase starts, and the switch SW1 is switched off; the switch SW2 is turned off, and the switched capacitor digital-to-analog converter 3 is disconnected from the discharge load capacitor 1; the switch SW0 is turned on, the charge in the discharge load capacitor 1 is discharged to ground through the discharge current source 2, and a voltage falling edge with a constant slope is output, when the voltage is smaller than the threshold voltage of the buffer 4, the output clock output by the buffer 4 generates a rising edge, and the delay between the rising edge and the rising edge of the input clock is controlled by the input delay control word dcw.
As shown in fig. 4 and 5, a conventional digital-to-time converter is usually implemented by using an adjustable buffer 4 and an adjustable load, when a conversion current or load of the buffer 4 changes, a slope of a transition edge of an output changes, and a time from a time when an input change crosses a threshold voltage to a time when an output change crosses the threshold voltage also changes, so that an adjustable delay time is implemented, which is called as a variable slope digital-to-time converter. The basic principle of a variable slope digital-to-time converter is to control the change in output along the slope. The digital-to-time converter of this architecture has limited linearity performance because there is no completely linear relationship between input control and delay variation. The constant slope digital-to-time converter provided by the invention discharges the discharge load capacitor 1 through the discharge current source 2 to generate a voltage falling edge with constant slope, and the initial discharge voltage is set by the switched capacitor digital-to-analog converter 3 and can be higher than the power supply voltage. Because the output change is constant along the slope, the discharge starting voltage and the output delay have higher linearity. The switched capacitor digital-to-analog converter 3 has the characteristics of low power consumption and low noise. Therefore, the constant slope digital-to-time converter provided by the invention has the characteristics of high performance and high energy efficiency.
Fig. 6 is a schematic diagram of a digital-to-time converter according to an embodiment of the present invention. When the falling edge of the input clock comes, in the voltage reset phase, the output voltage Vdac of the digital-to-analog converter is pulled to the power supply voltage Vdd, so that the buffer 4 outputs a falling edge; after a period of time delay, before the rising edge of the input clock comes, the input clock enters a voltage setting phase, and the initial discharge voltage is set; when the rising edge of the input clock comes, the discharging phase starts, the charge in the discharging load capacitor 1 is discharged to the ground through the discharging current source 2, a voltage falling edge with a constant slope is output, and when the voltage is smaller than the threshold voltage Vth of the buffer 4, the output clock generates a rising edge.
Fig. 7 is a timing diagram of the switched capacitor digital-to-analog converter 3 according to an embodiment of the present invention, which includes a voltage resetting phase, a voltage setting phase, and a discharging phase. In the switched capacitor digital-to-analog converter 3, in a voltage resetting phase, both ends of a load capacitor CT are connected to a power supply, a common end of a capacitor array and the load capacitor CT is also connected to the power supply, an actual delay control word dcw _ act connected to the other end is equal to a resetting control word dcw _ rst, an output end, namely the common end of the capacitor array and the load capacitor CT, is connected to a power supply Vdd, and a voltage Vdac is Vdd; in the voltage setting phase, one end of the load capacitor CT is connected to the power supply, the common end of the capacitor array and the load capacitor CT is an output end, the actual delay control word dcw _ act connected to the other end is equal to the input delay control word dcw, the common end voltage of the output end, namely the capacitor array and the load capacitor CT, is Vdac ═ Vdd · [ CT + (M-dcw _ rst + dcw) · Cu ]/(CT + M · Cu), where Cu is the value of the unit capacitor in the capacitor array, M is the total number of the unit capacitors in the capacitor array, dcw _ rst is the reset control word, dcw is the input delay control word, and Vdd is the power supply voltage, namely the voltage corresponding to the high level of the control word. Two clock phase control modes are used so that the output voltage Vdac can be higher than the supply voltage Vdd. When the reset control word dcw _ rst used in the voltage reset phase is smaller than the input delay control word, the output voltage Vdac > Vdd of the switched capacitor digital-to-analog converter 3 in the voltage setting phase; when the reset control word dcw _ rst used in the voltage reset phase is greater than the input delay control word, the switched-capacitor digital-to-analog converter 3 outputs the voltage Vdac < Vdd at the voltage set phase. When the rising edge of the input clock comes, the discharging load capacitor starts to be discharged, Vdac generates a falling edge with a fixed slope, and when the voltage is smaller than the threshold voltage Vth of the buffer 4, the output clock generates a rising edge. Specifically, the switch control method is as follows:
(1) in the voltage reset phase, switch SW0 is open; the switch SW1 is turned on, both ends of the discharge load capacitor 1 are connected to the power supply, the stored charge is 0, the output voltage is pulled to the power supply, and thus the buffer 4 outputs a falling edge; switch SW2 is open; the switch SW3 is turned on, and the common end of the load capacitor CT and the capacitor array in the switched capacitor digital-to-analog converter 3 is connected to the power supply; the actual delay control word dcw _ act is equal to the reset control word dcw _ rst;
(2) in the voltage set phase, switch SW0 is open; switch SW1 is open; the switch SW2 is turned on, the discharging load capacitor 1 is connected with the switched capacitor digital-to-analog converter 3, and the discharging initial voltage is set; switch SW3 is open and the actual delay control word dcw _ act is input equal to the input control word dcw;
(3) in the discharging phase, switch SW1 is open; the switch SW2 is turned off, and the switched capacitor digital-to-analog converter 3 is disconnected from the discharge load capacitor 1; the switch SW0 is turned on, the charge in the discharge load capacitor 1 is discharged to the ground through the discharge current source 2, a voltage falling edge with a constant slope is output, when the voltage is smaller than the threshold voltage of the buffer 4, the output clock generates a rising edge, and the delay between the rising edge and the rising edge of the input clock is controlled by the input delay control word dcw; the switch SW3 may be on or off.
In summary, the digital-to-time converter provided by the invention employs a switched capacitor digital-to-analog converter based on low noise and low power consumption, and is used for setting the initial discharge voltage of the output change edge, and setting the output change edge with constant slope through a current source with high linearity, so that the control relation from the input control word with high linearity to the output delay time is realized. Because the switched capacitor digital-to-analog converter is used, the initial discharge voltage can be higher than the power supply voltage, and the working voltage interval of the discharge current source is expanded to a range from higher voltage to threshold voltage, so that high linearity in a larger delay time range is realized. The digital-to-time converter has the characteristics of low noise and low power consumption, has high linearity and is very suitable for being applied to a fractional-frequency phase-locked loop.
While the present invention has been described in detail with reference to the preferred embodiments, it should be understood that the above description should not be taken as limiting the invention. Various modifications and alterations to this invention will become apparent to those skilled in the art upon reading the foregoing description. Accordingly, the scope of the invention should be determined from the following claims.
Claims (10)
1. A constant slope digital-to-time converter, comprising:
a discharge load capacitor for storing charge to discharge to generate a voltage falling edge;
the input end of the discharging current source is connected with the output end of the discharging load capacitor and is used for determining the slope of the falling edge of the output voltage according to the discharging current of the discharging load capacitor;
the output end of the switch capacitor digital-to-analog converter is connected with the output end of the discharge load capacitor and is used for setting the discharge starting voltage of the discharge load capacitor;
the input end of the buffer is connected with the output end of the switched capacitor digital-to-analog converter, and the buffer is used for converting the voltage falling edge discharged by the discharging load capacitor into a rising edge and providing stable output rising edge conversion rate;
and the output end of the clock and control signal generating circuit is respectively connected with the discharging load capacitor and the switched capacitor digital-to-analog converter and is used for receiving the input delay control word dcw and the input clock in and outputting the actual delay control word dcw _ act and a plurality of different clock phases.
2. The constant slope digital-to-time converter of claim 1, wherein the discharge current source comprises a current bias circuit, an nmos cascode current source, and a switch SW 0; the nmos cascode current source comprises an nmos common-source tube and an nmos common-gate tube; the grid electrode of the nmos common source tube is connected with a bias voltage Vbg1 provided by the current bias circuit; the grid electrode of the nmos common-grid tube is connected with a bias voltage Vbg2 provided by the current bias circuit; the source electrode input end of the nmos common-gate tube is connected with the output end of the discharge load capacitor; the source electrode output end of the nmos common-gate tube is connected with the source electrode input end of the nmos common-source tube; one end of the switch SW0 is connected with the source electrode output end of the nmos common-source tube, and the other end of the switch SW0 is grounded; the control terminal of the switch SW0 receives an input clock in.
3. The constant slope digital-to-time converter of claim 1, wherein said discharge load capacitance comprises a capacitance CL and a switch SW 1; one polar plate of the capacitor CL is connected with a power supply, and the other polar plate of the capacitor CL is connected with the output end of the switched capacitor digital-to-analog converter; two ends of the switch SW1 are respectively connected with two ends of the capacitor CL; the control terminal of the switch SW1 receives the clock phase ck1 output by the clock and control signal generation circuit.
4. The constant slope digital-to-time converter of claim 1, wherein the switched capacitor digital-to-analog converter comprises a load capacitor CT, a capacitor array consisting of capacitors C1-Cn, a switch SW2 and a switch SW 3; the load capacitor CT is connected with one end of a capacitor in the capacitor array; the other end of the load capacitor CT is connected with a power supply; the other end of the capacitor in the capacitor array receives the actual delay control word dcw _ act output by the clock and control signal generating circuit; one end of the switch SW2 is connected with the common end of the load capacitor CT and the capacitor array, and the other end of the switch SW2 is connected with the output end of the discharge load capacitor and the input end of the buffer; the control end of the switch SW2 receives the clock phase ck2 output by the clock and control signal generating circuit; two ends of the switch SW3 are respectively connected with two ends of the load capacitor CT; the control terminal of the switch SW3 receives the clock phase ck3 output by the clock and control signal generation circuit.
5. A constant slope digital to time converter as claimed in claim 4 wherein the actual delay control word dcw act received by the switched capacitor digital to analog converter is taken as a binary input and the capacitance Cn in the capacitor array has a magnitude of 2(n-1)Cu, where Cu is the unit capacitance magnitude in the capacitor array.
6. The constant slope digital-to-time converter of claim 1, wherein the switched capacitor digital-to-analog converter uses at least two clock phases:
voltage reset phase: both ends of the load capacitor CT are connected to a power supply; the common end of the capacitor array and the load capacitor CT is also connected to the power supply, and the actual delay control word dcw _ act received by the other end is equal to the reset control word dcw _ rst; the output voltage Vdac of the switched capacitor digital-to-analog converter is equal to the power supply voltage Vdd;
voltage setting phase: one end of the load capacitor CT is connected with a power supply; the common end of the capacitor array and the load capacitor CT is communicated with the output end of the discharge load capacitor and the input end of the buffer, and the actual delay control word dcw _ act received by the other end is equal to the input delay control word dcw; the output voltage Vdac of the switched capacitor digital-to-analog converter is Vdd · [ CT + (M-dcw _ rst + dcw) · Cu ]/(CT + M · Cu), where Cu is the unit capacitance of the capacitor array, and M is the total number of capacitors in the capacitor array.
7. The constant slope digital-to-time converter of claim 6, wherein the output voltage Vdac > Vdd for the switched capacitor digital-to-analog converter at the voltage set phase when the reset control word dcw rst used in the voltage reset phase is less than the input delay control word dcw; when the reset control word dcw _ rst used in the voltage reset phase is greater than the input delay control word dcw, the output voltage Vdac < Vdd of the switched-capacitor digital-to-analog converter at the voltage set phase.
8. The constant slope digital to time converter of claim 1, wherein for the buffer: when the input voltage crosses its threshold voltage from high to low, a rising edge is output, whereas when the input voltage crosses its threshold voltage from low to high, a falling edge is output, which is output as the output clock out of the digital-to-time converter.
9. The constant slope digital to time converter of claim 1, wherein the input clock in cycles divided into 3 clock phases, comprising:
voltage reset phase, switch SW0 open; switch SW1 is ON; switch SW2 is open; switch SW3 is on and the actual delay control word dcw _ act equals the reset control word dcw _ rst;
voltage set phase, switch SW0 open; switch SW1 is open; switch SW2 is ON; switch SW3 is open and the actual delay control word dcw _ act equals the input delay control word dcw;
discharge phase, switch SW0 is on; switch SW1 is open; switch SW2 is open.
10. A method of controlling a constant slope digital to time converter as claimed in any one of claims 1 to 9, comprising the steps of:
(1) when the falling edge of the input clock comes, in the voltage reset phase, the switch SW0 is turned off; the switch SW1 is turned on, both ends of the discharging load capacitor are connected to the power supply, the stored charge is 0, the output voltage is pulled to the power supply, and at this time, the buffer outputs a falling edge; switch SW2 is open; the switch SW3 is turned on, and the common end of the load capacitor CT and the capacitor array in the switched capacitor digital-to-analog converter is connected to the power supply; the actual delay control word dcw _ act is equal to the reset control word dcw _ rst;
(2) after a period of time delay, before the rising edge of the input clock comes, the input clock enters a voltage setting phase, and the switch SW0 is switched off; switch SW1 is open; the switch SW2 is turned on, the discharging load capacitor is connected with the switch capacitor digital-to-analog converter, and the discharging initial voltage is set; switch SW3 is open and the actual delay control word dcw _ act equals the input delay control word dcw;
(3) when the rising edge of the input clock comes, the discharging phase starts, and the switch SW1 is switched off; the switch SW2 is disconnected, and the switched capacitor digital-to-analog converter is disconnected with the discharging load capacitor; the switch SW0 is turned on, the charge in the discharge load capacitor is discharged to ground through the discharge current source, a voltage falling edge with a constant slope is output, when the voltage is smaller than the threshold voltage of the buffer, the output clock of the buffer output generates a rising edge, and the delay between the rising edge and the rising edge of the input clock is controlled by the input delay control word dcw.
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