CN117555212A - Time delay module, time-to-digital converter, system and method - Google Patents
Time delay module, time-to-digital converter, system and method Download PDFInfo
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Abstract
The application relates to a delay module, a time-to-digital converter, a system and a method, wherein the delay module comprises: an input unit configured to acquire a signal to be measured; a delay adjustment unit coupled to the input unit and configured to perform a first delay adjustment on the signal to be measured, wherein the delay adjustment unit comprises a capacitor array that provides a capacitance value corresponding to the first control signal under the influence of the first control signal; and an output unit coupled to the delay adjustment unit and configured to provide an output signal based on the delay-adjusted signal to be measured. The delay module in the method can reduce mismatch errors, so that linearity and measurement accuracy of the TDC system are improved.
Description
Technical Field
The present application relates to the field of integrated circuits, and in particular to a delay module, a time-to-digital converter, a system and a method.
Background
The high-precision time-to-digital converter is used as a precise time interval measurement technology and has wide application in the fields of high-energy physical experiments, medical imaging, laser radar, topographic mapping and the like. The time-to-digital converter is capable of converting the time interval into a binary digital signal, which is further processed to obtain a specific time interval length. The measurement accuracy of the time-to-digital converter often determines the data accuracy of the measurement system, so in order to improve the measurement accuracy of the time-to-digital converter, research in the field of time interval measurement has been increasingly conducted in recent years.
The design of the time-to-digital converter is generally realized by adopting an Application Specific Integrated Circuit (ASIC) design, so that the design with higher precision and lower power consumption can be realized, but the design period is long and the cost is relatively high. In addition, since the delay time of the designed delay module is larger or smaller than the ideal delay due to the inherent error and mismatch error in the system, the linearity and measurement accuracy of the time-to-digital converter are reduced, and therefore calibration is needed to improve the measurement accuracy of the time-to-digital converter.
Common calibration methods for time-to-digital converters are largely divided into average calibration and bitwise calibration. The average calibration can quickly calibrate the time-to-digital converter, but only the average delay time of all delay module taps is obtained, and each delay module tap in the time-to-digital converter cannot be calibrated bit by bit, which can lead to a large measurement error. The bit-by-bit calibration criterion is to calibrate each delay module tap in the cascade delay chain, which is generally realized by a code density method, and the delay time of each delay unit tap can be accurately calibrated by inputting a random signal to count the jump number of the delay module tap.
Therefore, a low cost, high precision time-to-digital converter is needed.
Disclosure of Invention
Aiming at the technical problems in the prior art, the method and the device for adjusting the delay time of the time delay module through the programmable adjustment improve the linearity and the precision of the time data converter.
In one aspect, the present application proposes a delay module, which includes: an input unit configured to acquire a signal to be measured; a delay adjustment unit coupled to the input unit configured to perform a first delay adjustment on the signal to be measured, wherein the delay adjustment unit comprises a capacitor array providing a capacitance value corresponding to a first control signal under the influence of the first control signal; and an output unit coupled to the delay adjustment unit configured to provide an output signal based on the delay-adjusted signal to be measured.
In one embodiment, the capacitor array comprises a plurality of capacitor branches in parallel, the plurality of capacitor branches being selectively coupled to the output unit under the influence of the first control signal, wherein the capacitor branches comprise capacitors.
In one embodiment, the delay module further comprises: and a decoding unit configured to generate a switching signal based on the first control signal, and at least one capacitor branch of the plurality of capacitor branches is selected and electrically connected to an input terminal of the output unit in response to the switching signal, wherein the number of bits of the first control signal is less than or equal to the number of bits of the switching signal.
In one embodiment, the capacitance values of the capacitors in the plurality of capacitor branches are equal.
In an embodiment, the capacitor branch further comprises a switch in series with the capacitor, the capacitor being implemented by a transistor, wherein a gate of the transistor is coupled to the input of the output unit via the switch, a source of the transistor is connected to a drain and coupled to a low potential, the switch being closed or opened in dependence of the switching signal.
In one embodiment, the delay module further comprises: and a voltage-controlled current source coupled to the input unit to perform a second delay adjustment on the signal to be measured under the influence of a second control signal, wherein the range of the second delay adjustment is larger than the range of the first delay adjustment, and the precision of the second delay adjustment is lower than the precision of the first delay adjustment.
In one embodiment, the voltage controlled current source includes a control transistor having a gate receiving the second control signal, a source coupled to a low potential, and a drain coupled to the input unit.
Another aspect of the present application proposes a time-to-digital converter comprising: a plurality of cascaded delay modules as previously described; the data input ends of the triggers are respectively coupled to the output end of each delay module and are configured to receive the output signals of the delay modules, the set ends of the triggers receive sampling control signals and are configured to respond to the sampling control signals to sample the output signals of the delay modules; and an encoder coupled to the outputs of the plurality of flip-flops and configured to generate encoded signals corresponding to the output signals of the plurality of delay modules.
Another aspect of the present application proposes a time-to-digital conversion system comprising: a time-to-digital converter as described above; the transmitter is configured to transmit a detection signal to an object to be detected and trigger the time-to-digital converter to start timing; the receiver is configured to receive a reflected signal from the object to be detected and trigger the time-to-digital converter to stop timing; and a calibrator configured to provide a random signal to said time-to-digital converter, to determine a delay time for each of said delay modules in said time-to-digital converter, and to adjust a capacitance value of a capacitor array in each of said delay modules based on said delay time.
Another aspect of the present application proposes a calibration method for a time-to-digital converter, comprising: providing a random signal; performing jump sampling on the output signals of the delay modules to generate code density information, and determining delay time of each delay module; and based on the delay time, respectively adjusting the capacitance value provided by the capacitor array in each delay module so as to adjust the delay time of each delay module.
The delay time of each delay module is corrected by adjusting the number of the switch capacitors in the delay module, so that mismatch errors among the modules are reduced, and the linearity and measurement accuracy of the TDC system are improved. In addition, after the delay module in the application is adopted, a lookup table is not required to be generated, so that the design difficulty and cost are reduced, and the delay module can be calibrated by adopting background calibration measurement, and has good universality in a tap delay chain TDC and a vernier TDC.
Drawings
Preferred embodiments of the present application will be described in further detail below with reference to the attached drawing figures, wherein:
FIG. 1 is a schematic diagram of a delay module according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a delay module according to another embodiment of the present application;
FIG. 3 is a schematic diagram of a decoding unit according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a delay chain type time-to-digital converter according to an embodiment of the present application;
FIG. 5 is a schematic diagram of a delay of a time-to-digital converter without delay adjustment;
FIG. 6 is a diagram showing the number of hops of a delay module without delay adjustment;
FIG. 7 is a schematic diagram of a delay time of a delay module without delay adjustment;
FIG. 8 is a schematic diagram of a calibration method according to an embodiment of the present application;
FIG. 9 is a schematic diagram of a delay time of a delay-adjusted time-to-digital converter;
fig. 10 is a schematic diagram of a time-to-digital converter system with calibration function according to an embodiment of the present application.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the application may be practiced. In the drawings, like reference numerals describe substantially similar components throughout the different views. Various specific embodiments of the present application are described in sufficient detail below to enable those skilled in the art to practice the teachings of the present application. It is to be understood that other embodiments may be utilized or structural, logical, or electrical changes may be made to the embodiments of the present application.
Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail, but are intended to be part of the specification where appropriate. For the purpose of illustration only, the connection between elements in the figures is meant to indicate that at least the elements at both ends of the connection are in communication with each other and is not intended to limit the inability to communicate between elements that are not connected. In addition, the number of lines between two units is intended to mean at least the number of signals involved in communication between the two units or at least the output terminals provided, and is not configured to limit the communication between the two units to only signals as shown in the figures.
In the prior art, the code density calibration test generates a large number of random time interval signals to be input into the time-to-digital converter for quantization and statistics analysis, so as to calibrate the delay time of the delay module in the time-to-digital converter, and a lookup table is generated according to the statistics result, and the output digital code value is used for outputting the actual time interval of each delay module. Because of the integrated circuit manufacturing process problem, there is a mismatch error between delay modules in each time-to-digital converter chip, resulting in poor measurement linearity and reduced accuracy, and an integrated calibrator is also required in the chip to perform code density testing on each time-to-digital converter and generate a corresponding look-up table, which greatly increases the complexity and cost of TDC design.
Aiming at the problems, the application provides a programmable delay module for overcoming the defects in the prior art, and the programmable delay module is subjected to statistical analysis to generate a logic control strategy for the programmable delay module so as to compensate the linearity of the time-digital converter and improve the measurement accuracy of a measurement system.
Fig. 1 is a schematic diagram of a delay module according to an embodiment of the present application, and fig. 3 is a schematic diagram of a decoding unit according to an embodiment of the present application. As shown in fig. 1, the delay module includes an input unit 11 configured to acquire an input signal (signal to be measured); an output unit 12 configured to provide an output signal based on the delay-adjusted signal to be measured, i.e., to provide the output signal with a specified delay time; the delay adjustment unit 13 is coupled between the input unit 11 and the output unit 12, and under the influence of the first control signal, the delay adjustment unit 13 provides a capacitance corresponding to the first control signal, so that the output unit 12 provides an output signal based on the delay-adjusted input signal.
Specifically, the input unit 11 includes transistors M1, M2 connected in series, and gates of the two transistors are connected. The source of the transistor M1 is coupled to the high level VDD, the drain thereof is connected to the drain of the transistor M2, and the source of the transistor M2 is coupled to the low level GND. Similarly, the output unit 12 includes transistors M3, M4 connected in series, and the gates of the two transistors are connected to the output terminal of the input unit 11. The source of the transistor M3 is coupled to the high level VDD, the drain thereof is connected to the drain of the transistor M4, and the source of the transistor M4 is coupled to the low level GND.
In one embodiment, delay adjustment unit 13 comprises a capacitor array comprising a plurality of capacitor branches connected in parallel with each other, wherein each capacitor branch comprises a capacitor C0-C7, and a respective switch S0-S7. Specifically, a capacitor Ci is connected in series with the switch Si and is coupled between node A and a low potential, where i ε [0,7]. When the switch Si is closed, the corresponding capacitor Ci will be electrically connected to node a, i.e. (output of input unit 11, input of output unit 12); when the switch Si is opened, the corresponding capacitor Ci is then disconnected from node a. In the present embodiment the capacitor is realized by a capacitive transistor, i.e. the gate of the capacitive transistor Ci is coupled to the input of the output unit 12 via a switch Si, the source of the capacitive transistor Ci being connected to the drain and coupled to a low potential.
For convenience of description, the present embodiment temporarily does not consider the influence of parasitic capacitance of each transistor in the input unit 11 and the output unit 12 on the node a. Based on this premise, the speed of the potential change of node a depends on the number of access circuits in the capacitor array. Therefore, when the capacitors C0-C7 are selectively coupled to the output of the input unit under the influence of the first control signal, the capacitance value at the node a will change, thereby affecting the rate of change of the potential of the node a.
When the input signal received at the input terminal IN is inverted from low to high, the potential of the node a is inverted from high to low, and at this time, the capacitor connected to the circuit is discharged through the transistor M2. Also, when the input signal received at the input terminal IN is inverted from a high level to a low level, the potential of the node a increases from the low level to the high level, and at this time, the capacitor connected to the circuit is charged through the transistor M1, thereby raising the potential of the node a. As will be appreciated by those skilled in the art, the time for which the capacitor charges and discharges is proportional to the capacitance value. Thus, under the influence of the capacitor array, the delay time T1 of the delay block (i.e., the potential inversion time of the node a) can be approximately expressed as:
T1 = k·RC A （1）
in the formula (1), R is the resistance on a charge-discharge circuit, C A The effective capacitance value of the node A, k is a parameter of charge and discharge time. Here, C A Is the sum of the capacitances of the capacitors in the capacitor array that are connected to the circuit.
When the delay module is applied to a time-to-digital converter, the delay times of a plurality of delay modules in the delay chain may need to be adjusted to be uniform, i.e. each delay module may need to be adjusted in a targeted manner, in other words, the effective capacitance value provided by the capacitor array in each delay module may be different. In the present embodiment, the control of the states of the switches (i.e. switches S <0> to S <7 >) is achieved by a programmable first control signal, so that a plurality of capacitors are selectively coupled to the input unit 11 for delay adjustment of the signal to be measured.
The delay module further includes a decoding unit 14 to generate a switching signal based on the first control signal (e.g., signals D <2:0 >). In response to the switching signal, at least one capacitor of the capacitor array is selected and electrically connected to the output of the input unit 11. Specifically, the upper controller (e.g., a calibrator implemented by MCU, CPU, ASIC or FPGA) generates the first control signal based on the delay requirement, and it is understood that the first control signal includes capacitance information corresponding to the delay requirement. After receiving the first control signal, the decoding unit 14 generates a switching signal to control on/off of the switches (for example, the switches S <0> to S <7 >) so as to realize that one or more capacitors are connected into the circuit, change the capacitance value at the node a, and adjust the delay time of the delay module.
In one embodiment, the number of bits of the first control signal is less than the number of bits of the switching signal, so that more capacitors can be controlled with control signals having fewer data bits (e.g., 2 bits, 3 bits). For example, the decoding unit may be a thermometer code decoder or a programmable decoder, etc. Taking a 3bit binary code to thermometer code decoder as an example, a maximum of eight switches can be selectively operated by a three bit control signal, such as selecting one or more switches, so that the corresponding capacitors are connected to the circuit. Table 1 shows the correspondence of binary control signals of decoders employing 3bit binary code to thermometer code and switching signals (8 bit thermometer code control signals).
Table 1 correspondence between control signals and switching signals
In one embodiment, the number of capacitors selected at a time or the particular capacitor branch may be determined based on the switching signal.
Case 1: at least one capacitor branch is selected at a time:
in this case, when the delay time needs to be raised, the number of capacitors connected to the circuit will be increased; when the delay time needs to be reduced, the number of capacitors connected to the circuit will be reduced. For example, when the control signal changes from 001 to 011, the number of capacitors connected to the circuit can be increased from 2 to 4; when the control signal changes from 111 to 011, the number of capacitors connected to the circuit can be reduced from 8 to 4. In this way, the capacitance value at node a will be increased. It will be appreciated that the capacitance values of the plurality of capacitors in the capacitor array may or may not be equal, i.e. the capacitance values of the 8 capacitors are equal; or, the capacitance values of the 8 capacitors are in a certain proportional relationship, specifically, the capacitance values can be adjusted according to application scenes, and detailed description is omitted here.
Case 2: one capacitor leg at a time is selected:
in this case, in response to the switching signal, one capacitor at a time will be selected, at which time the capacitance values of the plurality of capacitors in the capacitor array are unequal. Therefore, when the delay time needs to be increased, a capacitor with larger capacitance is selected to be connected into the circuit; when the delay time needs to be reduced, a capacitor with a smaller capacitance will be selected to be connected to the circuit. For example, when the control signal changes from 001 to 011, the capacitor that is connected will change from capacitor C1 to capacitor C4. Through the arrangement, the capacitor array in each delay module can be subjected to the appointed arrangement according to scene requirements, and then the delay time of the delay module can be adjusted.
It will be appreciated that the accuracy of the delay adjustment in this embodiment is related to the value of each capacitor. For example, when the capacitors are equal, the capacitance at node A ranges from 0-C, and the corresponding adjustment unit is C/8. Thus, the accuracy t of the adjustment of the delay time affected by the capacitor array can be expressed as:
t= k·RC/8 （2）
in the formula (2), R is a resistance on the charge-discharge circuit, C is a maximum effective capacitance value of the node a (a maximum capacitance of the capacitor array), and k is a parameter of charge-discharge time.
Fig. 2 is a schematic diagram of a delay module according to another embodiment of the present application.
Compared to the delay module in fig. 1, the delay module in fig. 2 further includes a voltage-controlled current source 15 for performing delay adjustment of the signal to be measured with a second accuracy (i.e., a larger range). In the present embodiment, the voltage-controlled current source 15 is realized by controlling the transistor M5.
As shown in fig. 2, the gate of the control transistor M5 is configured to receive a second control signalV ctrl The source is coupled to the low level GND and the drain is connected to the source of the transistor M2. When the second control signal V ctrl Generating a bias current I above the threshold voltage of transistor M2 bias ，V ctrl The greater the voltage is the bias current I bias The larger the delay time is, the smaller the delay time is, whereas the bias current I is bias The smaller the delay time is, the larger the second control signal V is ctrl When the threshold voltage of the transistor M2 is smaller, the transistor M2 is cut off, and the circuit cannot work normally. By varying the bias current I bias The time for the node a to flip from high to low can be influenced, thereby changing the variation time of the output signal of the output unit 12 and realizing the adjustment of the delay time.
From the above, the second control signal V ctrl The voltage of the delay module can be adjusted to prolong the time of the delay module, and a larger range of adjustment can be realized, and the delay time T2 of the delay module can be expressed as:
wherein R is a resistor input to the charge-discharge circuit, C A Is the effective capacitance value of node A, V swing For the voltage variation swing on node A, I bias A bias current generated for a voltage controlled current source. Optionally, a second control signal V ctrl The adjustment accuracy of (2) is lower than that of the first control signal, i.e., the minimum variation of adjustment T2 is greater than that of adjustment T1. Thus, the second control signal V can be passed ctrl To determine an approximate adjustment target for the delay time and then to use the control of the capacitor array by the first control signal to make an accurate adjustment to the delay time.
Fig. 4 is a schematic diagram of a delay chain type time-to-digital converter according to an embodiment of the present application.
As shown, the delay chain type time-to-digital converter includes a delay module group, a flip-flop group, and an encoder. The delay module group comprises a plurality of cascaded delay modules 31i, each delay module having a respective delay time; the trigger group includes a plurality of triggers 32i, and a data input terminal of each trigger is connected to an output of each delay module 31i, and configured to obtain an output signal of the delay module 31 i. The encoder 33 receives the output signal from the flip-flop 32i and generates an encoded signal based on a preset decoding strategy. In this embodiment, the flip-flop 32i is a D flip-flop, and it is understood that the flip-flop 32i may be another type of flip-flop.
The measurement principle of the time-to-digital converter is explained below:
the signal START to be measured sequentially passes through the delay modules 31i of different numbers and then reaches the data input terminal (D terminal) of the D flip-flop 32i in the flip-flop group, and the sampling control signal STOP is input to the set terminal (CLK terminal) of the D flip-flop. The START signal in the form of a step is input to the delay chain, delayed and reaches the D terminal of the D flip-flop, at which point the D terminal is set high. At some later point in time, the rising edge of the STOP signal is input to the CLK terminal of D flip-flop 32i, and since the START signal will go through a series of basic delay blocks 31i during transmission, when the rising edge of the STOP signal arrives, flip-flop 32i will sample the delay chain, the output of all the D flip-flops that the START signal arrives is "1", while the output of the D flip-flops that do not arrive is still 0, thus producing a thermometer code such as "1 … 1100 … 0". The number of '1's in the thermometer code is used to measure the time interval between the START signal and the STOP signal, and finally the thermometer code obtains the output digital code after coding. If the delay of the single delay module is τ, the number of D flip-flops outputting 1 is N, and the time interval T quantized by the time-to-digital converter can be expressed as:
T =N·τ （4）
it will be appreciated that the linearity of the time to digital converter measurement will be affected when the delays of the delay modules are not equal. For this reason, the delay time of each delay module needs to be adjusted so that the delay modules on the delay chain have substantially the same delay time.
According to the method and the device, the adjustment of each delay module is achieved through code density testing. In particular, a large number of random pulses uniformly distributed over the measuring range are used as input signals to be measured by the time-to-digital converter, and because the input signals are random, the probability of the signals falling at each point in the measuring range is equal. If the delays of each delay module are identical, the number of each output of the time-to-digital converter is equal. If there is mismatch between the delay modules, each output of the time-to-digital converter will appear different times according to the difference of the delay time of the delay module, the times of falling on each delay module are recorded, when the samples of the random pulse are enough, the delay time will be proportional to the number of events, so that the relative magnitude of the delay of each delay module and the delay time of the whole delay chain can be obtained according to the difference of the number of events. Through the above process, the actual value of each delay module can be estimated.
Before delay adjustment, each delay module on the delay chain has different delay times, and when the delay module is measured in a code density manner, the number of hops of each delay module can be counted (as shown in fig. 6), and the specific delay time of each delay module can be determined by calibrating the delay module, and fig. 7 shows the specific delay time of each delay module.
In order to maintain the linearity of the time-to-digital converter, the delay time of each delay module needs to be adjusted so that each delay module on the delay chain has substantially the same delay time.
Fig. 8 is a schematic diagram of a calibration method according to an embodiment of the application.
Step S801: generating a plurality of random signals
In this step, a large number of random pulses uniformly distributed in the measuring range are generated by the calibrator as input signals to be measured by the time-to-digital converter, and because the input signals are random, the probability of the signals falling on each point in the measuring range is equal. If the delays of each delay module are identical, the number of each output of the time-to-digital converter is equal.
Step S802: and acquiring a sampling result of the time-to-digital converter and determining code density information.
In this step, the time-to-digital converter performs a jump sampling with respect to the random signal, and generates code density information corresponding to each delay module. When the delay time of each delay module is different, the corresponding code density of each delay module is also different.
Step S803: the delay ratio of each delay module is determined based on the code density information.
In this step, the delay proportion of each delay module is determined based on the corresponding code density of each delay module, so as to calibrate each delay module later.
Step S804: and determining an adjustment strategy based on the delay proportion, and adjusting the delay time of each delay module.
In this step, an adjustment policy will be determined based on the delay ratio acquired in the previous step. It will be appreciated that the actual delay time of each delay module may be determined by calibration based on the delay ratio. Thus, the adjustment can be made separately for each delay module. For example, when the delay time of the delay module needs to be reduced, the number of capacitors connected in the delay module is reduced; conversely, the number of capacitors connected in the delay module will be increased.
As shown in fig. 9, after delay adjustment, each delay module on the delay chain has the same delay time, when the code density mode is adopted for measurement, the number of hops of each delay module can be counted to be the same, and the specific delay time of each delay module can be determined by calibrating the delay modules.
Fig. 10 is a schematic diagram of a time-to-digital converter system with calibration function according to an embodiment of the present application.
As shown, the time-to-digital converter system includes a transmitter 71, a receiver 72, a time-to-digital converter 73, and a calibrator 74. Specifically, the transmitter 71 transmits a detection signal to the object to be measured while triggering the time-to-digital converter 73 to start timing; after receiving the reflected detection signal of the object to be detected, the receiver 72 stops the time counting by triggering the time-to-digital converter 73 and samples the signal. The time-to-digital converter 73 generates a corresponding output (B based on the result of the sampling N B N-1 ……B 0 ). When the time-to-digital converter 73 needs calibration, the calibrator 74 provides a random signal to the time-to-digital converter 73 to determine the delay time of each delay module of the TDC, and adjusts the delay time of each delay module by adjusting the capacitor array in each delay module, so that the time-to-digital converter 73 has good linearity.
It will be appreciated that the calibrators and time to digital converters referred to in this application may be implemented by digital signal processor (Digital Signal Processor, DSP), programmable logic gate array (Field Programmable Gate Array, FPGA) or analog to digital converter (Analog Digital Converter, ADC) chips. The delay time of each delay module is corrected by adjusting the number of the switch capacitors in the delay module, so that mismatch errors among the modules are reduced, and the linearity and measurement accuracy of the TDC system are improved. In addition, after the delay module in the application is adopted, a lookup table is not required to be generated, so that the design difficulty and cost are reduced, and the delay module can be calibrated by adopting background calibration measurement, and has good universality in a tap delay chain TDC and a vernier TDC.
The above embodiments are provided for illustrating the present application and are not intended to limit the present application, and various changes and modifications can be made by one skilled in the relevant art without departing from the scope of the present application, therefore, all equivalent technical solutions shall fall within the scope of the present disclosure.
Claims (10)
1. A delay module, comprising:
an input unit configured to acquire a signal to be measured;
a delay adjustment unit coupled to an output of the input unit and configured to perform a first delay adjustment on the signal to be measured, wherein the delay adjustment unit includes a capacitor array that provides a capacitance value corresponding to a first control signal under the influence of the first control signal; and
an output unit coupled to the delay adjustment unit and configured to provide an output signal based on the delay-adjusted signal to be measured.
2. The delay module of claim 1 wherein the capacitor array comprises a plurality of capacitor branches in parallel, the plurality of capacitor branches selectively coupled to the output unit under the influence of the first control signal, wherein the capacitor branches comprise capacitors.
3. The delay module of claim 2, further comprising:
and a decoding unit configured to generate a switching signal based on the first control signal, and at least one capacitor branch of the plurality of capacitor branches is selected and electrically connected to an input terminal of the output unit in response to the switching signal, wherein the number of bits of the first control signal is less than or equal to the number of bits of the switching signal.
4. A delay module as recited in claim 3, characterized in that the capacitance values of the capacitors in the plurality of capacitor branches are equal.
5. A delay module as recited in claim 3, wherein the capacitor branch further comprises a switch in series with the capacitor, the switch being closed or opened under the influence of the switching signal, the capacitor comprising a capacitive transistor,
the grid electrode of the capacitor transistor is coupled to the input end of the output unit through the switch, and the source electrode and the drain electrode of the capacitor transistor are connected and coupled to a low potential.
6. The delay module of claim 1, further comprising:
and a voltage-controlled current source coupled to the input unit to perform a second delay adjustment on the signal to be measured under the influence of a second control signal, wherein the range of the second delay adjustment is larger than the range of the first delay adjustment, and the precision of the second delay adjustment is lower than the precision of the first delay adjustment.
7. The delay module of claim 6 wherein the voltage controlled current source comprises a control transistor having a gate receiving the second control signal, a source coupled to a low potential, and a drain coupled to the input cell.
8. A time-to-digital converter, comprising:
a plurality of cascaded delay modules as claimed in any one of claims 1 to 7;
the data input ends of the plurality of triggers are respectively coupled to the output end of each delay module, the setting end of each trigger receives a sampling control signal, and the triggers respond to the sampling control signals to sample the output signals of the delay modules; and
an encoder coupled to the outputs of the plurality of flip-flops is configured to generate encoded signals corresponding to the output signals of the plurality of delay modules.
9. A time to digital conversion system, comprising:
the time-to-digital converter of claim 8;
the transmitter is configured to transmit a detection signal to an object to be detected and trigger the time-to-digital converter to start timing;
the receiver is configured to receive a reflected signal from the object to be detected and trigger the time-to-digital converter to stop timing; and
a calibrator configured to provide a random signal to said time-to-digital converter, to determine a delay time for each of said delay modules in said time-to-digital converter, and to adjust a capacitance value of a capacitor array in each of said delay modules based on said delay time.
10. A calibration method for a time-to-digital converter as claimed in claim 8, comprising:
providing a random signal;
performing jump sampling on the output signals of the delay modules to generate code density information, and determining delay time of each delay module; and
and respectively adjusting the capacitance value provided by the capacitor array in each delay module based on the delay time so as to adjust the delay time of each delay module.
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