WO2021090860A1 - Analog device, method for controlling same, temperature sensor, and analog-element-associated system - Google Patents

Abstract

The present invention estimates the value of a threshold-value voltage of a transistor related to operation of a temperature sensor. Each of a plurality of transistors (Mn) that perform analog operations has: a threshold-value voltage related to operation of a temperature sensor (1), the threshold-value voltage being such that variation therein follows a statistical distribution; and a sub-threshold leak current corresponding to the threshold-value voltage. A control device (2) sequences the plurality of transistors (Mn) in accordance with a measurement value of the sub-threshold leak current, and associates the value of the threshold-value voltage and the transistors (Mn) on the basis of the statistical distribution pertaining to the threshold-value voltage and the sequence of the transistors (Mn).

Description

Analog devices and their control methods, temperature sensors, and analog element mapping systems

The present invention relates to an analog device provided on an IC (integrated circuit) chip, a control method thereof, a temperature sensor, and an analog element association system.

In a CMOS ((Complementary Metal Oxide Semiconductor)) process, mounting a digital circuit and an analog circuit on a single IC chip has the advantages of miniaturization, high-speed operation, and low power consumption. However, MOS One of the problems in designing analog devices using transistors is the variation in device characteristics that occurs during manufacturing. As the process becomes finer, the variation in transistors increases, which causes analog. The variation in the characteristics of the device becomes large. As a result, the analog device may not achieve a predetermined performance.

In order to suppress variations in the characteristics of the analog device, it is conceivable to increase the area of the analog device. However, in this case, not only the size of the analog device is increased, but also the power consumption and the manufacturing cost are increased.

In response to the above problems, Non-Patent Documents 1 and 2 disclose a flash type ADC (Analog-to-Digital Converter) that converts an analog signal into a 6-bit digital signal. In the ADC, 63 comparators into which the analog signals are input and a decoder that converts the signals from the 63 comparators into 6-bit digital signals are provided on a single IC chip. There is. Each of the comparators utilizes the fact that the offset voltage follows a normal distribution, and uses the offset voltage as a reference for AD conversion instead of the reference voltage.

In the case of the above ADC, it is not necessary to suppress the above variation because the variation of the offset voltage of the comparator (the variation of the device characteristics) is used. Therefore, it is not necessary to increase the area of the comparator, and it is possible to suppress an increase in power consumption and manufacturing cost.

On the other hand, it is necessary to accurately measure the offset voltage of each comparator. However, it is difficult to accurately measure the offset voltage in the IC chip (on-chip). Further, when measuring the offset voltage with a measuring device outside the IC chip, a high-performance measuring device is required, and an output port for measuring the offset voltage needs to be provided on the IC chip. ..

One aspect of the present invention is to realize an analog device or the like capable of estimating the value of the first characteristic of an analog element related to the operation of the analog device.

The analog device according to one aspect of the present invention is an analog device provided on an IC chip, and the analog device includes a plurality of analog elements that perform analog operation and a control device that controls the operation of the analog device. Each of the analog elements has a first characteristic related to the operation of the analog device, a first characteristic whose variation follows a statistical distribution, and a second characteristic related to the first characteristic, which are on. The control device has a second characteristic that can be measured by a chip, and the control device orders a plurality of the analog elements according to the measured value of the second characteristic, and the statistical distribution regarding the first characteristic and the order of the analog elements. It is characterized in that the value of the first characteristic is associated with the analog element based on the above.

Further, in the capacitor device according to this aspect, it is preferable that the control device operates the analog element corresponding to a predetermined value of the first characteristic. The control device may stop analog elements other than the analog element corresponding to the predetermined value of the first characteristic.

Further, the capacitor device according to this aspect further includes a measuring device for measuring the second characteristic, and the control device orders a plurality of the analog elements according to the measured value of the second characteristic measured by the measuring device. You may.

In one example, the analog element is a transistor, the first characteristic of the analog element is the threshold voltage of the transistor, and the second characteristic of the analog element is the subthreshold leakage current of the transistor. Be done.

In another example, the analog element is a comparator, the first characteristic of the analog element is the offset voltage of the comparator, and the second characteristic of the analog element is a plurality of characteristics included in the comparator. This is the difference between the output voltage when the operation of a part of the transistors is stopped and the output voltage when the operation of the other part of the plurality of transistors is stopped.

Another method of controlling an analog device according to another aspect of the present invention is an analog device provided on an IC chip, wherein the analog device includes a plurality of analog elements that perform analog operation, and each of the analog elements. Is a first characteristic related to the operation of the analog device, a first characteristic in which the variation follows a statistical distribution, and a second characteristic related to the first characteristic, which is a second characteristic that can be measured on-chip. A method of controlling an analog device having the above, based on a step of ordering a plurality of the analog elements according to the measured value of the second characteristic, the statistical distribution regarding the first characteristic, and the order of the analog elements. It is characterized by including a step of associating a value of one characteristic with the analog element.

The temperature sensor according to still another aspect of the present invention is a temperature sensor provided on an IC chip, which is a capacitor, a plurality of transistors connected in parallel to the capacitor, the capacitor, and the plurality of transistors, respectively. A plurality of switching elements provided between the two and a control device for controlling the plurality of switching elements are provided, and the control device is such that the current from the capacitor is the transistor for each of the plurality of transistors. It is characterized in that the discharge time until the voltage of the capacitor drops to a predetermined voltage is measured, and the ratio of at least two discharge times of the plurality of transistors is output as temperature information.

The temperature sensor according to another aspect of the present invention includes a plurality of analog elements that are provided on an IC chip and perform analog operation, and a control device that controls the operation of the analog element, and each of the analog elements has a control device. The control device has a first characteristic in which the variation follows a statistical distribution and a second characteristic related to the first characteristic, which can be measured on-chip, and the control device has a measured value of the second characteristic. A plurality of the analog elements are ordered according to the above, and the value of the first characteristic is associated with the analog element based on the statistical distribution regarding the first characteristic and the order of the analog elements.

According to one aspect of the present invention, there is an effect that the value of the first characteristic of the analog element related to the operation of the analog device can be estimated.

It is a circuit diagram which shows the schematic structure of the temperature sensor which concerns on one Embodiment of this disclosure. It is a circuit diagram which shows one structural example of the switching part in the said temperature sensor. It is a flow chart which showed the operation example of the said temperature sensor. It is a flow diagram which showed an example of the subroutine included in the said flow. It is a circuit diagram for demonstrating the measurement principle of the said temperature sensor. It is a figure of the graph which shows an example of the voltage-current characteristic of the 1st and 2nd transistors. It is a figure which shows the variation of the threshold voltage in the analog transistor group of the said temperature sensor. It is a figure of the graph which shows the correspondence relationship between the temperature and the discharge time ratio in the temperature sensor which concerns on another embodiment of this disclosure. It is a figure of the graph which shows the relationship between the threshold voltage difference of a transistor in the said temperature sensor, and the coefficient of determination adjusted for degrees of freedom. It is a figure of the graph which shows the correspondence relationship between the temperature and the discharge time ratio in the said temperature sensor. It is a figure of the graph which shows the error of the calculated temperature in the said temperature sensor. It is a circuit diagram which shows one structural example of the switching part in the said temperature sensor. This is an equivalent circuit when the first transistor is connected to the capacitor in the switching unit. It is a circuit diagram which shows the schematic structure of the flash type ADC which concerns on other embodiment of this disclosure. It is a flow chart which showed the operation example of the above-mentioned ADC. It is a circuit diagram which shows one structural example of the comparator in the above-mentioned ADC. It is a figure of the graph which shows the distribution of the offset voltage of the said comparator. It is a figure of the graph which shows the relationship between the output code and DNL in one Example of ADC. It is a figure of the graph which shows the relationship between a population parameter and DLN in the said Example. It is a circuit diagram which shows the schematic structure of the comparator in the said Example. It is a figure of the graph which shows the relationship between the threshold voltage of the transistor in the said comparator and the offset voltage of the said comparator. It is a figure of the graph which shows the distribution of the offset voltage of the comparator in one Example of the ADC by a vertical bar.

[Embodiment 1]
Hereinafter, one embodiment of the present disclosure will be described in detail.

(Temperature sensor configuration)
FIG. 1 is a circuit diagram showing a schematic configuration of a temperature sensor 1 (analog device) according to an embodiment of the present disclosure.

The temperature sensor 1 is provided on a single IC chip, and is inverted with a control device 2, a switching unit 3, an analog transistor group Tr, a bias generation circuit 4, a capacitor 5, and a charging transistor 6. It includes an amplifier 7, a TDC (Time-to-Digital Converter) 8, and a calculation unit 9. The IC chip is preferably a CMOS IC chip from the viewpoints of miniaturization, high-speed operation, low power consumption, and the like.

The control device 2 controls the operation of the temperature sensor 1. Specifically, the control device 2 is input with the clock signal Clock and the result of the TDC 8. The control device 2 is configured to control the opening and closing of the switching element included in the switching unit 3 and to control the gate potential of the charging transistor 6.

The switching unit 3 is configured to selectively connect one electrode of the capacitor 5 to any source terminal of any of the N transistors Mn. N is a natural number of 2 or more.

FIG. 2 is a circuit diagram showing a configuration example of the switching unit 3. As shown in FIG. 2, the switching unit 3 includes N switching elements S (first switching element S ₁ to Nth switching element _SN ). Each switching element S is a fine MOSFET (Metal-Oxide Semiconductor Field-Effect Transistor) that operates digitally.

The analog transistor group Tr includes N transistors Mn (first transistor Mn ₁ to Nth transistor Mn _N ) (analog element), and each transistor Mn is a fine n-type MOSFET. The k transistor Mn k _{(integer k} is 1 ~ N) is grounded source terminal, connected to the capacitor 5 and the drain terminal via the first k switching elements S _k of switching unit 3, gate terminal bias generating circuit It is connected to 4. Each transistor Mn operates in an analog manner, that is, _{a bias voltage V b} equal to or less than the _{threshold voltage V th} is applied and used. Since the N transistors Mn are fine, their characteristics are not negligible at the time of manufacture. This will be described later.

_{The bias generation circuit 4 generates a bias voltage V b} applied between the gate and the source of the N transistors Mn. The bias voltage V _b is smaller than the threshold voltages V _th1 to V _thN of any of the first transistors Mn ₁ to N transistors Mn _N.

In the capacitor 5, one electrode is connected to the switching unit 3, the drain terminal of the charging transistor 6, and the input terminal of the inverting amplifier 7, and the other electrode is grounded.

The charging transistor 6 is a minute MOSFET that operates digitally. In the charging transistor 6, the source terminal is _{connected to the power supply voltage Vdd} on the high potential side, the drain terminal is connected to the capacitor 5, and the gate terminal is connected to the control device 2.

In the inverting amplifier 7, the input terminal is connected to the capacitor 5 and the output terminal is connected to the TDC 8.

The clock signal Clock and the result of the inverting amplifier 7 are input to the TDC 8. The TDC 8 measures the discharge time required for the output voltage V _out of the capacitor 5 to decrease to a given threshold voltage V _c. The TDC 8 outputs the discharge time as a digital value to the control device 2 and the arithmetic unit 9.

The clock signal Clock and the discharge time from the TDC 8 are input to the arithmetic unit 9. The arithmetic unit 9 includes two volatile recording media (registers) 10a and 10b and a logic circuit 11. The two volatile recording media 10a and 10b each temporarily store the two discharge times from the TDC 8. The logic circuit 11 calculates the discharge time ratio between the discharge time stored in the volatile recording medium 10a and the discharge time stored in the volatile recording medium 10b, and outputs a digital signal corresponding to the discharge time ratio. Output as temperature information indicating the temperature. Then, when the control device (not shown) receives the digital signal, it calculates the temperature from the discharge time ratio based on the calibration data and outputs it. Here, the control device (not shown) may be a control device in the same IC chip or a control device of another chip. The details of the temperature calculation method (digital signal output method) will be described later.

(Operation of temperature sensor)
FIG. 3 is a flow chart showing an operation example of the temperature sensor 1 shown in FIG.

When the temperature sensor 1 starts temperature sensing (START), the control device 2 starts operation from the initial setting k = 1 (step S1). First, the control device 2 executes a subroutine (step S2) for measuring the k-th discharge time d _{k when the capacitor 5 is discharged through the k-th transistor Mn k.} This subroutine will be described later. Subsequently, the control device 2 writes the k-th discharge time on the volatile recording medium in the control device 2 (step S3), and determines whether k = N is satisfied (step S4). If No in step S4, k is incremented by 1 (step S5), and the process returns to step S2.

In the case of Yes in step S4, the control device 2 finishes the measurement of _{the discharge time and reads out the measured first discharge time d 1} to Nth discharge time d _N (step S6). _{Then, the control device 2 sorts the first transistors Mn 1} to N transistors Mn _N so that the discharge times are arranged in ascending (or descending) order (step S7). That is, the control device 2 orders _{the first transistor Mn 1} to the Nth transistor Mn _N according to the ascending order (or descending order) of the discharge time.

After sorting as described above, the control device 2 _{selects the first reference transistor Tr 1} and the second reference transistor Tr ₂ as follows.

The control device 2 reads out the order of the first reference transistor Tr _{1 (step S8).} Then, among the first transistors Mn ₁ to N transistors Mn _N , the i-th transistor Mn _i located in this order is selected as the first reference transistor Tr ₁ (step S9), and the selection result is volatilized in the control device 2. Write to the sex recording medium (step S10). Similarly, the control device 2 reads out the order of _{the second reference transistor Tr 2 (step S11).} Then, among the first transistors Mn ₁ to N transistors Mn _N , the j transistor Mn _j located in this order is selected as the second reference transistor Tr ₂ (step S12), and the selection result is volatilized in the control device 2. Write to the sex recording medium (step S13). The control device 2 may execute steps S8 to S10 and steps S11 to S13 in parallel or in reverse order. The order of reading in steps 8 and 11 will be described later.

After selecting as described above, the control device 2 _{measures the first reference discharge time dref1} and the second reference discharge time _dref2 as follows.

The control device 2 reads out the selection result for the first reference transistor Tr ₁ (step S14), sets the setting k = i for measuring the _i- th discharge time di (step S15), and the capacitor 5 passes through _{the k-th transistor Mn k.} A subroutine for measuring the k-th discharge time d _k in the case of discharging is executed (step S16). Subsequently, the control device 2 writes the i-th discharge time di as _{the first reference discharge time d ref1 on} the first volatile recording medium 10a in the arithmetic unit 9 (step S17). Similarly, control device 2 reads the selection result for the second reference transistor Tr ₂ (step S18), and the set k = j to measure the j discharge time _{d j} (step S19), through the first k transistor Mn _k A subroutine for measuring the k-th discharge time d _k when the capacitor 5 is discharged is executed (step S20). Subsequently, the control device 2 writes the j-th discharge time dj as _{the second reference discharge time dref2 on} the second volatile recording medium 10b in the arithmetic unit 9 (step S21).

After that, the arithmetic unit 9 _{reads out the first reference discharge time dref1} and the second reference discharge time _dref2 (step S22). Then, the arithmetic unit 9 calculates the discharge time ratio d _ref1 / d _{ref2 between the first reference discharge time d ref1} and the second reference discharge time d _ref2 using the logic circuit 11 (step S23), and generates a digital signal. And output (step S24). The arithmetic unit 9, after calculating the discharge time ratio _d ref1 _{/ d ref2,} reads calibration data, be output to calculate the absolute temperature on the basis of the discharge time ratio _d ref1 _{/ d ref2} and calibration data Good. Then, it is determined whether to end (step S25), if Yes, the temperature sensing is ended (END), and if No, the process returns to step 14.

The information stored in the volatile recording medium is erased when the temperature sensing is completed. Therefore, the temperature sensor 1 repeats the operation from step S1 every time the temperature sensing is started.

(Subroutine to measure discharge time)
FIG. 4 is a flow chart showing an example of a subroutine (steps S2, 16, 20) for measuring the k-th discharge time d _k when the capacitor 5 is discharged through the k-th transistor Mn _{k shown in FIG.}

When the subroutine is started (START), charging is first started (step S31). In step S31, the control device 2 instructs the switching unit 3 to open all the switching elements and disconnect the analog transistor group Tr from the capacitor 5. After disconnection, the control device 2 applies the gate voltage of the charging transistor 6 so that the charging transistor 6 is energized. Then, with respect to _{the potential difference V out} at both ends of the capacitor 5, _{it is determined whether V out} = V _dd (step S32). If No in step S32, charging is continued, and if Yes, charging is terminated (step S33). In step S33, the control device 2 applies the gate voltage of the charging transistor 6 so that the charging transistor 6 is in a non-energized state.

After the charging is completed, the discharge is started (step S34), and at the same time, the measurement of the discharge time is also started (step S35). In step S34, the control device 2 _{commands the switching unit 3 so that only the kth transistor Mn k} is connected to the capacitor 5 and the other transistors remain disconnected from the capacitor 5. Switching unit 3 shown in FIG. 2, only the first k switching elements S _k in the closed state, the other switching element remains open. In step S35, the TDC 8 measures the elapsed time from the time when V _out = V _{dd during V out} <V _dd , digitally converts this elapsed time, and continues to output.

During discharging, the control device 2 _{determines whether V out} <V _c (step S36). V _c is a given threshold of the potential difference of the capacitor 5. If No in step S36, the discharge is continued. In the case of Yes, it is determined that the capacitor 5 is sufficiently discharged, and the discharge is terminated (step S37). At the same time, the measurement of the discharge time is completed (step S38). In step S37, the control device 2 instructs the switching unit 3 so that the switching unit 3 opens all the switching elements. In step S38, the elapsed time that is output at this time from TDC8 is acquired as the k discharge time _{d k.}

(Conventional temperature sensor)
Some conventional on-chip temperature sensors utilize various measurement principles.

As an example, there is a bandgap type temperature sensor using a bipolar transistor having the same characteristics (Non-Patent Documents 3 and 4). As another example, there is a temperature sensor that utilizes the subthreshold characteristics of two MOSFETs having the same characteristics (Non-Patent Documents 5 and 6). However, none of these methods has realized an on-chip type temperature sensor with low power consumption and an output value linearly related to temperature (PTAT, proportional-to-absolute-temperature).

In addition, both methods require two transistors having the same characteristics. When the transistor is manufactured, the characteristic variation of the transistor occurs, and the smaller the transistor size, the larger the characteristic variation. After manufacturing a transistor, it is difficult to accurately measure the characteristics of the transistor. Therefore, in the prior art, the transistor is manufactured in a size larger than the minimum size that can be manufactured, thereby reducing the variation in the characteristics of the transistor.

(Measurement principle of temperature sensor according to the present disclosure)
Hereinafter, the measurement principle of the temperature sensor 1 according to the present disclosure will be described in detail.

FIG. 5 is a circuit diagram for explaining the measurement principle. FIG. 6 is a graph showing an example of the voltage-current characteristics of the first and _{second transistors M n1} and M _n2 in the circuit shown in FIG. 5, and more specifically, when the drain-source voltage is constant. , Is a diagram showing an example of the relationship between the gate-source voltage and the drain current.

Two of the circuit shown in FIG. 5 are identical except the first transistor _{M n1} the second transistor _{M n2. The voltage V DS1} applied by the capacitor 5 between the drain and the source of the first transistor M _n1 is the same as _{the voltage V DS2} applied by the capacitor 5 between the drain and the source of the second transistor M _n2. Two such circuits are switching unit 3 is achievable by first only the switching element S _1, or when only the second switching element S ₂ to the closed state.

In the example shown in FIG. 6, the threshold voltage V _{th1 of the first transistor M n1} is larger than the threshold voltage V _th2 of the second transistor M _n2. A small bias voltage _{V b} than the threshold voltage _{V th1, V th2} is applied between the gate and the source of the first transistor _{M n1,} and applies the same bias voltage _{V b} between the gate and source of the second transistor _{M n2.} At this time, the first transistor _{M n1} flows a drain current _{I 1,} the drain current _{I 2} flows through the second transistor _{M n2.} These drain currents I ₁ and I ₂ are subthreshold leakage currents and show different values as shown in FIG. Approximately, it is expressed by the following equations (1) and (2).

Here, T is absolute temperature, K is a coefficient depending on the manufacturing process, n is a subthreshold coefficient, k is Boltzmann's constant, q is an elementary charge, and λ ₁ , λ ₂ , α ₁ , α ₂ are positive coefficients. V _DS1 indicates the drain-source voltage of the first transistor M _{n1 , and V DS2} indicates the drain-source voltage of the second transistor M _n2 . Since V _DS1 ≈ V _DS2 and _{the variation of λ 1} , λ ₂ , α ₁ , α ₂ can be ignored, it _{is approximated as α 1} T−α ₂ T ≈ 0, λ ₁ V _DS1 −λ ₂ V _DS2 = ≈ 0. Will be done. Therefore, T is approximated by the following equation (3).

From equation (3), the absolute temperature T can be calculated by a method that does not depend on the _{bias voltage V b.} The threshold voltages V _th1 and V _th2 (first characteristic) are constants because they are characteristic values of _{the first transistor M n1} and the second transistor M _n2. Therefore, the absolute temperature T has a linear relationship with the natural logarithm _{of the drain current ratio I 2} / I _1. Here, if ΔV _th = V _th1 −V _th2 is appropriately set, the absolute temperature T is approximated to a linear relationship _{with the drain current ratio I 2} / I ₁ by linearly approximating the natural logarithm within an arbitrary temperature range. can do. This linear relationship enables temperature sensing in which the output value is linearly related to the temperature without depending on the _{bias voltage V b.}

In two of the circuit shown in FIG. 2, the capacitor 5 are charged with the same supply voltage V _dd, the same bias voltage V _b is applied to the first transistor M _n1 and the second transistor M _n2. In this case, the following equation (4) approximately holds.

Here, d _{1 is the time required for the output voltage V out} of the capacitor 5 to decrease to a given threshold voltage V _{c in} the circuit including the first transistor M _n 1 (the circuit on the left side of FIG. 2). _{Reference numeral 2} denotes a discharge time required for _{the output voltage V out} of the capacitor 5 to decrease to the same given threshold voltage V _{c in} the circuit including the second transistor M n2 (the circuit on the right side of FIG. 2).

Therefore, since the drain current ratio I ₂ / I ₁ can be approximated to the absolute temperature linearly, the discharge time ratio d ₁ / d ₂ can also be approximated to the absolute temperature linearly. Therefore, temperature sensing by measuring the discharge time ratio d ₁ / d _{2 becomes possible.}

(Transistor selection method)
As described above, the characteristics of the N transistors Tr have a non-negligible variation. It has been reported that when a large number of MOSFETs are manufactured on one chip, the threshold voltage of the MOSFETs follows a normal distribution (statistical distribution) represented by the following equation (5) (Non-Patent Document 7). The standard deviation σ of this distribution can be obtained by the following equation (6) according to Pelgrom's Law (Non-Patent Document 8).

Here, _AVth is a parameter depending on the manufacturing process, W is a design value of the gate width of the transistor, and L is a design value of the gate length of the transistor. Therefore, the standard deviation σ in the equation (5) is a constant value determined by the manufacturing process and the design of the transistor size.

Accordingly, as ΔV _th = _V th1 _{-V th2} is properly obtained, it is difficult to set the threshold voltage _{V th1} of the first transistor _{M n1} and threshold voltage _{V th2} of the second transistor _{M n2.} However, the first reference transistor Tr ₁ and the second reference transistor Tr ₂ are selected _{from the first transistors Mn 1} to N transistors Mn _{N so that ΔV th} = V _{th, ref1-} V _{th, ref 2} can be appropriately obtained. It is possible to do. Here, V _{th and ref 1} are the threshold voltages of the first reference transistor Tr _{1, and V th and ref 2} are the threshold voltages of the second reference transistor Tr 2.

FIG. 7 is a diagram showing variations _{in the threshold voltage Vth} in the analog transistor group Tr.

_{As shown in FIG. 7, the threshold voltage Vth} of the sorted N transistors Mn follows a normal distribution as described above. Therefore, according to statistical estimation, the first reference transistor Tr ₁ exists in the order of the ratio obtained by the following equation (7) from the beginning. Similarly, the second reference transistor Tr ₂ exists in the order of the ratio obtained by the following equation (8) from the beginning.

_{The order of the first reference transistor Tr 1} read out in step 8 described above is the order obtained by the equation (7), and the order of the second reference transistor Tr ₂ read out in step S11 is obtained by the equation (8). It is a ranking.

The above statistical inference is more accurate as it is closer to the center of the normal distribution. Therefore, it is preferable that the reference threshold voltages _{Vth, ref1} , _{Vth, and ref2} are selected so that their arithmetic mean is close to the center of the normal distribution. The above statistical inference is more accurate as the population parameter increases. Therefore, it is preferable that N is large. Since the N transistors Mn are fine, unlike the transistors that operate in an analog manner with the sensor chip of the prior art, the temperature sensor 1 can be miniaturized even if N is large. In addition, such statistical inference can be made with statistical distributions other than the normal distribution, such as beta distribution and gamma distribution.

(Transistor sorting method)
In the above subroutine, the current I _{i flowing through the i-th transistor M ni} is approximately represented by the following equation (9) according to the subthreshold characteristics of the MOSFET when V _{c = 0 V.}

Here, lambda _i, alpha _i is a positive _{coefficient, V thi} is the threshold _{voltage, V DSi} of the i transistors _{M ni} drain of the i transistors _{M ni} - shows the source voltage.

Therefore, the _{larger the threshold voltage V thi} , the smaller the current I _i .

From the N transistors Mn, the relationship represented by the following equation (10) is approximately established when _{the i-th transistor Mn i} and the j-th transistor Mn _{j are compared.}

In the case of V _c> 0V, the relationship of the discharge time ratio _{d i / d j ≒ I j} / I i is established. Therefore, as the discharge current _{I i} is small, the discharge time _{d i} is long. Therefore, in step S7 described above, by sorting the N transistors Mn so that the discharge time (second characteristic) is arranged in ascending order, the N transistors Mn are sorted so that the threshold voltage is arranged in ascending order.

The upper figure of FIG. 7 shows the _{threshold voltage Vth with respect to the discharge time d. This also indicates} that the larger the threshold voltage V thk, the longer the _{discharge time d k.}

(Action effect)
As described above, the temperature sensor 1 according to the present disclosure is sorted (ordered) so that the N transistors Mn included in the analog transistor group Tr are arranged in ascending or descending order of the discharge time d. Then, based on the order of the normal distribution and the transistor Mn of variations in the threshold voltage V _th, it is associated with the threshold voltage V _th and the transistor Mn. _{Therefore, the relative value of the threshold voltage Vth} with respect to the other transistors Mn of each transistor Mn can be estimated on-chip.

The temperature sensor 1 according to the present disclosure includes the first reference transistor Tr _{1 so that ΔV th} = V _{th, ref1} −V _{th, ref2} can be appropriately obtained from the N transistors Mn included in the analog transistor group Tr. The second reference transistor Tr ₂ is selected. As a result, the temperature sensor 1 can be operated appropriately. _{Therefore, since the temperature information can be detected without measuring the threshold voltage Vth} of the transistor Mn, it is not necessary to increase the area of the temperature sensor 1, and it is possible to suppress an increase in power consumption and manufacturing cost. In addition, a high-performance measuring device for measuring the threshold voltage Vth becomes unnecessary.

The temperature sensor 1 according to the present disclosure does not require a plurality of analog transistors having the same characteristics, and it is allowed that the characteristics of the analog transistors vary. Therefore, in the temperature sensor 1 according to the present disclosure, since the analog transistor can be miniaturized, the temperature sensor 1 can operate with current saving, and power saving and miniaturization are possible.

The temperature sensor 1 according to the present disclosure does not require a reference voltage or a reference current. Therefore, the temperature sensor 1 according to the present disclosure can be reduced in power consumption and size.

The temperature sensor 1 according to the present disclosure does not require a non-volatile recording medium. Therefore, the temperature sensor 1 according to the present disclosure can be reduced in power consumption and size.

The temperature sensor 1 according to the present disclosure sorts the transistors Mn and selects the _{reference transistors Tr 1} and Tr _{2 for each temperature sensing.} Even if a small number of transistors Mn out of N deteriorate, the distribution followed by the N transistors Mn does not substantially change. Therefore, even if a small number of transistors Mn deteriorate, the temperature sensor 1 according to the present disclosure is suppressed from deteriorating the accuracy of temperature sensing, and can continue to maintain the function as the temperature sensor 1. ..

[Embodiment 2]
Other embodiments of the present invention will be described below. For convenience of explanation, the same reference numerals will be added to the members having the same functions as the members described in the above embodiment, and the description will not be repeated.

FIG. 12 is a circuit diagram showing a configuration example of the switching unit 3 according to the present embodiment.

As shown in FIG. 12, the switching unit 3 is of a tree type. FIG. 12 shows an example composed of a binary tree, but may include a non-binary tree such as a ternary tree, a quadtree, or a quintuplet. When composed of a binary tree as shown in FIG. 12, the parasitic capacitance connected in parallel to the capacitor 5 _{is proportional to log 2} (N). Therefore, the parasitic capacitance can be reduced and the discharge time can be shortened as compared with the configuration example (parasitic capacitance N) shown in FIG. 2 in which N switching elements S are connected in parallel in one stage.

FIG. 13 shows an equivalent circuit of the switching unit 3 shown in FIG. 12 when the first transistor Mn ₁ is connected to the capacitor 5.

(Appropriate threshold voltage difference)
As described above, the absolute temperature T is approximately expressed by the following equation (11).

Since this is an approximation, it is preferable to determine the _{threshold voltage difference ΔV th} (first characteristic) so that the approximation error is small.

As an example, in the circuit shown in FIG. 1 on the simulation, the switching unit 3 is configured as shown in FIG. 12, and ΔV _th is changed from -80 mV to -60 mV in 2 mV units, and the number is in the range of 0 to 100 ° C. It was determined 1 reference discharge time _{d 1} of the transistor Tr ₁ and the discharge time ratio _d 1 / _{d 2} between the discharge time _{d 2} of the second reference transistor Tr _2. FIG. 8 shows the result of this simulation.

The coefficient of determination adjusted for degrees of freedom (Adjust-R ² ) was calculated from the simulation results shown in FIG. The adjusted coefficient of determination is a value for evaluating linearity. The closer the coefficient of determination adjusted for degrees of freedom is to 1, the higher the linearity of the relationship between the _{discharge time ratio d 1} / d _{2 and the temperature T.} FIG. 9 shows the coefficient of determination adjusted for this degree of freedom.

As shown in FIG. 9, _{when ΔV th} = −64 mV, the linearity is closest to 1. Therefore, ΔV _th = −64 mV is the optimum threshold voltage difference.

(Evaluation of error)
In the above simulation example, the _{measurement error when ΔV th} = −64 mV is set is evaluated.

The analog transistor group Tr shown in FIG. 1 was randomly generated 10 times with N = 1024. Then, steps S1 to S13 were executed to obtain 10 sets of reference threshold voltage sets (V _{th, ref1} , V _{th, ref 2} ). At this point, it should be noted that an error of _{V th, ref1-} V _{th, ref2 ≠ -64 mV occurs in each set.}

Using this combination of 10 sets of reference threshold voltages, the discharge time ratio d ₁ / d ₂ was measured in the range of 0 to 100 ° C. FIG. 10 shows the measurement result.

The temperature was calculated by calibrating the measurement results shown in FIG. 10 at two points of 20 ° C and 80 ° C. FIG. 11 shows the error of the calculated temperature.

As shown in FIG. 11, the error is within ± 1.2 ° C even in the worst case.

In order to reduce this error, N may be increased. The magnitude of N required for the margin of error is appropriately determined for those skilled in the art based on statistical inference.

[Embodiment 3]
Other embodiments of the present invention will be described below. For convenience of explanation, the same reference numerals will be added to the members having the same functions as the members described in the above embodiment, and the description will not be repeated.

FIG. 14 is a circuit diagram showing a schematic configuration of a flash type ADC 20 (analog device, AD converter) according to this embodiment.

As shown in FIG. 14, the ADC 20 includes a sample hold circuit 21, a comparator group 22, a switch matrix 23, an encoder 24, a voltage measuring circuit 25, a control device 26, and a switching element group 27.

Sample-and-hold circuit 21 holds the input voltage _{V in.} Input voltage V _in that is held is applied to the comparator group 22.

The comparator group 22 includes M comparators Cp (first comparator Cp ₁ to M first comparator Cp _M ), and each comparator Cp contains a plurality of fine MOSFETs. In each comparator Cp, one of the two input terminals is connected to the sample hold circuit 21 and the other is grounded. In each comparator Cp, the output terminal is connected to the switch matrix 23 and is connected to the voltage measuring circuit 25 via the switching element group 27. Further, in each comparator Cp, the circuit configuration is switched based on the configuration signal from the control device 26. The details of the comparator Cp will be described later.

The switch matrix 23 selects N-1 (N is a natural number smaller than M) from the M input signals from the comparator group 22 based on the 26 switch signals from the control device, and rearranges the encoder 24. Output to.

The encoder 24 encodes and outputs N input signals from the switch matrix 23. Specifically, the encoder 24 detects the boundary between 0 and 1 for N-1 input signals, and encodes them based on the detection result.

The voltage measuring circuit 25 measures the output voltage of each comparator Cp. The voltage measuring circuit 25 notifies the control device 26 of the measurement result.

The control device 26 controls the operation of the ADC 20. Specifically, in the control device 26, the output voltage of each comparator Cp is input from the voltage measuring circuit 25. The control device 26 is configured to control the circuit configuration in each comparator Cp, the switch matrix 23, and the switching element group 27.

(Operation of ADC)
FIG. 15 is a flow chart showing an operation example of the ADC 20 shown in FIG.

When the power is turned on, the control device 26 starts operation from the initial setting i = 0 (step S41). The control device 26 first selects the i-th comparator (comparator) (step S42), and measures and records the voltage corresponding to the offset voltage as follows (step S43). Therefore, the control device 26 controls the switching element group 27 in the closed state.

FIG. 16 is a circuit diagram showing a configuration example of the comparator Cp. The comparator Cp in the present embodiment, as compared to a comparator used in the conventional flash-type ADC, except that the switching elements S _{1 ~} S ₃ are newly provided, other configurations are the same.

Switching elements _S 1 ~ _{S 3} are controlled by a control device 26. Switching element _{S 1} is provided between the gate terminal and the power supply voltage _{V dd} of FET32 input voltage _{V in} is inputted. The switching element S ₂ is provided between the gate terminal of the FET 33 to which the reference voltage V _{ref is input and the power supply voltage V dd.} The switching element S ₃ is provided between the output terminals V _out ⁺ and V _out ^−. The output terminals V _out ⁺ and V _out ⁻ are connected to the voltage measuring circuit 25.

The comparator Cp in the above-described configuration, the switching element _{S 1} to the open state, when the switching element _S 2 · _{S 3} is closed, current flows through the FET 33 · 35. At this time, the voltage measured by the voltage measuring circuit 25 (hereinafter referred to as the first measured voltage) becomes a function of the above current and exhibits the characteristics of the FETs 33 and 35.

Then, the switching element _{S 2} to the open state, when the switching element _S 1 · _{S 3} is closed, current flows through the FET 32 · 34. At this time, the voltage measured by the voltage measuring circuit 25 (hereinafter referred to as the second measured voltage) becomes a function of the above current and exhibits the characteristics of the FETs 32 and 34. Therefore, the difference between the first measurement voltage and the second measurement voltage becomes the voltage corresponding to the offset voltage of the comparator Cp. At the time of operation of the AD converter, the switching elements _S 1 ~ _{S 3} has opened is maintained.

With reference to FIG. 15, the control device 26 increments i by 1 (step S44) and determines whether i <M is satisfied (step S45). If Yes in step S45, the process returns to step S42.

If No in step S45, the control device 26 controls the switching element group 27 in the open state, while the first comparators Cp ₁ to M comparators so that the recorded voltages are arranged in ascending (or descending) order. Sort Cp _M (step S46). That is, the control device 2 orders _{the first comparator Cp 1} to the M first comparator Cp _M according to the ascending order (or descending order) of the voltage.

Next, the control device 26 selects N-1 comparators Cp from M comparators Cp as follows (step S47).

FIG. 17 is a graph showing the distribution of the offset voltage of the comparator Cp. Since the comparator Cp consists of a plurality of transistors, its offset voltage follows a normal distribution as shown in FIG. Therefore, the sorted first comparator Cp ₁ to M first comparator Cp _M can be associated with the value of the offset voltage according to the normal distribution. As a result, the control device 26 can select N-1 comparators Cp corresponding to N-1 _{offset voltages V offset1} to _{VoffsetN-1 having a predetermined voltage interval.} Note that N depends on the number of bits n of the output signal of the encoder 24, and N = 2 ⁿ .

Next, the control device 26 determines the configuration of the selected comparator Cp and the non-selected comparator Cp, generates a configuration signal indicating the determined configuration, and transmits it to the comparator group 22 (step S48). In this case, the power consumption can be reduced by stopping the operation of the non-selective comparator Cp.

Next, the control device 26 generates a switch signal and transmits it to the switch matrix 23 so that the output signals of the selected comparator Cp _{are arranged in the order of the offset voltages V offset1} to _{VoffsetN-1 (step S49).} Thus, since the preparation for AD converting an input voltage V _in of the analog to digital n-bit signal is completed, the operation of the AD conversion starts.

(Action effect)
As described above, in the ADC 20 according to the present embodiment, as in Non-Patent Documents 1 and 2, the reference voltage is not supplied to the comparator Cp by utilizing the fact that the offset voltage follows a normal distribution, and instead, the offset voltage is offset. Use voltage. Therefore, it is not necessary to increase the area of the comparator, and it is possible to suppress an increase in power consumption and manufacturing cost.

Further, in the ADC 20 according to the present embodiment, the first measurement voltage (output voltage) when the operation of a part of the plurality of FETs included in the comparator Cp is stopped and the operation of the other part of the plurality of FETs are performed. The comparator Cp is ordered according to the difference from the second measured voltage when stopped. Then, the value of the offset voltage and the comparator Cp are associated with each other based on the normal distribution of the offset voltage and the order of the comparator Cp. Therefore, the offset voltage of each comparator Cp can be estimated. As a result, a high-performance measuring device for measuring the offset voltage becomes unnecessary.

As a result, the output signals of the N-1 comparators Cp are rearranged in the order of the offset voltage by the switch matrix 23 using the N-1 comparators Cp from the M comparators Cp, and the encoder 24 is used. Can output an n-bit digital signal appropriately. Therefore, the ADC 20 according to the present embodiment adds the switch matrix 23 as compared with the ADCs of Non-Patent Documents 1 and 2, but does not need to use a wallace tree decoder that uses a large number of adders. Since the switch matrix 23 can be composed of a plurality of switching elements, the switch matrix 23 and the encoder 24 of the present embodiment can reduce the circuit scale as compared with the Wallace tree decoders of Non-Patent Documents 1 and 2. it can.

[Example 1]
The input / output characteristics and DNL (Differential Non-Linearity) of the ADC 20 according to this embodiment were evaluated by simulation. The simulation was performed under the following conditions.
-The comparator Cp has an offset voltage.
The offset voltage of the comparator Cp follows a normal distribution with an expected value of μ = 0 mV and a standard deviation of σ = 90 mV.
• The input voltage _{V in} is, in the range of -90mV ≦ _{V in} ≦ 90mV.
-The output is 6 bits.

The DNL is used as an index used for evaluating the performance of the ADC. Using the input voltage Vi when the output code is i and the input width V _LSB-ideal = V _ref / 2 ^N when the ADC is ideal, the DNL is expressed by the following equation (12).

DNL [i] = {(V _{i + 1-} V _i ) / (V _LSB-ideal )} -1 (0 <i <2 ^N -1) (12).

That is, DNL indicates the difference between the ideal value and the measured value of the step width of a certain output code, the unit is LSB (Least Significant Bit), and the minimum voltage value V _{LSB-ideal that can detect the actual voltage value.} Is standardized by.

(Input / output characteristics)
In the simulation, to generate M = 5000 or comparators as ^population elected 2 6 -1 = 63 comparators Cp (N = 64, n = 6). Using the selected comparator Cp with the ADC 20 shown in FIG. 14, the DNL in the output codes of 0 to 63 was calculated. The result is shown in FIG.

FIG. 18 is a graph showing the relationship between the output code and DNL. Referring to FIG. 18, in this embodiment, −0.3 <DNL <+0.3 is satisfied. Therefore, it can be understood that the ADC 20 functions well.

(Parameter of comparator)
In addition, DNL was executed 300 times for each parameter (1000, 2000, 3000, 4000, 5000, 7000, 10000), and the relationship between the parameter of the comparator Cp and DNL was investigated. The result is shown in FIG.

FIG. 19 is a graph showing the relationship between the population parameter and DLN. In FIG. 19, the maximum value and the minimum value of DNL are evaluated by ± 3σ. When the absolute value of DNL is 1 or more, a missing code appears, so that it is required to satisfy -1 <DNL <+1. With reference to FIG. 19, it can be understood that if the population parameter is 3000 or more, -1 <DNL <1 is satisfied and the missing code does not appear.

(Offset voltage of comparator)
FIG. 20 is a circuit diagram showing a schematic configuration of the comparator Cp in this embodiment. For comparator Cp as shown in FIG. 20, by changing the threshold voltage _{[Delta] V Thp3} transistor MP3, and analyze changes in the offset voltage _{V offset} in HSPICE. The analysis result is shown in FIG. The analysis conditions were set as follows.
・ V _ref = 0
Of · _{V in} amplitude: 1mV
・ CLK frequency: 1GHz
-Transistor (MOSFET) size: L = 65 nm, W = 140 nm
_-Threshold voltage range: ΔV thp3 = ± 40 mV.

Figure 21 is a diagram of a graph showing the relationship between the threshold voltage _{[Delta] V Thp3} and the offset voltage _{V offset.} Referring to FIG. 21, the threshold voltage _{[Delta] V Thp3} and the offset voltage _{V offset,} it can be understood that in a substantially linear relationship. Therefore, if the variation of the threshold voltage of the transistor MP3 follows a normal distribution, it is considered that the offset voltage also follows a normal distribution. Further, if the variation of the threshold voltage of other transistors follows a normal distribution, it is expected that the offset voltage also follows a normal distribution.

(Required number of comparators)
Referring to FIG. 17, the first offset voltage _{V offset1} and the N-1 offset voltage _{V offsetN-1} it will be understood that the probability density is minimal. The position of the error of the N-1 offset voltage _VoffsetN-1 and the probability that a certain comparator Cp falls within the allowable range (2σ ± 0.1σ) are expressed by the following equation (13).

Further, the condition of the required number N for including at least one comparator Cp within the allowable range with a probability of 95% is N ≧ 4 / P. _{The same applies to} the case of the first offset voltage V offset1.

The probability shown in the above equation (13) depends on the standard deviation σ and depends on the position of the error and the allowable range. From this, the required number N of analog elements may differ greatly depending on the target analog device.

[Example 2]
FIG. 22 is a graph showing the distribution of the offset voltage of the comparator Cp in the ADC of this embodiment by vertical bars.

The input / output characteristics, DNL and INL (Integral Non-Linearity) of the ADC 20 according to this embodiment were evaluated by simulation. The simulation was performed under the following conditions.
-The comparator Cp has an offset voltage.
-The offset voltage of the comparator Cp follows the distribution function obtained by Monte Carlo analysis, as described later.
• The input voltage _{V in} is, in the range of -90mV ≦ _{V in} ≦ 90mV.
-The output is 6 bits.

Regarding the offset voltage of the comparator Cp, it was assumed that the offset voltage of the comparator Cp follows the distribution function obtained as follows. 5000 comparators Cp having the same configuration were prepared by a 60 nm process, and the offset voltage of each comparator Cp was measured. Then, the distribution function of the offset voltage of the comparator Cp was obtained by Monte Carlo analysis. Therefore, in the simulation, the offset voltage of the comparator Cp was randomly selected from the distribution function obtained by Monte Carlo analysis.

The INL is used as another index used for the performance evaluation of the ADC. The input voltage _{V i} when the output code is i, using input width _{V LSB-ideal = V ref /} 2 N when the ideal the ADC, INL is represented by the following formula (14).

INL [i] = {(V _{i + 1-} V ₀ ) / (V _LSB-ideal )}-i (0 <i <2 ^N ) (14).

That is, INL indicates the difference between the ideal input threshold value and the actually measured input threshold value of a certain output code, the unit is represented by LSB, and the actual voltage value is standardized by the _{minimum voltage value V LSB-ideal that can be detected.}

When following a normal distribution with expected value μ = 0 mV and standard deviation σ = 90 mV, the input / output characteristics of ADC20 are theoretically -0.47 <DNL <+0.53 and -1.23 <INL <+1.24. Fulfill.

First, assuming that the distribution of the offset voltage of the comparator Cp according to the second embodiment shown in FIG. 22 follows a normal distribution, the offset voltage was used as a reference for AD conversion. As a result of this AD conversion, the input / output characteristics of the ADC 20 satisfied −0.49 <DNL <+0.80 and -1.85 <INL <+0.44. This result was worse than the theoretical prediction. Therefore, it is estimated that the offset voltage of the comparator Cp according to the second embodiment follows a distorted distribution from the above normal distribution. For example, the offset voltage may deviate from the normal distribution due to the non-linearity of the transistor characteristics.

Next, a beta distribution that fits the distribution shown in FIG. 22 was obtained. The beta distribution can represent an asymmetric statistical distribution. FIG. 22 shows the obtained fitted beta distribution as a curve.

Then, assuming that the offset voltage of the comparator Cp according to the second embodiment follows the above beta distribution, the offset voltage was used as a reference for AD conversion. As a result of this AD conversion, the input / output characteristics of the ADC 20 satisfied -0.62 <DNL <+0.61 and -0.44 <INL <+1.41. This result was better than the result when the normal distribution was used. Therefore, the input / output characteristics of the ADC 20 could be improved by using the beta distribution rather than by using the normal distribution.

Therefore, it can be understood that the control device 26 can bring out the best performance of the ADC 20 by selecting and using the optimum statistical distribution from various statistical distributions.

(Additional notes)
In the above embodiment, the voltage measuring circuit 25 and the control device 26 are provided inside the ADC 20, but may be provided outside the ADC 20.

[Example of realization by software]
The control blocks (particularly control devices 2.26) of the temperature sensor 1 and the ADC 20 may be realized by a logic circuit (hardware) formed in an integrated circuit (IC chip) or the like, or may be realized by software. ..

In the latter case, the temperature sensor 1 includes a computer that executes a program instruction, which is software that realizes each function. The computer includes, for example, one or more processors and a computer-readable recording medium that stores the program. Then, in the computer, the processor reads the program from the recording medium and executes it, thereby achieving the object of the present invention. As the processor, for example, a CPU (Central Processing Unit) can be used. As the recording medium, in addition to a “non-temporary tangible medium” such as a ROM (Read Only Memory), a tape, a disk, a card, a semiconductor memory, a programmable logic circuit, or the like can be used. Further, a RAM (RandomAccessMemory) for expanding the above program may be further provided. Further, the program may be supplied to the computer via an arbitrary transmission medium (communication network, broadcast wave, etc.) capable of transmitting the program. It should be noted that one aspect of the present invention can also be realized in the form of a data signal embedded in a carrier wave, in which the above program is embodied by electronic transmission.

The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the claims, and the embodiments obtained by appropriately combining the technical means disclosed in the different embodiments. Is also included in the technical scope of the present invention.

For example, a control device provided outside the IC chip may control an analog device having a plurality of analog elements provided on the IC chip so that the value of the first characteristic and the analog element are associated with each other. Even in this case, a high-performance measuring device becomes unnecessary.

1 Temperature sensor (analog device, analog element association system)
2 Control device 3 Switching unit 4 Bias generation circuit 5 Capacitor 6 Charging transistor 7 Inversion amplifier 8 TDC (Measuring device)
9 Arithmetic unit 10a, 10b Volatile recording medium 11 Logic circuit 20 ADC (Analog device, analog element association system)
21 Sample hold circuit 22 Comparator group (multiple analog elements)
23 Switch matrix 24 Encoder 25 Voltage measurement circuit (measurement device)
26 Control device 27 Switching element group Tr Transistor group (multiple analog elements)

Claims (8)

1. An analog device installed on an IC chip
   The analog device includes a plurality of analog elements that perform analog operation and a control device that controls the operation of the analog device.
   Each of the analog elements
   The first characteristic related to the operation of the analog device, the first characteristic in which the variation follows a statistical distribution, and
   It is a second characteristic related to the first characteristic and has a second characteristic that can be measured on-chip.
   The control device is
   The plurality of analog elements are ordered according to the measured value of the second characteristic,
   An analog device characterized in that the value of the first characteristic and the analog element are associated with each other based on the statistical distribution regarding the first characteristic and the order of the analog elements.
2. The analog device according to claim 1, wherein the control device operates the analog element corresponding to a predetermined value of the first characteristic.
3. Further equipped with a measuring device for measuring the second characteristic,
   The analog device according to claim 1 or 2, wherein the control device orders a plurality of the analog elements according to a measured value of a second characteristic measured by the measuring device.
4. The analog element is a transistor and
   The first characteristic of the analog element is the threshold voltage of the transistor.
   The analog device according to any one of claims 1 to 3, wherein the second characteristic of the analog element is a subthreshold leakage current of the transistor.
5. The analog element is a comparator and
   The first characteristic of the analog element is the offset voltage of the comparator.
   The second characteristic of the analog element is the output voltage when a part of the plurality of transistors included in the comparator is stopped, and the output voltage when the other part of the plurality of transistors is stopped. The analog device according to any one of claims 1 to 3, wherein the analog device is the difference from the above.
6. An analog device provided on an IC chip, the analog device includes a plurality of analog elements that perform analog operation, and each of the analog elements is a first characteristic related to the operation of the analog device. This is a control method for an analog device having a first characteristic in which the variation follows a statistical distribution and a second characteristic related to the first characteristic, which is a second characteristic that can be measured on-chip.
   A step of ordering a plurality of the analog elements according to the measured value of the second characteristic, and
   A method for controlling an analog device, which comprises a step of associating a value of the first characteristic with the analog element based on the statistical distribution regarding the first characteristic and the order of the analog elements.
7. It is a temperature sensor installed on the IC chip.
   Capacitors and
   A plurality of transistors connected in parallel to the capacitor,
   A plurality of switching elements provided between the capacitor and each of the plurality of transistors, and
   It is equipped with a control device that controls the plurality of switching elements.
   The control device is
   For each of the plurality of transistors, the discharge time until the current from the capacitor is discharged to the transistor and the voltage of the capacitor drops to a predetermined voltage is measured.
   A temperature sensor characterized in that the ratio of at least two discharge times of the plurality of transistors is output as temperature information.
8. A plurality of analog elements provided on the IC chip and performing analog operation,
   A control device for controlling the operation of the analog element is provided.
   Each of the analog elements
   The first characteristic that the variation follows a statistical distribution,
   It is a second characteristic related to the first characteristic and has a second characteristic that can be measured on-chip.
   The control device is
   The plurality of analog elements are ordered according to the measured value of the second characteristic,
   An analog element mapping system, characterized in that the value of the first characteristic is associated with the analog element based on the statistical distribution relating to the first characteristic and the order of the analog elements.

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