TW202122766A - Analog device and control method of the same, temperature sensor, and analog element associating system - Google Patents

Abstract

This disclosure is to estimate a threshold voltage value of a transistor related to the operation of a temperature sensor. Each of a plurality of transistors (Mn) performing analog operation has a threshold voltage related to the operation of the temperature sensor (1) and whose variation follows a statistical distribution, and a sub-threshold leakage current corresponding to the threshold voltage. A control device (2) orders a plurality of transistors (Mn) according to the measured value of the sub-threshold leakage current and associates the value of the threshold voltage with the transistor (Mn) based on the statistical distribution regarding the threshold voltage and the order of the transistors (Mn).

Description

Analog device and its control method, temperature sensor, and analog element corresponding system

The present invention relates to an analog device installed on an IC (Integrated Circuit) chip, a control method thereof, a temperature sensor, and an analog component corresponding system.

In the CMOS (Complementary Metal Oxide Semiconductor) process, mixing digital circuits and analog circuits on a single IC chip has the advantages of miniaturization, high-speed operation, and low power consumption. However, one of the problems when designing analog devices using MOS transistors is the deviation of device characteristics during manufacturing. With the miniaturization of the manufacturing process, the deviation of the transistor has increased, and as a result, the deviation of the characteristics of the analog device has increased. As a result, there is a concern that the above-mentioned analog devices cannot achieve specific performance.

In order to suppress the characteristic deviation of the above-mentioned analog device, consider increasing the area of the above-mentioned analog device. However, in this case, not only the size of the above-mentioned analog device will increase, but also the power consumption and manufacturing cost will increase. [Prior Technical Literature] [Non-Patent Literature]

[Non-Patent Literature 1] T. Sundstrom and A. Alvandpour, "Utilizing process variations for reference generation in a flash ADC," IEEE Trans. Circuits Syst. II Express Briefs, vol. 56, no. 5, pp. 364-368 , 2009 [Non-Patent Document 2] V. H. Chen and L. Pileggi, "An 8.5mW 5GS / s 6b Flash ADC with Dynamic Offset Calibration in 32nm CMOS SOI," in IEEE Symposium on VLSI Circuits, 2013, pp. 264-265 [Non-Patent Document 3] T. Someya, AKMM Islam, T. Sakurai, and M. Takamiya, "An 11-nW CMOS temperature-to-digital converter utilizing sub-threshold current at sub-thermal drain voltage," IEEE Journal of Solid-State Circuits, vol.54, no.3, pp.613-622, 2019 [Non-Patent Document 4] H. Wang and P.P. Mercier, "Near-zero-power temperature sensing via tunneling currents through complementary metal-oxide-semiconductor transistors," Scientific Reports, vol.7, no.1, p.4427, 2017 [Non-Patent Document 5]AKMM Islam, J. Shiomi, T. Ishihara, and H. Onodera, "Wide-supply-range all-digital leakage variation sensor for on-chip process and temperature monitoring," IEEE Journal of Solid-State Circuits, vol.50, no.11, pp.2475-2490, 2015. [Non-Patent Document 6] K. Yang, Q. Dong, W. Jung, Y. Zhang, M. Choi, D. Blaauw, and D. Sylvester, "A 0.6nJ -0.22/+0.19℃ inaccuracy temperature sensor using exponential subthreshold oscillation dependence,'' IEEE International Solid-State Circuits Conference, pp.160-162, 2017 [Non-Patent Document 7] T. Tsunomura, A. Nishida, F. Yano, AT Putra, K. Takeuchi, S. Inaba, S. Kamohara, K. Terada, T. Hiramoto, and T. Mogami, "Analyses of 5 σ Vth fluctuation in 65nm-MOSFETs using takeuchi plot,'' Symposium on VLSI Technology, pp.156-157, June 2008 [Non-Patent Document 8] M.J.M. Pelgrom, A.C.J. Duinmaijer, and A.P.G. Welbers, "Matching properties of MOS transistors," IEEE Journal of Solid-State Circuits, vol.24, no.5, pp.1433-1439, Oct. 1989

[The problem to be solved by the invention]

In response to the above problems, Non-Patent Documents 1 and 2 disclose flash ADCs (Analog-to-Digital Convertor) that convert analog signals into 6-bit digital signals. In the ADC, a single IC chip is provided with: 63 comparators, which are input with the above-mentioned analog signal; and a decoder, which converts the signal from the 63 comparators into a 6-bit digital signal. Each of the above-mentioned comparators takes advantage of the fact that the bias voltage follows a normal distribution, instead of the reference voltage, and uses the above-mentioned bias voltage as a reference for AD conversion.

In the case of the above-mentioned ADC, since the deviation of the bias voltage of the comparator (the characteristic deviation of the device) is used, there is no need to suppress the above deviation. Therefore, there is no need to increase the area of the comparator, and the increase in power consumption and manufacturing cost can be suppressed.

On the other hand, the bias voltage of each comparator must be accurately measured. However, it is difficult to accurately measure the above-mentioned bias voltage on the above-mentioned IC chip (on chip). Moreover, when measuring the bias voltage with the external measuring equipment of the IC chip, a high-performance measuring equipment is required, and an output port for measuring the bias voltage must be provided in the IC chip.

An object of one aspect of the present invention is to realize an analog device or the like capable of estimating the value of the first characteristic of an analog element related to the operation of the analog device. [Means to solve the problem]

An analog device of one aspect of the present invention is provided on an IC chip, wherein: the analog device includes a plurality of analog elements for performing analog operations, and a control device for controlling the motion of the analog device, each of the analog elements has: 1 characteristic, which is related to the action of the above-mentioned analog device, and the deviation follows a statistical distribution; and the second characteristic, which is related to the first characteristic and can be measured on chip; the above-mentioned control device is based on the second characteristic The measured value ranks the plurality of the analog elements, and the value of the first characteristic corresponds to the analog element based on the statistical distribution related to the first characteristic and the order of the analog elements.

Furthermore, in the condenser device of this aspect, the control device preferably operates the analog element corresponding to the specific value of the first characteristic. In addition, the control device may also stop analog elements other than the analog element corresponding to the specific value of the first characteristic.

Furthermore, the capacitor device of this aspect is further provided with a measuring device for measuring the second characteristic, and the control device may also sequence a plurality of the analog elements based on the measured value of the second characteristic measured by the measuring device.

In one example, the analog element is a transistor, the first characteristic of the analog element is the threshold voltage of the transistor, and the second characteristic of the analog element is the sub-threshold leakage current of the transistor. ).

In another example, the analog element is a comparator, the first characteristic of the analog element is the bias voltage of the comparator, and the second characteristic of the analog element is a part of the plurality of transistors included in the comparator. The difference between the output voltage when the operation is stopped and the output voltage when the other part of the plurality of transistors is stopped.

In another aspect of the control method of an analog device of the present invention, the analog device is provided on an IC chip, and the analog device is provided with a plurality of analog elements that perform analog operations, and each of the analog elements has a similar value to that of the analog device. The first characteristic that is action-related and the deviation follows the statistical distribution, and the second characteristic that is related to the first characteristic and can be measured on the chip, the control method of the above analog device includes the following steps: according to the measured value of the second characteristic, a plurality of The step of sequencing the above-mentioned analog components; and the step of making the value of the first characteristic correspond to the above-mentioned analog components based on the above statistical distribution related to the first characteristic and the order of the above-mentioned analog components.

Another aspect of the present invention is that the temperature sensor is arranged on an IC chip, and includes: a capacitor; a plurality of transistors connected in parallel with the capacitor; and a plurality of switching elements, etc., are provided above Between the capacitor and each of the plurality of transistors; and a control device that controls the plurality of switching elements; the control device measures the current discharged from the capacitor to the transistor for each of the plurality of transistors The discharge time until the voltage of the capacitor drops to a specific voltage is output as temperature information by the ratio of at least two discharge times of the plurality of transistors.

A temperature sensor of another aspect of the present invention includes: a plurality of analog elements, which are arranged on an IC chip and perform analog operations; and a control device, which controls the motion of the analog elements; each of the above-mentioned analog elements has : The first characteristic, the deviation of which follows a statistical distribution; and the second characteristic, which is related to the first characteristic and can be measured on the chip; the above-mentioned control device is based on the measured value of the second characteristic to sequence the plurality of the above-mentioned analog components, And based on the statistical distribution related to the first characteristic and the order of the analog element, the value of the first characteristic corresponds to the analog element. [Effects of Invention]

According to one aspect of the present invention, it is possible to estimate the value of the first characteristic of the analog element related to the operation of the analog device.

[Embodiment 1]

Hereinafter, an embodiment of the present invention will be described in detail. (Composition of temperature sensor)

Fig. 1 is a circuit diagram showing a schematic configuration of a temperature sensor 1 (an analog device) according to an embodiment of the present invention.

The temperature sensor 1 is installed on a single IC chip and includes a control device 2, a switching unit 3, an analog transistor group Tr, a bias voltage generating circuit 4, a capacitor 5, a charging transistor 6, an inverter amplifier 7, and TDC (time- Digital converter, Time-to-Digital Convertor) 8, and arithmetic unit 9. In addition, from the viewpoints of miniaturization, high-speed operation, low power consumption, etc., the above-mentioned IC chip is preferably a CMOS IC chip.

The control device 2 controls the operation of the temperature sensor 1. Specifically, the control device 2 is inputted with the result of the clock signal Clock and TDC8. The control device 2 is configured to control the on and off of the switching element included in the switching unit 3 and to control the gate potential of the charging transistor 6.

The switching unit 3 is configured to selectively connect one electrode of the capacitor 5 to the source terminal of any one of the N transistors Mn. In addition, N is a natural number of 2 or more.

FIG. 2 is a circuit diagram showing an example of the configuration of the switching unit 3. As shown in Fig. 2, the switching unit 3 includes N switching elements S (first switching element S ₁ to N-th switching element S _N ). It is a fine MOSFET (Metal-Oxide Semiconductor Field-Effect Transistor) that operates with S coefficients of each switching element.

The analog transistor group Tr includes N transistors Mn (first transistor Mn ₁ to N-th transistor Mn _N ) (analog elements), and each transistor Mn is a fine n-type MOSFET. K-th transistor Mn _k (N k is an integer of 1 ~), the source terminal is grounded, the drain terminal via the switching section of the switching element S _k 3 k of the capacitor 5 is connected, a gate terminal connected to the bias generation Circuit 4. Each transistor Mn operates analogously, that is, the bias voltage V _{b below the threshold voltage V th} is applied and used. Since the Mn of the N transistors are fine, their characteristics will not be negligible deviations during manufacturing. This point will be described later.

_{The bias voltage generating circuit 4 generates a bias voltage V b} to be applied between the gate and the source of the N transistors Mn. The bias voltage V _{b is lower than the threshold voltage V th1} to V _thN of any one of the first transistor Mn ₁ to the Nth transistor Mn _N.

In the capacitor 5, one electrode is connected to the switching part 3, the drain terminal of the charging transistor 6 and the input terminal of the inverting amplifier 7, and the other electrode is grounded.

The charging transistor is a tiny MOSFET that operates at six coefficients. In the charging transistor 6, the source terminal is connected to the power supply voltage V _dd on the high potential side, the drain terminal is connected to the capacitor 5, and the gate terminal is connected to the control device 2.

In the inverting amplifier 7, the input terminal is connected to the capacitor 5, and the output terminal is connected to the TDC8.

TDC8 is the result of inputting the clock signal Clock and inverting the amplifier 7. The TDC8 measures the discharge time required for the _{output voltage V out} of the capacitor 5 to decrease to a given threshold voltage V _c. The TDC8 outputs the discharge time to the control device 2 and the arithmetic unit 9 in the form of a digital value.

The arithmetic unit 9 receives the clock signal Clock and the discharge time from the TDC8. The arithmetic unit 9 includes two volatile recording media (registers) 10a, 10b and a logic circuit 11. The two volatile recording media 10a, 10b temporarily store two discharge times from the TDC8, respectively. The logic circuit 11 calculates the discharge time ratio between the discharge time stored in the volatile recording medium 10a and the discharge time stored in the volatile recording medium 10b, and outputs a digital signal corresponding to the discharge time ratio as temperature information indicating temperature. Then, when receiving the above-mentioned digital signal, a control device not shown in the figure calculates and outputs the temperature based on the correction data based on the discharge time ratio. Here, the control device not shown in the figure may be a control device in the same IC chip or a control device of another chip. In addition, the details of the above-mentioned temperature calculation method (digital signal output method) will be described later. (Action of temperature sensor)

FIG. 3 is a flowchart showing an example of the operation of the temperature sensor 1 shown in FIG. 1.

When the temperature sensor 1 starts temperature sensing (START), the control device 2 starts operating from the initial setting k=1 (step S1). The control device 2 first executes a subroutine for measuring the k-th discharge time d _{k when} the capacitor 5 is discharged through the k-th transistor Mn _k (step S2). In addition, this subroutine will be described later. Then, the control device 2 writes the k-th discharge time to the volatile recording medium in the control device 2 (step S3), and determines whether k=N is satisfied (step S4). If it is "No" in step S4, k is increased by 1 (step S5), and the process returns to step S2.

If "YES" in step S4, the control device 2 ends the measurement of the discharge time, and reads the measured first discharge time d ₁ to the Nth discharge time d _N (step S6). _{Then, the control device 2 sorts the first transistor Mn 1} to the Nth transistor Mn _{N in} a manner that the discharge time is arranged in ascending order (or descending order) (step S7). That is, the control device 2 orders the _{first transistor Mn 1} to the N-th transistor Mn _{N in} the ascending order (or descending order) of the discharge time.

After the sequencing is completed as described above, the control device 2 selects the first reference transistor Tr ₁ and the second reference transistor Tr _{2 in the} following manner.

The control device 2 reads the order of the first reference transistor Tr ₁ (step S8). Then, among the first transistor Mn ₁ to the N- _{th transistor Mn N} , the i-th transistor Mn _i located in this position is selected as the first reference transistor Tr ₁ (step S9), and the selection result is written to In the volatile recording medium in the control device 2 (step S10). Similarly, the control device 2 reads the order of the second reference transistor Tr ₂ (step S11). Then, among the first transistor Mn ₁ to the N- _{th transistor Mn N} , the j-th transistor Mn _j located in this position is selected as the second reference transistor Tr ₂ (step S12), and the selection result is written to In the volatile recording medium in the control device 2 (step S13). In addition, the control device 2 may execute steps S8 to S10 and steps S11 to S13 simultaneously or in the reverse order. In addition, the order of reading in steps 8 and 11 will be described later.

After making the selection as described above, the control device 2 measures the first reference discharge time d _ref1 and the second reference discharge time d _{ref2 in the} following manner.

Read control means 2 about the first reference transistor Tr selection result (step S14) of _a provided measurement i-discharge time D _i of the set k = i (Step S15), performs measuring capacitor 5 by the k-th transistor Mn _k The subroutine of the k-th discharge time d _k during discharge (step S16). Then, the control device 2 writes the i-th discharge time di as the first reference discharge time _dref1 in the first volatile recording medium 10a in the arithmetic unit 9 (step S17). Similarly, the control device 2 is read out on a second reference transistor Tr selection result (step S18) _2, the provided measurement j-discharge time D _j of the set k = j (step S19), performs measuring capacitor 5 by the k-th power The subroutine of the k-th discharge time d _k when the crystal Mn _{k is} discharged (step S20). Then, the control device 2 writes the j-th discharge time dj as the second reference discharge time _dref2 in the second volatile recording medium 10b in the arithmetic unit 9 (step S21).

After that, the arithmetic unit 9 reads the first reference discharge time d _ref1 and the second reference discharge time d _ref2 (step S22). Then, the arithmetic unit 9 to use logic circuit 11 calculates the first reference discharge time d _REF1 and second reference discharge time d discharge time _ref2 ratio d _ref1 / d _ref2 (step S23), generates a digital signal and outputs (step S24). In addition, the arithmetic unit 9 may also _{read the correction data after calculating the discharge time ratio d ref1} /d _ref2 , and calculate and output the absolute temperature based on the discharge time ratio d _ref1 /d _{ref2 and the correction data.} Then, it is determined whether to end (step S25), if it is "Yes", the temperature sensing is ended (END), and if it is "No", it returns to step 14.

The information stored in the volatile recording medium will be erased if the temperature sensing ends. Therefore, the temperature sensor 1 repeats the operation from step S1 every time it starts temperature sensing. (Subprogram for measuring discharge time)

4 is a flowchart showing an example of a subroutine (steps S2, 16, 20) of the _k -th discharge time d k when the measuring capacitor 5 shown in FIG. 3 is _{discharged through the k-th transistor Mn k.}

When the subroutine is started (START), first, charging is started (step S31). In step S31, the control device 2 issues an instruction to the switching unit 3 so that the switching unit 3 turns on all the switching elements and cuts off the analog transistor group Tr from the capacitor 5. After the disconnection, the control device 2 applies the gate voltage of the charging transistor 6 so that the charging transistor 6 is in an energized state. _{Then, regarding the potential difference V out} between the two ends of the capacitor 5, it is determined whether V _out =V _dd (step S32). If it is "No" in step S32, the charging is continued, and if it is "YES", the charging is ended (step S33). In step S33, the control device 2 applies the gate voltage of the charging transistor 6 so that the charging transistor 6 is in a non-energized state.

After the charging is completed, the discharge is started (step S34), and at the same time, the measurement of the discharge time is also started (step S35). In step S34, the control device 2 issues an instruction to the switching unit 3 to _{connect only the k-th transistor Mn k} to the capacitor 5 and keep the other transistors in a disconnected state from the capacitor 5. The switching part 3 shown in FIG. 2 only sets the k-th switching element _Sk to the off state, and keeps the other switching elements in the on state. In step S35, TDC8 in V _out <V _dd between, measured from V _out = V _dd of the elapsed time from the time point, the elapsed time and continues to output digital conversion.

During discharging, the control device 2 determines whether or not V _out &lt; V _c (step S36). V _c is the given threshold value of the potential difference of the capacitor 5. If "No" in step S36, continue to discharge. If it is "Yes", it is determined that the capacitor 5 has been fully discharged, and the discharge is terminated (step S37). At the same time, the measurement of the discharge time also ends (step S38). In step S37, the control device 2 issues an instruction to the switching unit 3 so that the switching unit 3 sets all the switching elements to the ON state. In step S38, the elapsed time output from the TDC8 at this point in time is acquired as the k-th discharge time d _k . (Prior art temperature sensor)

Various measurement principles are used in the on-chip temperature sensor of the prior art.

As an example, there is a band gap type temperature sensor using bipolar transistors with the same characteristics (Non-Patent Documents 3 and 4). As another example, there are temperature sensors that use subcritical characteristics of two MOSFETs with the same characteristics (Non-Patent Documents 5 and 6). However, in either method, an on-chip temperature sensor with low power consumption and a linear relationship (PTAT, proportional-to-absolute-temperature) between the output value and the temperature cannot be achieved.

Moreover, either method requires two transistors with the same characteristics. When the transistor is manufactured, the characteristic deviation of the transistor will occur, and the smaller the size of the transistor, the greater the characteristic deviation. After manufacturing the transistor, it is difficult to accurately measure the characteristics of the transistor. Therefore, in the prior art, the transistor is manufactured in a size larger than the minimum size that can be manufactured, thereby reducing the characteristic deviation of the transistor. (The measuring principle of the temperature sensor of the present invention)

Hereinafter, the measurement principle of the temperature sensor 1 of the present invention will be described in detail.

Figure 5 is a circuit diagram for explaining the principle of measurement. _{Fig. 6 is a graph showing an example of the voltage and current characteristics of the first and second transistors M n1} and M _n2 in the circuit shown in Fig. 5. In more detail, it shows the case where the drain-source voltage is fixed The diagram below shows an example of the relationship between the voltage between the gate and the source and the drain current.

In the two circuits shown in Figure 5, except for the first transistor M _n1 and the second transistor M _n2 , they are all the same. _{The voltage V DS1} between the drain and the source of the capacitor 5 applied to the first transistor M _{n1 is} the same as _{the voltage V DS2} between the drain and the source of the capacitor 5 applied to the second transistor M _n2. These two circuits can be realized by switching only the first switching element S ₁ or only the second switching element S _{2 in the} off state by the switching unit 3.

In the example shown in FIG. 6, the threshold voltage V _{th1 of the first transistor M n1} is greater than the threshold voltage V _{th2 of} the second transistor M _n2 . Apply a bias voltage V _b smaller than the threshold voltages V _th1 and V _th2 between the gate and source of the first transistor M _n1 , and apply the same bias voltage V _b to the gate of the second transistor M _n2 Between the source. At this time, the first transistor M _n1 flowing drain current I _1, the second transistor M _n2 flowing drain current I _2. The drain currents I ₁ and I ₂ are subcritical leakage currents, and they represent different values as shown in FIG. 6. It is approximately represented by the following equations (1) and (2).

[數2]

此處，T表示絕對溫度，K表示依存於製造製程之係數，n表示次臨界係數，k表示玻爾茲曼常數，q表示電荷量，λ₁ 、λ₂ 、α₁ 、α₂ 表示正係數，V_DS1 表示第1電晶體M_n1 之汲極‐源極間電壓，V_DS2 表示第2電晶體M_n2 之汲極‐源極間電壓。因V_DS1 ≒V_DS2 ，且λ₁ 、λ₂ 、α₁ 、α₂ 之偏差可忽視，故近似為α₁ T－α₂ T≒0、λ₁ V_DS1 －λ₂ V_DS2 ＝≒0。因此，T由下述式(3)近似。[Number 1]

[Number 2]

Here, T represents the absolute temperature, K represents the coefficient dependent on the manufacturing process, n represents the subcritical coefficient, k represents Boltzmann's constant, q represents the amount of charge, and λ ₁ , λ ₂ , α ₁ , and α ₂ represent positive coefficients , V _DS1 represents the drain-source voltage of the first transistor M _{n1 , and V DS2} represents the drain-source voltage of the second transistor M _n2 . Because V _DS1 ≒ V _DS2 , and _{the deviation of λ 1} , λ ₂ , α ₁ , and α ₂ can be ignored, it is approximated as α ₁ T-α ₂ T≒0, λ ₁ V _DS1 -λ ₂ V _DS2 =≒0. Therefore, T is approximated by the following equation (3).

根據式(3)，可用不依存於偏置電壓V_b 之方式算出絕對溫度T。因閾值電壓V_th1 、V_th2 (第1特性)為第1電晶體M_n1 與第2電晶體M_n2 之特性值，故為常數。因此，絕對溫度T與汲極電流之比I₂ /I₁ 的自然對數處於線性關係。此處，若適當地設定ΔV_th ＝V_th1 －V_th2 ，則於任意溫度範圍內線性近似自然對數，藉此絕對溫度T可與汲極電流比I₂ /I₁ 近似為線性關係。利用該線性關係，能夠不依存於偏置電壓V_b 地進行輸出值與溫度處於線性關係的溫度感測。[Number 3]

According to equation (3), the absolute temperature T can be calculated _{without depending on the bias voltage V b.} Since the threshold voltages V _th1 and V _th2 (first characteristic) are _{characteristic values of the first transistor M n1} and the second transistor M _n2 , they are constants. _{Therefore, the natural logarithm of the ratio I 2} /I ₁ of the absolute temperature T to the drain current is in a linear relationship. Here, if ΔV _th =V _th1 −V _th2 is appropriately set, the natural logarithm can be linearly approximated in any temperature range, whereby the absolute temperature T can be approximately linearly related _{to the drain current ratio I 2} /I _1. Using this linear relationship, temperature sensing in which the output value and temperature are in a linear relationship can be performed independently of the bias voltage V _b.

In the two circuits shown in FIG. 2, the capacitor 5 is _{charged with the same power supply voltage V dd} , and the same bias voltage V _b is applied to the first transistor M _n1 and the second transistor M _n2 . In this case, the following equation (4) holds approximately.

此處，d₁ 係指以包含第1電晶體M_n1 之電路(圖2之左側的電路)，電容器5之輸出電壓V_out 減少至給定的閾值電壓V_c 所需之時間，d₂ 係指以包含第2電晶體M_n2 之電路(圖2之右側的電路)，電容器5之輸出電壓V_out 減少至相同的給定閾值電壓V_c 所需之放電時間。[Number 4]

Here, d ₁ refers to the time required for the _{output voltage V out of the} capacitor 5 to decrease to a given threshold voltage V _{c in} the circuit including the first transistor M _n1 (the circuit on the left in FIG. 2 ), _{and d 2} is It refers to the discharge time required for the _{output voltage V out of the} capacitor 5 to decrease to the same given threshold voltage V _{c in} the circuit including the second transistor M _n2 (the circuit on the right side of FIG. 2 ).

Therefore, the drain current ratio I ₂ /I ₁ can be approximately linearly related to the absolute temperature, so the discharge time ratio d ₁ /d ₂ can also be approximately linearly related to the absolute temperature. Thus, temperature sensing can be performed by measuring the discharge time ratio d ₁ /d _2. (How to select transistors)

As described above, the characteristics of the N transistors Tr have deviations that cannot be ignored. It is reported that when many MOSFETs are manufactured on one wafer, the threshold voltage of the MOSFETs follows a normal distribution (statistical distribution) represented by the following formula (5) (Non-Patent Document 7). The standard deviation σ of this distribution is calculated from the following equation (6) based on Pelgrom's Law (Non-Patent Document 8).

[數6]

此處，A_Vth 係依存於製造製程之參數，W係電晶體之閘極寬度之設計值，L係電晶體之閘極長度之設計值。因此，式(5)中之標準偏差σ係由製造製程及電晶體尺寸之設計所決定之常數值。[Number 5]

[Number 6]

Here, A _Vth is a parameter that depends on the manufacturing process, the design value of the gate width of the W series transistor, and the design value of the gate length of the L series transistor. Therefore, the standard deviation σ in formula (5) is a constant value determined by the manufacturing process and the design of the transistor size.

Thus, it is difficult to set the first transistor M _n1 threshold voltage V _th1 of the second transistor M _n2 of the threshold voltage V _th2 to properly obtain ΔV _th = V _th1 -V _th2. However, the first reference transistor Tr ₁ and the second reference transistor Tr ₂ can be selected from the first transistor Mn ₁ to the N- _{th transistor Mn N} to appropriately obtain ΔV th =V _{th , ref1} −V _{th , ref2} . Here, V _{th , ref1} are the threshold voltages of the first reference transistor Tr _{1 , and V th , ref2} are the threshold voltages of the second reference transistor Tr ₂ .

FIG. 7 is a diagram showing the deviation of _{the threshold voltage V th in the analog transistor group Tr.}

As shown in FIG. 7, the threshold voltage V _th of the N transistors Mn that are sorted follows the normal distribution as described above. Therefore, based on statistical estimation, the first reference transistor Tr ₁ has existed in the order of the ratio calculated by the following formula (7) from the beginning. Similarly, the second reference transistor Tr ₂ has existed from the beginning in the order of the ratio calculated by the following formula (8).

[數8]

上述步驟8中讀出之第1參考電晶體Tr₁ 之位次係由式(7)求出之位次，步驟S11中讀出之第2參考電晶體Tr₂ 之位次係由式(8)求出之位次。[Number 7]

[Number 8]

The order of the first reference transistor Tr ₁ read in the above step 8 is calculated by equation (7), and the order of the second reference transistor Tr ₂ read in step S11 is calculated by the equation (8 ) Find the rank.

The above statistical inference system is closer to the center of the normal distribution, the higher the accuracy. Therefore, the reference threshold voltages V _{th , ref1} , V _{th , and ref2 are} preferably selected in such a way that their arithmetic average is close to the center of the normal distribution. The greater the number of the above statistical presumptions, the higher the accuracy. Therefore, it is preferable that N is larger. Since the N transistors Mn are different from the transistors that operate analogously in the sensor chip of the prior art, they are fine. Therefore, even if N is large, the temperature sensor 1 can be miniaturized. Furthermore, this statistical estimation may also be a statistical distribution other than the normal distribution such as β distribution and γ distribution. (Sequencing method of transistors)

When the current I _i flowing through the i-th transistor M _{ni in} the above subroutine is at V _c =0V, according to the subcritical characteristics of the MOSFET, it is approximately expressed by the following formula (9).

此處，λ_i 、α_i 表示正係數，V_thi 表示第i電晶體M_ni 之閾值電壓，V_DSi 表示第i電晶體M_ni 之汲極‐源極間電壓。[Number 9]

Here, λ _i, α _i denotes a positive coefficient, V _thi i th represents the threshold voltage of the transistor M _ni, V _DSi is the i transistor M _ni the drain - source voltage.

Therefore, the larger the _{threshold voltage V thi} , the smaller the _{current I i.}

Comparing the i-th transistor Mn _i and the j-th transistor Mn _j among N transistors Mn, the relationship approximately expressed by the following formula (10) holds.

在V_c ＞0V之情況，放電時間比d_i /d_j ≒I_j /I_i 之關係亦成立。因此，放電電流I_i 越小，放電時間d_i 越長。因此，上述步驟S7中，以放電時間(第2特性)按升序排列的方式將N個電晶體Mn排序，藉此以閾值電壓按升序排列的方式將N個電晶體Mn排序。[Number 10]

In V _c> 0V case, the discharge time ratio _{d i / d j ≒ I j} / I _i the relation is also established. Therefore, the discharge current I _i, the longer the discharge time d _i. Therefore, in the above step S7, the N transistors Mn are sorted in an ascending order of discharge time (the second characteristic), thereby sorting the N transistors Mn in an ascending order of threshold voltage.

In addition, the graph on the upper side of FIG. 7 shows the threshold voltage V _th with respect to the discharge time d. This also means that the _{larger the threshold voltage V thk} , the longer the discharge time d _k. (Effect)

As described above, in the temperature sensor 1 of the present invention, the N transistors Mn included in the analog transistor group Tr are sorted (sequenced) in the ascending or descending order of the discharge time d. Then, based on the normal distribution and variation of the order of Mn transistor threshold voltage V _th of the threshold voltage V _th of the transistor corresponding to Mn. Therefore, the relative value _{of the threshold voltage V th} corresponding to the other transistors Mn of each transistor Mn can be estimated on the wafer.

The temperature sensor 1 of the present invention selects the first reference transistor Tr ₁ and the second reference transistor Tr ₂ from the N transistors Mn included in the analog transistor group Tr to appropriately obtain ΔV _th =V _{th , Ref1-} V _{th , ref2} . Thereby, the temperature sensor 1 can be operated appropriately. Therefore, the temperature information can be detected without measuring the threshold voltage V _{th of the} transistor Mn. Therefore, there is no need to increase the area of the temperature sensor 1 and the increase in power consumption and manufacturing cost can be suppressed. Furthermore, there is no need for a high-performance measuring device for measuring the threshold voltage Vth.

The temperature sensor 1 of the present invention does not require multiple analog transistors with the same characteristics, and allows the characteristics of the analog transistors to deviate. Therefore, in the temperature sensor 1 of the present invention, the analog transistor can be miniaturized, so that the temperature sensor 1 can operate with current saving, thereby saving power and miniaturization.

The temperature sensor 1 of the present invention does not require a reference voltage or a reference current. Therefore, the temperature sensor 1 of the present invention can save power and be miniaturized.

The temperature sensor 1 of the present invention does not require a non-volatile recording medium. Therefore, the temperature sensor 1 of the present invention can save power and be miniaturized.

The temperature sensor 1 of the present invention performs the sorting of the transistors Mn and the selection of the _{reference transistors Tr 1} and Tr _{2 every time the temperature is sensed.} Even if a few of the N transistors Mn deteriorate, there is no substantial change in the distribution followed by the N transistors Mn. Therefore, in the temperature sensor 1 of the present invention, even if a few transistors Mn deteriorate, the accuracy of temperature sensing can be suppressed from deterioration, and the function as the temperature sensor 1 can be maintained. [Embodiment 2]

Hereinafter, other embodiments of the present invention will be described. In addition, for convenience of description, members having the same functions as those described in the above-mentioned embodiments are given the same reference numerals, and the description thereof will not be repeated.

FIG. 12 is a circuit diagram showing an example of the configuration of the switching unit 3 of this embodiment.

As shown in FIG. 12, the switching unit 3 has a tree type. FIG. 12 shows an example of a binary tree structure, and types other than binary trees such as a ternary tree, a quaternary tree, and a quintuple tree may also be included. As shown in FIG. 12, when it is composed of a binary tree, the parasitic capacitance connected to the capacitor 5 in parallel is _{proportional to log 2} (N). Therefore, compared with the configuration example (parasitic capacitance N) shown in FIG. 2 in which N switching elements S are connected in parallel in one stage, the parasitic capacitance can be reduced and the discharge time can be shortened.

FIG. 13 shows an equivalent circuit when the _{first transistor Mn 1 is} connected to the capacitor 5 in the switching section 3 shown in FIG. 12. (Appropriate threshold voltage difference)

As described above, the absolute temperature T is approximately expressed by the following formula (11).

因這是近似的，故較佳為以使近似誤差小的方式決定閾值電壓差ΔV_th (第1特性)。[Number 11]

Since this is an approximation, it is preferable to determine the threshold voltage difference ΔV _th (first characteristic) so that the approximation error is small.

As an example, in the circuit shown in Fig. 1 in the simulation, the switching section 3 is set to the configuration shown in Fig. 12, and ΔV _th varies from -80mV to -60mV in units of 2mV, and is set at 0～100℃ within the scope of the obtained first reference transistor Tr ₁ d ₁ of discharge time and the second reference transistor Tr ₂ of the discharge time the discharge time ₂ d ratio d ₁ / d _2. Fig. 8 shows the simulation result.

According to the simulation results shown in Figure 8, the coefficient of determination (Adjust-R ² ) of the adjusted degrees of freedom is calculated. The coefficient of determination of the adjusted degrees of freedom is the value for evaluating the linearity. The closer the coefficient of determination of the adjusted degree of freedom is to 1, the higher the linearity of the relationship between the _{discharge time ratio d 1} /d _{2 and the temperature T is.} Fig. 9 shows the coefficient of determination of the adjusted degree of freedom.

As shown in Fig. 9, when ΔV _th = -64mV, the linearity is closest to 1. Therefore, ΔV _th = -64mV is the optimal threshold voltage difference. (Evaluation of error)

In the above simulation example, the measurement error in the case where _{ΔV th =-64mV is set is evaluated.}

Set the analog transistor group Tr shown in Fig. 1 to N=1024, and randomly generate 10 times. Then, steps S1 to S13 are executed to obtain 10 sets of reference threshold voltages (V _{th , ref1} , V _{th , ref2} ). It should be noted that at this point in time, errors of _{V th , ref1-} V _{th , ref2 ≠ -64mV occurred in each group.}

Using the combination of the 10 sets of reference threshold voltages, the discharge time ratio d ₁ /d ₂ was measured in the range of 0-100°C. Fig. 10 shows the results of this measurement.

The temperature is calculated by calibrating the measurement results shown in Fig. 10 at two points of 20°C and 80°C. Fig. 11 shows the error of the calculated temperature.

As shown in Figure 11, even in the worst case, the error is within ±1.2°C.

In addition, in order to reduce this error, it is sufficient to increase N. The size of N required for the allowable error is appropriately determined by a person with ordinary knowledge in the field based on statistical inferences. [Embodiment 3]

Hereinafter, other embodiments of the present invention will be described. In addition, for convenience of description, members having the same functions as those described in the above-mentioned embodiments are given the same reference numerals, and the description thereof will not be repeated.

FIG. 14 is a circuit diagram showing the schematic configuration of the flash ADC 20 (analog device, AD converter) of this embodiment.

As shown in FIG. 14, the ADC 20 includes a sample-and-hold circuit 21, a comparator group 22, a switch matrix 23, an encoder 24, a voltage measurement circuit 25, a control device 26, and a switch element group 27.

The sample-and-hold circuit 21 maintains the input voltage V _in . The maintained input voltage V _{in is} applied to the comparator group 22.

The comparator group 22 includes M comparators Cp (the first comparator Cp ₁ to the _{M-th comparator Cp M} ), and each comparator Cp includes a plurality of fine MOSFETs. In each comparator Cp, one of the two input terminals is connected to the sample-and-hold circuit 21, and the other is grounded. In each comparator Cp, the output terminal is connected to the switch matrix 23 and also connected to the voltage measurement circuit 25 via the switching element group 27. In addition, in each comparator Cp, the circuit configuration is switched based on the configuration signal from the control device 26. In addition, the details of the comparator Cp will be described later.

The switch matrix 23 selects N-1 (N is a natural number smaller than M) from the M input signals from the comparator group 22 based on the switch signal from the control device 26, and outputs the rearranged to the encoder 24.

The encoder 24 encodes the N input signals from the switch matrix 23 and outputs them. Specifically, the encoder 24 detects the boundary between 0 and 1 for N-1 input signals, and performs encoding based on the detection result.

The voltage measuring circuit 25 measures the output voltage of each comparator Cp. The voltage measurement circuit 25 notifies the control device 26 of the measurement result.

The control device 26 controls the operation of the ADC 20. Specifically, the control device 26 receives the output voltage of each comparator Cp from the voltage measurement circuit 25. The control device 26 is configured to control the circuit configuration in each of the comparators Cp, the switch matrix 23, and the switch element group 27. (ADC action)

FIG. 15 is a flowchart showing an example of the operation of the ADC 20 shown in FIG. 14.

When the power is turned on, the control device 26 starts operating from the initial setting i=0 (step S41). The control device 26 first selects the i-th comparator (step S42), measures and records the voltage corresponding to the bias voltage as follows (step S43). Therefore, the control device 26 controls the switching element group 27 to be in the off state.

Fig. 16 is a circuit diagram showing a configuration example of the comparator Cp. The difference between the comparator Cp of this embodiment and the comparator used in the previous flash ADC is that the switching elements S ₁ to S ₃ are newly provided, and the other structures are the same.

The switching elements S ₁ to S _{3 are} controlled by the control device 26. Switching element S ₁ is provided between a voltage V _in the gate terminal of the FET32 and is input to the power supply voltage V _dd input. The switching element S _{2 is} provided between the gate terminal of the FET 33 to which the reference voltage V _{ref is input and the power supply voltage V dd} . The switching element S _{3 is} provided between the output terminals V _out ⁺ and V _out ^- . The output terminals V _out ⁺ and V _out ^{− are} connected to the voltage measurement circuit 25.

In the comparator Cp configured as described above, when the switching element S _{1 is} turned on and the switching elements S ₂ and S _{3 are} turned off, current flows through the FETs 33 and 35. At this time, the voltage measured by the voltage measuring circuit 25 (hereinafter referred to as the first measured voltage) becomes a function of the above-mentioned current, and exhibits the characteristics of the FETs 33 and 35.

Next, when the switching element S _{2 is} set to the on state, and the switching elements S ₁ and S _{3 are} set to the off state, current flows through the FETs 32 and 34. At this time, the voltage measured by the voltage measuring circuit 25 (hereinafter referred to as the second measured voltage) becomes a function of the above-mentioned current, and exhibits the characteristics of the FETs 32 and 34. Therefore, the difference between the first measurement voltage and the second measurement voltage becomes the voltage corresponding to the bias voltage of the comparator Cp. In addition, during the AD conversion operation, the switching elements S ₁ to S ₃ maintain the ON state.

15, the control device 26 increases i by 1 (step S44), and determines whether i<M is satisfied (step S45). If it is "Yes" in step S45, return to step S42.

If “No” in step S45, the control device 26 controls the switching element group 27 to be in an on state. On the other hand, the first comparator Cp _{1 is arranged in an ascending order (or descending order) with the recorded voltages.} The M-th comparator Cp _{M is} sorted (step S46). _{That is, the control device 2 sorts the first comparator Cp 1} to the M-th comparator Cp _M according to the ascending order (or descending order) of the above-mentioned voltage.

Next, the control device 26 selects N-1 comparators Cp from the M comparators Cp as follows (step S47).

Fig. 17 is a graph showing the distribution of the bias voltage of the comparator Cp. Since the comparator Cp is composed of a plurality of transistors, its bias voltage follows a normal distribution as shown in FIG. 17. Therefore, the sorted first comparator Cp ₁ ˜M-th comparator Cp _M can be made to correspond to the value of the bias voltage following the normal distribution. As a result, the control device 26 may select a particular voltage having N-1 interval and a bias voltage _{V offset1} ~ V offsetN _{- 1} corresponding to the N-1 comparators Cp. In addition, N depends on the bit number n of the output signal of the encoder 24, and is N=2 ⁿ .

Next, the control device 26 determines the configuration of the selected comparator Cp and the non-selected comparator Cp, generates a configuration signal indicating the determined configuration, and sends it to the comparator group 22 (step S48). In this case, the power consumption can be reduced by stopping the operation of the non-selected comparator Cp.

Next, the control unit 26 outputs the selected signal to the comparator Cp, the bias voltage by _{V offset1} ~ V offsetN _- arranged in the order of embodiment _1, a switching signal is generated and transmitted to the switch matrix 23 (step S49). Accordingly, the completion of the analog input voltage V _in preparation for the AD conversion of the digital signal of n bits, it starts the operation of the above-described AD conversion. (Effect)

As described above, in the ADC 20 of the present embodiment, as in Non-Patent Documents 1 and 2, the bias voltage follows the normal distribution, and the reference voltage is not supplied to the comparator Cp. Instead, the bias voltage is used. . Therefore, there is no need to increase the area of the comparator, and the increase in power consumption and manufacturing cost can be suppressed.

Furthermore, in the ADC 20 of this embodiment, based on the first measured voltage (output voltage) when one part of the plurality of FETs included in the comparator Cp stops operating, and the second when the other part of the plurality of FETs stops operating Measure the voltage difference and sequence the comparator Cp. Then, based on the normal distribution of the bias voltage and the order of the comparator Cp, the value of the bias voltage corresponds to the comparator Cp. Therefore, the bias voltage of each comparator Cp can be estimated. As a result, there is no need for a high-performance measuring device for measuring the above-mentioned bias voltage.

Thereby, N-1 comparators Cp can be used from the M comparators Cp, and the output signals of the N-1 comparators Cp can be rearranged in the order of the bias voltage by the switch matrix 23, and the encoder 24 Properly output n-bit digital signals. Therefore, compared with the ADCs of Non-Patent Documents 1 and 2, the ADC 20 of this embodiment adds a switch matrix 23. On the other hand, it does not require a Wallace tree decoder that uses many adders. The switch matrix 23 can be composed of a plurality of switch elements. Therefore, compared with the Wallace tree decoders of Non-Patent Documents 1 and 2, the switch matrix 23 and the encoder 24 of this embodiment can suppress the circuit scale. [Example 1]

The performance evaluation of the input and output characteristics and DNL (Differential Non-Linearity) of the ADC 20 of this embodiment is performed by simulation. The simulation is performed under the following conditions.・The comparator Cp has a bias voltage.・The bias voltage of the comparator Cp follows the normal distribution of expected value μ=0mV and standard deviation σ=90mV. · Input voltage V _in to -90mV ≦ V _in the range of ≦ 90mV.・The output is set to 6 bits.

The above-mentioned DNL is used as the index used in the performance evaluation of ADC. Used when the output code of the input voltage i Vi, and V _LSB-ideal input width when the ADC is over in = V _ref / 2 ^N, DNL is represented by the formula (12).

DNL[i]={(V _{i ＋ 1} －V _i )/(V _LSB-ideal )} －1 (0＜i＜2 ^N －1) (12).

That is, DNL represents the difference between the ideal value of the step width of a certain output code and the actual measured value, and the unit is expressed by LSB (Least Significant Bit), and is standardized with the minimum voltage value V _LSB-ideal that can detect the actual voltage value. (Input and output characteristics)

In the simulation, M=5000 comparators are generated as a whole, and 2 ⁶ -1=63 comparators Cp (N=64, n=6) are selected. For the selected comparator Cp, use the ADC20 shown in Figure 14 to calculate the DNL in the output code from 0 to 63. The results are shown in Fig. 18.

Figure 18 is a graph showing the relationship between the output code and DNL. Referring to FIG. 18, in this embodiment, -0.3<DNL<+0.3 is satisfied. Therefore, it can be understood that the ADC 20 functions well. (Mother Number of Comparator)

In addition, for each mother number (1000, 2000, 3000, 4000, 5000, 7000, 10000), DNL is executed every 300 times, and the relationship between the mother number of the comparator Cp and the DNL is investigated. The results are shown in Fig. 19.

Figure 19 is a graph showing the relationship between the number of mothers and DLN. In Figure 19, the maximum and minimum values of DNL are evaluated with ±3σ. When the absolute value of DNL is more than 1, a missing code will appear, so it is required to satisfy -1<DNL<+1. Referring to FIG. 19, it can be understood that if the number of mothers is more than 3000, -1<DNL<1 is satisfied, and no missing codes will appear. (Bias voltage of comparator)

FIG. 20 is a circuit diagram showing the schematic configuration of the comparator Cp in this embodiment. Regarding the comparator Cp shown in FIG. 20, the threshold voltage ΔV _{thp3 of the} transistor MP3 is changed, and the change in the _{offset voltage V offset is analyzed by HSPICE.} The analysis results are shown in Fig. 21. In addition, the analysis conditions are set as follows.・V _ref =0 ・V _in amplitude: 1mV ・CLK frequency: 1GHz ・Transistor (MOSFET) size: L=65nm, W=140nm ・Threshold voltage range: ΔV _thp3 ＝±40mV.

FIG. 21 is a graph showing the relationship between the _{threshold voltage ΔV thp3} and the offset voltage V _offset. If referring to FIG. 21, it can be understood that the threshold voltage ΔV _thp3 and the offset voltage V _{offset are} approximately in a linear relationship. Therefore, it is considered that if the deviation of the threshold voltage of the transistor MP3 follows the normal distribution, the bias voltage also follows the normal distribution. Moreover, it is expected that if the deviation of the threshold voltage of other transistors follows the normal distribution, the bias voltage also follows the normal distribution. (Necessary number of comparators)

Referring to Figure 17, it is understood as a first bias voltage V _offset1 N-1 and the second bias voltage _V offsetN _{- a} minimum density of probability. A comparator Cp N-1 enters the first bias voltage _V offsetN _- Probability of ₁ and the position error of the allowable range (2σ ± 0.1σ) represented by the following formula (13).

而且，以95%之概率在上述容許範圍內包含至少1個比較器Cp之必要數N的條件為N≧4/P。另外，第1偏置電壓V_offset1 之情形亦相同。[Number 12]

Furthermore, the condition that the necessary number N of at least one comparator Cp is included within the above allowable range with a probability of 95% is N≧4/P. In addition, the same _{applies to the first offset voltage V offset1.}

The probability shown in the above formula (13) depends on the standard deviation σ, and also depends on the position of the error and the allowable range. Therefore, the necessary number N of analog components may vary greatly depending on the target analog device. [Example 2]

FIG. 22 is a graph showing the distribution of the bias voltage of the comparator Cp in the ADC of this embodiment with vertical lines.

The performance evaluation of the input and output characteristics, DNL and INL (Integral Non-Linearity) of the ADC 20 of this embodiment is performed by simulation. The simulation is carried out under the following conditions.・The comparator Cp has a bias voltage.・The bias voltage of the comparator Cp follows the distribution function obtained by Monte Carlo analysis as described later. · Input voltage V _in to -90mV ≦ V _in the range of ≦ 90mV.・The output is set to 6 bits.

Regarding the bias voltage of the comparator Cp, the bias voltage of the comparator Cp follows the distribution function obtained as follows. 5,000 comparators Cp of the same configuration were fabricated in a 60nm manufacturing process, and the bias voltage of each comparator Cp was measured. Then, by Monte Carlo analysis, the distribution function of the bias voltage of the aforementioned comparator Cp is obtained. Therefore, in the simulation, the bias voltage of the comparator Cp is randomly selected from the distribution function obtained by Monte Carlo analysis.

The above-mentioned INL is used as another indicator used in the performance evaluation of the ADC. Using the output code when the input voltage V _i of i, and input to the ADC is over the width of the _{V LSB-ideal = V ref /} 2 N, INL represented by the following formula (14).

INL［i］={(V _{i ＋ 1} －V ₀ )/(V _LSB-ideal )}－i (0＜i＜2 ^N ) (14).

That is, INL represents the difference between the ideal input threshold of a certain output code and the measured input threshold. The unit is represented by LSB, and it is standardized by the minimum voltage value V _LSB-ideal that can detect the actual voltage value.

When following the normal distribution of expected value μ=0mV and standard deviation σ=90mV, the input and output characteristics of ADC20 theoretically satisfy -0.47<DNL<+0.53 and -1.23<INL<+1.24.

First, assume that the distribution of the bias voltage of the comparator Cp of the second embodiment shown in FIG. 22 follows the normal distribution, and the bias voltage is used as a reference for AD conversion. As a result of the AD conversion, the input and output characteristics of ADC20 satisfy -0.49<DNL<+0.80 and -1.85<INL<+0.44. The result is worse than the theoretical prediction. Therefore, it is estimated that the bias voltage of the comparator Cp of the second embodiment follows a distribution that is deformed compared to the above-mentioned normal distribution. For example, sometimes the above-mentioned bias voltage deviates from the normal distribution due to the nonlinearity of the transistor characteristics.

Next, find the β distribution that fits the distribution shown in Fig. 22. The beta distribution can show an asymmetric statistical distribution. Fig. 22 shows the calculated beta distribution as a curve.

Furthermore, assuming that the bias voltage of the comparator Cp of the second embodiment follows the above-mentioned β distribution, the bias voltage is used as a reference for AD conversion. As a result of the AD conversion, the input and output characteristics of the ADC 20 satisfy -0.62<DNL<+0.61 and -0.44<INL<+1.41. This result is better than the result when the normal distribution is used. Therefore, compared to using the normal distribution, using the β distribution can further improve the input and output characteristics of the ADC 20.

Therefore, it can be understood that the control device 26 exerts the best performance of the ADC 20 by selecting and using the most suitable statistical distribution among various statistical distributions. (Additional matters)

In addition, in the above embodiment, the voltage measurement circuit 25 and the control device 26 are provided inside the ADC 20, but they may also be provided outside the ADC 20. 〔Examples realized by software〕

The control blocks of the temperature sensor 1 and the ADC 20 (especially the control devices 2, 26) can be realized by a logic circuit (hardware) formed in an integrated circuit (IC chip) or the like, or can be realized by software.

In the latter case, the temperature sensor 1 is equipped with a computer that executes commands of software or programs for realizing each function. The computer has, for example, more than one processor and a computer-readable recording medium storing the above-mentioned program. Furthermore, in the above-mentioned computer, the above-mentioned processor reads and executes the above-mentioned program from the above-mentioned recording medium, thereby achieving the object of the present invention. As the aforementioned processor, for example, a CPU (Central Processing Unit) can be used. As the above-mentioned recording medium, a "non-transitory tangible medium" can be used. For example, in addition to ROM (Read Only Memory), magnetic tape, disc, card, semiconductor memory, programmable logic circuit, etc. can also be used. Moreover, it may be further equipped with RAM (Random Access Memory) which expands the above-mentioned program, etc. Moreover, the above-mentioned program can be supplied to the above-mentioned computer via any transmission medium (communication network or broadcasting, etc.) capable of transmitting the program. In addition, one aspect of the present invention can also be implemented in the form of a data signal embedded in a carrier wave in which the above-mentioned program is implemented by electronic transmission.

The present invention is not limited to the above-mentioned embodiments, and various modifications can be made within the scope shown in the claims. Embodiments obtained by appropriately combining the technical means disclosed in different embodiments are also included in the technical scope of the present invention.

For example, a control device provided outside the IC chip can be used to make an analog device equipped with a plurality of analog elements provided on the IC chip to control the value of the first characteristic corresponding to the analog element. In this case, there is no need for high-performance measuring equipment.

1: Temperature sensor (analog device, analog device corresponding system) 2: Control device 3: Switching section 4: Bias voltage generating circuit 5: Capacitor 6: Charging transistor 7: Inverting amplifier 8: TDC (measuring device) 9: Operation unit 10a, 10b: Volatile recording medium 11: Logic circuit 20: ADC (analog device, analog component corresponding system) 21: Sample and hold circuit 22: Comparator group (plural analog components) 23: Switch matrix 24: Encoder 25: Voltage measurement circuit (measuring device) 26: Control device 27: Switching element group 32, 33, 34, 35: FET Adjust-R ² : Adjusting the coefficient of determination of the degree of freedom Clock: Clock signal Cp ₁ ～Cp _M : the first comparator ~ the M- _{th comparator d 1} : the discharge time of the first reference transistor d ₂ : the discharge time of the second reference transistor I ₁ , I ₂ : the drain current I i: the current Mn ₁ , M _n1: a first transistor Mn _2, M _n2: the second transistor Mn _i, M _ni: i-th transistor Mn _j: j-th transistor Mn _N: N-transistor MP3: transistor S ₁ ~ S _N: first to N-th switching element switching element Tr: transistor group (a plurality of analog elements) V _b: bias voltage V _dd: voltage supply V _in: input voltage V _ref: reference voltage _{V th1, V th2, ΔV thp3} : the threshold voltage V _{th, ref1:} threshold first reference transistor's threshold voltage V _{th, ref2:} the threshold of the second reference transistor's threshold voltage _{V offset, V offset1 ~ V offsetN} - 1: bias voltage V _out: output voltage V _out ⁺ ,V _out ^－ : output terminal

Fig. 1 is a circuit diagram showing a schematic configuration of a temperature sensor according to an embodiment of the present invention. Fig. 2 is a circuit diagram showing a configuration example of a switching unit in the above-mentioned temperature sensor. Fig. 3 is a flowchart showing an example of the operation of the above-mentioned temperature sensor. Fig. 4 is a flowchart showing an example of a subroutine included in the above process. Fig. 5 is a circuit diagram for explaining the measuring principle of the above-mentioned temperature sensor. Fig. 6 is a graph showing an example of the voltage and current characteristics of the first and second transistors. FIG. 7 is a diagram showing the deviation of the threshold voltage in the analog transistor group of the above-mentioned temperature sensor. FIG. 8 is a graph showing the corresponding relationship between the temperature and the discharge time ratio in the temperature sensor of another embodiment of the present invention. FIG. 9 is a graph showing the relationship between the threshold voltage difference of the transistor in the temperature sensor and the determination coefficient of the adjusted degree of freedom. Fig. 10 is a graph showing the corresponding relationship between the temperature in the temperature sensor and the discharge time ratio. Fig. 11 is a graph showing the error of the calculated temperature in the above-mentioned temperature sensor. Fig. 12 is a circuit diagram showing a configuration example of the switching unit in the above-mentioned temperature sensor. Fig. 13 shows an equivalent circuit when the first transistor is connected to the capacitor in the above-mentioned switching section. Fig. 14 is a circuit diagram showing a schematic configuration of a flash ADC according to another embodiment of the present invention. Fig. 15 is a flowchart showing an example of the operation of the above-mentioned ADC. Fig. 16 is a circuit diagram showing a configuration example of the comparator in the ADC. Fig. 17 is a graph showing the distribution of the bias voltage of the above-mentioned comparator. Fig. 18 is a graph showing the relationship between the output code and DNL in an embodiment of the above-mentioned ADC. Fig. 19 is a graph showing the relationship between the mother number and DLN in the above embodiment. Fig. 20 is a circuit diagram showing the schematic configuration of the comparator in the above-mentioned embodiment. FIG. 21 is a graph showing the relationship between the threshold voltage of the transistor in the comparator and the bias voltage of the comparator. FIG. 22 is a graph showing the distribution of the bias voltage of the comparator in an embodiment of the above-mentioned ADC with vertical bars.

no

1: Temperature sensor (analog device, analog component corresponding system)

2: control device

3: Switching part

4: Bias voltage generating circuit

5: Capacitor

6: Transistor for charging

7: Inverting amplifier

8: TDC (determination device)

9: arithmetic unit

10a, 10b: Volatile recording media

11: Logic circuit

Clock: clock signal

Mn ₁ ~Mn _N : 1st transistor ~ Nth transistor

Tr: Transistor group (multiple analog components)

V _dd : power supply voltage

Claims (8)

An analog device, which is set on an IC chip, and: The above-mentioned analog device is provided with a plurality of analog elements that perform analog actions, and a control device that controls the actions of the analog device, Each of the above analog components has: The first characteristic, which is related to the action of the above-mentioned analog device, and the deviation follows a statistical distribution; and The second characteristic, which is related to the first characteristic and can be measured on chip; The above-mentioned control device is: Sequencing a plurality of the above-mentioned analog components according to the measured value of the second characteristic, and The value of the first characteristic corresponds to the analog element based on the statistical distribution related to the first characteristic and the order of the analog element. An analog device of claim 1, wherein the control device operates the analog element corresponding to the specific value of the first characteristic. For example, the analog device of claim 1 or 2, which is further equipped with a measuring device for measuring the second characteristic, The control device ranks the plurality of analog elements based on the measurement value of the second characteristic measured by the measurement device. Such as the analog device of claim 1 or 2, wherein the above-mentioned analog element is a transistor, The first characteristic of the above-mentioned analog element is the threshold voltage of the above-mentioned transistor, The second characteristic of the above-mentioned analog element is the second critical leakage current of the above-mentioned transistor. Such as the analog device of claim 1 or 2, wherein the above-mentioned analog element is a comparator, The first characteristic of the above-mentioned analog element is the bias voltage of the above-mentioned comparator, The second characteristic of the analog element is the difference between the output voltage when the operation of one part of the plurality of transistors included in the comparator is stopped and the output voltage when the operation of the other part of the plurality of transistors is stopped. A control method for an analog device. The analog device is set on an IC chip, and the analog device is provided with a plurality of analog elements that perform analog actions, each of the analog elements is related to the action of the analog device and the deviation follows a statistical distribution The first characteristic and the second characteristic that is related to the first characteristic and can be measured on the chip. The control method of the above-mentioned analog device includes the following steps: The step of sequencing a plurality of the above-mentioned analog components according to the measured value of the second characteristic; and The step of making the value of the first characteristic correspond to the analog component based on the statistical distribution related to the first characteristic and the order of the analog component. A temperature sensor, which is arranged on an IC chip and has: Capacitor A plurality of transistors are connected in parallel with the capacitor; A plurality of switching elements, which are arranged between the above-mentioned capacitor and each of the above-mentioned plurality of transistors; and A control device, which controls the plurality of switching elements; The control device is: For each of the plurality of transistors, measure the discharge time until the current from the capacitor is discharged to the transistor and the voltage of the capacitor drops to a specific voltage, and The ratio of at least two discharge times of the plurality of transistors is output as temperature information. A corresponding system of analog components, which has: A plurality of analog components are arranged on the IC chip and perform analog actions; and Control device, which controls the action of the analog element; Each of the above analog components has: The first feature, its deviation follows a statistical distribution; and The second characteristic, which is related to the first characteristic and can be measured on the wafer; The above-mentioned control device is: Sequencing a plurality of the above-mentioned analog components according to the measured value of the second characteristic, and The value of the first characteristic corresponds to the analog element based on the statistical distribution related to the first characteristic and the order of the analog element.

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