CN115096450A - Reading circuit with current mirror type input stage - Google Patents

Abstract

The invention relates to the field of reading circuits, and discloses a reading circuit taking a current mirror type as an input stage, which comprises a current mirror type input circuit arranged outside a chip, the current mirror type input circuit comprises a blind pixel branch circuit and a first branch circuit arranged in a mirror image mode with the blind pixel branch circuit, the grid electrode of a first PMOS transistor in the blind pixel branch circuit is connected with the grid electrode of a second PMOS transistor in the first branch circuit, the source electrode of the first NMOS transistor of the blind pixel branch circuit is grounded through a series blind pixel resistor, the blind pixel circuit also comprises a second branch circuit which is in mirror image with the input end of the basic pixel circuit, the gate of the second NMOS transistor of the first branch is connected to the gate of the third NMOS transistor of the second branch, and the grid electrode and the source electrode of the third PMOS transistor of the second branch circuit are respectively connected with the grid electrode and the source electrode of the fourth PMOS transistor of the basic pixel circuit. The invention solves the problem of limited area of a pixel level circuit by introducing a current mirror structure on the traditional electric bridge.

Description

Reading circuit with current mirror type input stage

Technical Field

The invention relates to the field of reading circuits, in particular to a reading circuit taking a current mirror type as an input stage.

Background

The infrared reading circuit is an important component of the infrared detector, and has the functions of providing bias voltage required by the detection pixels and sequentially outputting information of the detection array row by row and column by column. In the process of displaying an image through infrared radiation, the performance of the readout circuit plays a great role, and with the continuous development of the technology of the readout circuit, the integrated functions of the readout circuit are more and more, such as on-chip analog-to-digital conversion, on-chip non-uniformity correction and the like. The on-chip analog-to-digital conversion is divided into a chip level, a column level and a pixel level, and currently, an infrared reading circuit mostly adopts a column level analog-to-digital conversion channel to perform analog-to-digital conversion on array signals line by line. When the infrared readout circuit occupies too large area due to high precision or reduces the processing capacity of the circuit due to low power consumption, a compromise needs to be made on the practical application scenario. The infrared reading circuit generally comprises an input stage, an analog-to-digital conversion module and a latch module, and is gradually developed towards a pixel stage.

In the input stage of the traditional bridge, currents flowing through pixels and blind pixels are subtracted, so that the 'elimination and the reservation' are realized, and small current integral comparison reading due to the temperature change of the pixels can effectively read infrared signals, but the infrared signals are not suitable for application scenes requiring high integration level, because the column-level circuit cannot meet the application requirement of miniaturization due to low integration level along with the great reduction of the area of the pixels. Therefore, in an application scenario where the temperature gradient is large and miniaturization is required, it becomes important to develop research on the pixel-level input stage circuit.

Disclosure of Invention

In order to solve the problem that the area of a pixel-level circuit is limited, a unit circuit does not use a column-level traditional structure any more, and an input stage is split outside a chip.

The invention is realized by the following technical scheme:

a current mirror type reading circuit used as an input stage comprises a basic pixel circuit arranged on a chip and a current mirror type input circuit arranged outside the chip, the current mirror type input circuit comprises a blind pixel branch circuit and a first branch circuit arranged in a mirror image mode with the blind pixel branch circuit, the grid electrode of a first PMOS transistor in the blind pixel branch circuit is connected with the grid electrode of a second PMOS transistor in the first branch circuit, the source electrode of the first NMOS transistor of the blind pixel branch circuit is grounded through a series blind pixel resistor, the blind pixel circuit also comprises a second branch circuit which is in mirror image with the input end of the basic pixel circuit, the gate of the second NMOS transistor of the first branch is connected to the gate of the third NMOS transistor of the second branch, and the grid electrode and the source electrode of the third PMOS transistor of the second branch circuit are respectively connected with the grid electrode and the source electrode of the fourth PMOS transistor of the basic pixel circuit.

Preferably, the blind pixel branch circuit comprises a first PMOS transistor and a first NMOS transistor, a source of the first PMOS transistor is connected with a bias voltage through a series first resistor, and a drain of the first PMOS transistor is connected with a drain of the first NMOS transistor and a gate of the first NMOS transistor.

Preferably, the first branch circuit comprises a second PMOS transistor and a second NMOS transistor, a source of the second PMOS transistor is connected with the bias voltage through a second resistor connected in series, a drain of the second PMOS transistor is connected with a drain of the second NMOS transistor and a gate of the second NMOS transistor, and a source of the second NMOS transistor is grounded.

Preferably, the second branch circuit comprises a third PMOS transistor and a third NOMS transistor, a source of the third NMOS transistor is grounded, and a drain of the third NMOS transistor is connected to a drain of the third PMOS transistor and a gate of the third PMOS transistor, respectively.

Preferably, the basic pixel circuit comprises a pixel branch circuit, an integrating circuit and an A/D conversion module, the pixel branch circuit comprises a fourth PMOS transistor and a fourth NMOS transistor, a source electrode and a grid electrode of the fourth PMOS transistor are respectively connected with a source electrode and a grid electrode of the third PMOS transistor, a drain electrode of the fourth PMOS transistor is connected with a drain electrode of the fourth NMOS transistor and an inverted input end of the integrating circuit, a source electrode of the fourth NMOS transistor is grounded through a series pixel resistor, and a source electrode of the fourth NMOS transistor is connected with a drain electrode of the fourth NMOS transistor.

And optimally, the resistance values of the first resistor and the second resistor are 4 times of the resistance value of the blind element resistor.

For optimization, one A/D conversion module corresponds to four integrating circuits through control switches respectively, and each integrating circuit corresponds to one blind pixel branch circuit, one first branch circuit, one second branch circuit and one pixel branch circuit.

And optimally, the first NMOS transistor and the fourth NMOS transistor are manufactured by adopting a deep N-well process.

And optimally, the blind pixel resistor and the pixel resistor both adopt an MEMS process.

And optimally, the pixel resistor is a thermistor with a negative temperature coefficient.

Compared with the prior art, the invention has the following advantages and beneficial effects:

the current mirror structure is introduced to the traditional electric bridge, the temperature change is converted into the current change, the current change is provided for the subsequent signal processing, the methods of electric bridge balance, current copying, difference between the upper and lower parts and the like are utilized to serve as the input stage of the pixel-level reading circuit, the circuit has a performance reference value, is simple in structure and small in area, the problem that the area of the pixel-level circuit is limited is solved, and the circuit conforms to the principle that the current reading circuit develops towards the direction of the pixel level.

Drawings

In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the drawings that are required in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and that those skilled in the art may also derive other related drawings based on these drawings without inventive effort. In the drawings:

FIG. 1 is a circuit diagram of a sensing circuit with a current mirror as an input stage according to the present invention;

fig. 2 is a basic circuit architecture diagram of one pixel.

Reference numbers and corresponding part names in the drawings:

1-current mirror type input circuit and 2-basic pixel circuit.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to examples and accompanying drawings, and the exemplary embodiments and descriptions thereof are only used for explaining the present invention and are not meant to limit the present invention.

Examples

A reading circuit taking a current mirror type as an input stage comprises a basic pixel circuit 2 arranged on a chip and a current mirror type input circuit 1 arranged outside the chip, wherein the current mirror type input circuit 1 comprises a blind pixel branch, a first branch arranged with the blind pixel branch in a mirror mode, the grid electrode of a first PMOS transistor M1 in the blind pixel branch is connected with the grid electrode of a second PMOS transistor M2 of the first branch, the source electrode of a first NMOS transistor M3 of the blind pixel branch is grounded through a series blind pixel resistor Rb, the reading circuit also comprises a second branch which is in a mirror mode with the input end of the basic pixel circuit, the grid electrode of a second NMOS transistor M4 of the first branch is connected with the grid electrode of a third NMOS transistor M5 of the second branch, the grid electrode and the source electrode of a third PMOS transistor M6 of the second branch are respectively connected with the grid electrode and the source electrode of a fourth PMOS transistor M7 of the basic pixel circuit, that is, the gate of the third PMOS transistor M6 of the second branch is connected to the gate of the fourth PMOS transistor M7 of the basic pixel circuit, and the source of the third PMOS transistor M6 of the second branch is connected to the source of the fourth PMOS transistor M7 of the basic pixel circuit.

In this embodiment, the blind pixel branch includes a first PMOS transistor M1 and a first NMOS transistor M3, a source of the first PMOS transistor M1 is connected to the bias voltage Vsk through a series first resistor R1, and a drain of the first PMOS transistor M1 is connected to a drain of the first NMOS transistor M3 and a gate of the first NMOS transistor M3; the first branch comprises a second PMOS transistor M2 and a second NMOS transistor M4, the source of the second PMOS transistor M2 is connected with a bias voltage Vsk through a series second resistor R2, the drain of the second PMOS transistor M3 is connected with the drain of the second NMOS transistor M4 and the gate of the second NMOS transistor M4, and the source of the second NMOS transistor M4 is grounded; the second branch comprises a third PMOS transistor M6 and a third NOMS transistor M5, the source of the third NMOS transistor M5 is grounded, and the drain of the third NMOS transistor M5 is connected with the drain of the third PMOS transistor M6 and the gate of the third PMOS transistor M6 respectively; the basic pixel circuit comprises a pixel branch, an integrating circuit and an A/D conversion module, wherein the pixel branch comprises a fourth PMOS transistor M7 and a fourth NMOS transistor M8, the source electrode and the grid electrode of the fourth PMOS transistor M7 are respectively connected with the source electrode and the grid electrode of the third PMOS transistor, namely the source electrode of the fourth PMOS transistor M7 is connected with the source electrode of the third PMOS transistor, the grid electrode of the fourth PMOS transistor M7 is connected with the grid electrode of the third PMOS transistor, the drain electrode of the fourth PMOS transistor is connected with the drain electrode of the fourth NMOS transistor and the inverting input end of the integrating circuit, the source electrode of the fourth NMOS transistor is grounded through a pixel resistor connected in series, and the source electrode of the fourth NMOS transistor is connected with the drain electrode of the fourth NMOS transistor.

As shown in fig. 1, the current mirror input circuit 1 on the left is placed off-chip, and the basic picture element circuit 2 on the right is on-chip. A current mirror type input circuit is configured in one row of the whole pixel surface, namely, several current mirror type input circuits are arranged in rows corresponding to the array, and pixel branches, an integrating circuit and an A/D conversion module (an analog-to-digital converter) are arranged in a chip.

The first PMOS transistor M1 to the second NMOS transistor M4, the second NMOS transistor M4 to the third NMOS transistor M5, the third PMOS transistor M6 and the fourth PMOS transistor M7 form three pairs of basic current mirrors, and the same bias voltage V _sk 、V _eb The source and gate voltages of the first PMOS transistor M1 and the second PMOS transistor M2 are ensured to be the same,as can be known from the square law relationship, the currents of the first branch and the blind pixel branch are equal, so that the current of the blind pixel branch is transferred to the third NMOS transistor M5 through the second NMOS transistor M4, and since the third NMOS transistor M5 and the third PMOS transistor M6 are on the same branch (on the second branch), the current transferred from the blind pixel branch keeps 1 again in the manner of the current mirrors of the third PMOS transistor M6 to the fourth PMOS transistor M7: 1. When no input signal exists outside, the blind pixel current (the current flowing through the blind pixel resistor Rb) is equal to the pixel current flowing through the pixel resistor Rs, and the output obtained theoretically is zero; when an input signal exists outside (the input signal has a variable quantity which is the resistance value change of Rs caused by the environmental temperature change), at the drain end nodes of the fourth PMOS transistor M7 and the fourth NMOS transistor M8, the current of the blind pixel branch and the current of the pixel branch are differentiated, and the difference appears as the current flowing into or flowing out of the CTIA (in a circuit diagram, the operational amplifier connected with a capacitor is used, the CTIA is a capacitor feedback trans-impedance amplifier, and is a reset integrator formed by an operational amplifier and a feedback integrating capacitor). The pixel resistor Rs is a thermistor with a negative temperature coefficient, and if the ambient temperature rises, according to the characteristic that the temperature coefficient of the pixel resistor Rs is negative, the resistance value of the pixel resistor Rs is reduced, which means that the current of a pixel branch is increased, namely the current is pumped into the CTIA and is integrated upwards, namely the output integration voltage of the CTIA is higher than the reference voltage of an integration circuit, if the ambient temperature is reduced, the output integration voltage is opposite, namely the integration voltage of the CTIA is lower than the reference voltage of the CTIA, finally, the obtained integration result is input into the A/D conversion module to be compared with a ramp signal, a switching signal is generated after comparison to enable a latch to store, then the switching signal is digitized into a Gray code with a low error rate, and then, the binary conversion is carried out according to needs. The basic circuit architecture of one pixel is shown in fig. 2 below.

In particular, the bias voltage V _sk Given a supply voltage greater than the supply voltage (on-chip, the value of the supply voltage given outside the picture element), ensures almost "lossless" supply voltage (since the bias voltage, given otherwise, is less susceptible to interference from the supply voltage and reaches the defined Veb voltage point even via a MOS transistorThe consumed micro voltage has no great influence), and the voltage passes through a quadruple blind element resistor (a first resistor, a second resistor, the resistance values of the first resistor and the second resistor and the bias voltage V) _sk Related to the size of (c), V _eb (this voltage is shorthand for a bias voltage for the infrared balance bridge.) the DC bias, V, is provided by an off-chip source follower (a circuit structure providing a bias voltage in a bias module in the off-pixel chip) _fid And generating direct current bias to the pixel resistor in a drain-source short circuit mode. The sensor made by the MEMS technology has the main advantages of small volume, light weight, low power consumption, high reliability, high sensitivity, easy integration, low manufacturing cost after equipartition and the like, and is the main force of the micro sensor.

The gates between the first PMOS transistor M1 and the second PMOS transistor M2 are all off-chip V _eb And providing a bias voltage, wherein under the condition that the current of the blind pixel branch is determined, the connection relation of the two ends of the grid source determines that the currents flowing through the first PMOS transistor and the second PMOS transistor are the same, namely the current of the second branch is determined.

The second NMOS transistor M4 and the third NMOS transistor M5 serve as an intermediate "carrier" for transferring the blind pixel current, and the matching degree determines the accuracy of the replica current, so the parameter channel length L of the second NMOS transistor and the third NMOS transistor needs to be designed to be slightly larger (by fine-tuning the width-to-length ratio, when L is about 4 times of the minimum line width, the influence of channel modulation is not large, and the current can be replicated more accurately), and the coordination of the second NMOS transistor M4 and the third NMOS transistor M5 in the same branch is fully considered (the coordination refers to the fact that the branch currents on both sides of M1 to M4 are equal and are symmetrical in a certain sense, so that the accurate replication of the current mirror is important, not only to avoid channel modulation). By doing so, not only can channel modulation effects be avoided as much as possible, but also certain benefits can be achieved in reducing noise.

The first NMOS transistor M3 and the fourth NMOS transistor M8 are biased in a manner of a short-circuited gate-drain diode, and the gate voltages of the first NMOS transistor M3 and the fourth NMOS transistor M8 are the same, which means that the bias voltages of the blind pixel resistor and the pixel resistor are regulated by the drain voltage of the first PMOS transistor M1 and the blind pixel branch current. In addition, the first NMOS transistor M3 and the fourth NMOS transistor M8 are connection points for "communication" between the dummy resistor and the pixel resistor, and therefore are more sensitive to noise on the substrate of the NMOS transistor, and the noise requirement is more strict, so the first NMOS transistor M3 and the fourth NMOS transistor M8 need to adopt Deep N-Well (Deep N-Well process) for isolation to reduce noise.

From the above analysis, M ₃ 、M ₄ 、M ₆ The size of the circuit is very critical, because the sizes of M6 and M7 are the same, the voltage of M7, M8 and pixels on the AVDD of the branch is very critical to ensure the balance (no input and zero output), the voltages of drain ends of M7 and M8 are very critical, M7 needs to occupy a bigger Vgs, therefore, the width and length are smaller and need to be longer than the width, M8 does not need to be the same as M3, and the circuit can be matched with the M3 to determine the accuracy of signal reading, is equivalent to a current path, and is influenced by multiple factors such as power consumption, size, bias current, noise and the like.

The blind pixel current of the traditional structure is only influenced by the MOS transistor with fixed bias voltage and the blind pixel resistor, in the novel current mirror structure, the blind pixel branch and the pixel branch can be mutually influenced after the size is designed, and the aim is to increase the coordination of the circuit and reduce the error between the blind pixel and the pixel. Compared with the traditional structure in which the blind element resistor and the pixel resistor adopt fixed bias voltage, the self-adaptive flexibility is enhanced, the bias voltage of Veb and Vfrid influences the current which influences the bias voltage, and the error between the current and the bias voltage can be offset back and forth in the work of the structure of the invention.

When the environment temperature changes, the pixel resistance and the blind pixel resistance have a coefficient (the mismatch and the resistance value caused by the temperature change are different) alpha relation:

R _s ＝R _b ·(1+α)

suppose each MOS transistor is operated in the saturation region and V _gs (the first equation below is for M1, the second for M3) are nearly equal, then:

V _eb ＝V _sk -4·I _b ·R _b -V _gs1

V _fid ＝I _b ·R _b +V _gs3

I _b -I _s ＝1/2·μ ₁ C _ox (W/L) ₁ (V _eb -V _sk +4·I _b ·R _b -V _TH1 ) ² -1/2·μ ₈ C _ox (W/L) ₈ (V _fid -I _s ·R _s -V _TH8 ) ²

wherein, I _b Indicating the flow of the current through the blind cell resistor R _b Current of blind cell of (I) _s Representing the current flowing through the pixel resistance R _s Pixel current of (d), mu ₁ 、μ ₈ Respectively corresponding to the mobility of electrons and holes in the first PMOS transistor M1 and the fourth NMOS transistor M8, W/L represents the width-to-length ratio of the lower-corner corresponding MOS, V _eb 、V _fid Denotes a given bias voltage, V _TH1 、V _TH8 Each represents the threshold voltage of the first PMOS transistor M1 and the fourth NMOS transistor M8.

The mobility of the substituted NMOS is about twice that of the PMOS (the multiple of the mobility represents an estimated or ubiquitous rule, and there is a very slight change due to differences in process, temperature, etc.), and the absolute values of the thresholds are approximately equal, then:

I _b -I _s ＝μ ₁ /2·C _ox [(W/L) ₁ (V _eb -V _sk -V _TH1 +4·I _b ·R _b ) ² -2(W/L) ₈ (V _fid -V _TH8 -I _s ·(1+α)·R _b ) ² ]

again, as evidenced by the simple derivation of the above formula, V _eb 、V _fid Bias influencing current I _b 、I _s The current affects the bias voltage, so that a more accurate reference is provided for the fixed blind element resistance bias voltage, and the self-adjusting pixel resistance bias voltage has a certain positive effect on the adaptation of the blind element resistance and the pixel resistance, so that the noise and the mismatch rate are reduced.

The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are merely exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims (10)

1. A current mirror type reading circuit as an input stage comprises a basic pixel circuit arranged in a chip, it is characterized by also comprising a current mirror type input circuit arranged outside the chip, wherein the current mirror type input circuit comprises a blind pixel branch and a first branch arranged in a mirror image with the blind pixel branch, the grid electrode of a first PMOS transistor in the blind pixel branch circuit is connected with the grid electrode of a second PMOS transistor in the first branch circuit, the source electrode of the first NMOS transistor of the blind pixel branch circuit is grounded through a series blind pixel resistor, the blind pixel circuit also comprises a second branch circuit which is in mirror image with the input end of the basic pixel circuit, the gate of the second NMOS transistor of the first branch is connected to the gate of the third NMOS transistor of the second branch, and the grid electrode and the source electrode of the third PMOS transistor of the second branch circuit are respectively connected with the grid electrode and the source electrode of the fourth PMOS transistor of the basic pixel circuit.

2. A current-mirror input stage readout circuit according to claim 1, wherein the blind-cell branch comprises a first PMOS transistor and a first NMOS transistor, the source of the first PMOS transistor being connected to the bias voltage via a series first resistor, and the drain of the first PMOS transistor being connected to the drain of the first NMOS transistor and to the gate of the first NMOS transistor.

3. A current-mirror input stage readout circuit according to claim 2, wherein the first branch comprises a second PMOS transistor and a second NMOS transistor, the source of the second PMOS transistor being connected to the bias voltage via a second resistor in series, the drain of the second PMOS transistor being connected to the drain of the second NMOS transistor and to the gate of the second NMOS transistor, the source of the second NMOS transistor being connected to ground.

4. A current-mirror input stage readout circuit according to claim 3, wherein the second branch comprises a third PMOS transistor and a third NOMS transistor, the source of the third NMOS transistor is connected to ground, and the drain of the third NMOS transistor is connected to the drain of the third PMOS transistor and the gate of the third PMOS transistor, respectively.

5. The current mirror type input stage readout circuit according to claim 4, wherein the basic pixel circuit comprises a pixel branch, an integrating circuit and an A/D conversion module, the pixel branch comprises a fourth PMOS transistor and a fourth NMOS transistor, a source and a gate of the fourth PMOS transistor are respectively connected to a source and a gate of the third PMOS transistor, a drain of the fourth PMOS transistor is connected to a drain of the fourth NMOS transistor and an inverting input terminal of the integrating circuit, a source of the fourth NMOS transistor is connected to ground through a series pixel resistor, and a source of the fourth NMOS transistor is connected to a drain of the fourth NMOS transistor.

6. The current mirror input stage readout circuit of claim 5, wherein the first resistor and the second resistor have a resistance value 4 times that of the blind-cell resistor.

7. The current mirror type input stage sensing circuit of claim 5, wherein one A/D conversion module corresponds to four integration circuits through control switches, and each integration circuit corresponds to one blind pixel branch, one first branch circuit, one second branch circuit and one pixel branch circuit.

8. The current-mirror input stage readout circuit of claim 7, wherein the first and fourth NMOS transistors are formed by a deep N-well process.

9. The sensing circuit of claim 6, wherein the blind-cell resistor and the pixel resistor are both formed by MEMS process.

10. The current-mirror input stage readout circuit according to claim 5, wherein the pixel resistor is a negative temperature coefficient thermistor.

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