CN101043215A - High-performance time-digital converter circuit structure - Google Patents
High-performance time-digital converter circuit structure Download PDFInfo
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- CN101043215A CN101043215A CNA2007100379770A CN200710037977A CN101043215A CN 101043215 A CN101043215 A CN 101043215A CN A2007100379770 A CNA2007100379770 A CN A2007100379770A CN 200710037977 A CN200710037977 A CN 200710037977A CN 101043215 A CN101043215 A CN 101043215A
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- G04—HOROLOGY
- G04F—TIME-INTERVAL MEASURING
- G04F10/00—Apparatus for measuring unknown time intervals by electric means
- G04F10/005—Time-to-digital converters [TDC]
Abstract
The invention discloses a high performance time digital converter circuit frame, it includes time-delay chain loop which generates low bit data, counter which generates high bit data and a compensating control source; said time-delay chain loop counts the low bit and transfers to said counter in definite period, said counter accumulates the signal with definite period to be the high bit of the time digital converter; Said compensating control source compensates and controls the voltage signal of said time-delay chain loop; The precision is high; the minimum time distinguishing ratio is the one class buffer transmission delay; the speed of processing is quick, when the counting ends, data is obtained, without additional processing time; the output of flip-latch is connected with high bit counter, it guarantees the correctness of circulation and carry; the compensating control source is introduced to guarantee the consistency of system under the same temperature, voltage, craft; the requirement for every module is not high, so it is easy to realize.
Description
Technical field
The present invention relates to a kind of circuit framework, particularly a kind of high-performance time-digital converter circuit structure that is converted to digital signal the time interval.
Background technology
So-called TDC (Time-to-Digital Converters) is the time digital quantizer, is a kind of timer that is converted to digital signal the time interval.
The most basic time-to-digit converter is to utilize a counter in time range to be measured, and pulse is counted to string number; Although existing oscillator counting can be realized stable high-speed pulse, thing followed power consumption and noise are difficult to accept.Real efficient ways is to utilize lower toggle rate to carry out big time measurement, and the part-time of not enough this timing time one-period is done special processing, realizes accurately measuring.
For this accurate measurement that needs special processing, common several clocking methods are as follows:
Capacitance voltage method: in part scope to be measured, utilize an electric current that electric capacity is charged, be full of the back discharge, the cycle of discharging and recharging is designated as one-period, less than the time of one-period, difference utilizes an analog to digital converter ADC that this voltage is transferred to digital quantity to capacitance voltage again with this charging interval, can realize the accurate measurement less than one-period; The weak point of this method is to need a high-precision analog to digital converter ADC, and this analog to digital converter ADC design itself needs the consideration of a series of complexity; The linearity that guarantees capacitance voltage also is a difficult point, and this charging current is disturbed by external condition also easily simultaneously.
Time stretching method: a kind of method above similar, difference is, when the time to be measured finishes, utilize one than the much smaller rated current of charging current to capacitor discharge, till only dropping to the charging starting voltage, in discharge process, utilize counter to measure the time that this is exaggerated many times to capacitance voltage; Though this scheme goes up a scheme relatively and is improved, in order to obtain higher precision, need charging current bigger a lot of times than discharging current, in order to make this ratio enough big, need discharging current very little, charging current is very big.And too little discharging current is interfered easily, and excessive charging current is also unrealistic.After the timing period finishes, also need a special processing time that electric capacity is slowly discharged, can't realize continuous time figure conversion.
The vernier caliper method: basic principle is to produce three group pulse waveforms, one group of reference pulse, two groups of trigger impulses, but two groups of trigger impulse cycles identically minute differences is arranged with the reference pulse cycle, three counters calculate three group pulse numbers respectively; After initial pulse began, initial counter calculated the number of initial pulse, when initial pulse and reference pulse are overlapping, stopped to count; Similarly, end counter calculate to finish pulse and begins to the number when overlapping with reference pulse, and reference count is calculated the beginning pulse and finished the reference pulse number of pulse between beginning; The resolution of this method is by the periodic inequality decision of two kinds of pulses, weak point is, what need very high differential phase difference sees the phase device, after the timing period finishes, also need the extra time to wait and finish pulse and reference pulse coincidence, can't realize digital translation continuous time.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of high-performance time-digital converter circuit structure, adopts digital method, utilizes the time-delay of CMOS gate leve to do minimum time of day, accuracy of timekeeping height.
Technical problem to be solved by this invention can be achieved through the following technical solutions:
A kind of high-performance time-digital converter circuit structure is characterized in that, it comprises the time delay chain loop that produces low data, counter and compensating control source that produces high position data; Carried out the low level counting and given described counter with this signal with specific periodic transfer by described time delay chain loop, described counter adds up to the signal time in this specific cycle, as the high position of time-to-digit converter; Described compensating control source compensates, controls the voltage signal of described time delay chain loop.
Described time delay chain loop is made of delay unit loop, comparator, latch, encoder and initialization unit; Initial signal STA makes the conducting of described delay unit loop by described initialization unit, and described delay unit loop is converted to digital signal by comparator, and by latch output, the afterbody latch is exported as carry signal; End signal END makes data latching that described latch will this moment and latched data is transferred to encoder, by encoder with data transaction and as the low level output of time-to-digit converter.
Described delay unit loop is connected and composed by some fully differential buffers, and described afterbody buffer is connected with first order buffer is anti-phase, and remaining every grade buffer is connected together with back first-level buffer device.
Described buffer is made of P-channel field-effect transistor (PEFT) pipe, signaling switch EN, metal-oxide-semiconductor MP1, MP2, MN1, MN2, MN3, MN4; The source electrode of metal-oxide-semiconductor MN1, MN2, MN3, MN4 is connected to each other, then ground connection; The grid of metal-oxide-semiconductor MN1, MN3 is connected to each other, and connects the drain electrode of metal-oxide-semiconductor MN2, MN3 then successively, meets output OUT-, and the grid of metal-oxide-semiconductor MN2, MN4 is connected to each other, and connects the drain electrode of metal-oxide-semiconductor MN4, MN1 then successively, meets output OUT+; Supply voltage VDD connects the source electrode of P-channel field-effect transistor (PEFT) pipe, the voltage signal V of compensating control source
BPInsert the grid of P-channel field-effect transistor (PEFT) pipe, the drain electrode of P-channel field-effect transistor (PEFT) pipe is connected respectively to the source electrode of metal-oxide-semiconductor MP1, MP2 by signaling switch EN, the drain electrode of metal-oxide-semiconductor MP1, MP2 meets output OUT-and output OUT+ respectively, the grid of metal-oxide-semiconductor MP1, MP2 meets input IN+, IN-respectively, form the fully differential structure of both-end input both-end output, delay time by the voltage-controlled current source control transmission.
The described counter ripple counter that several d type flip flops constitute of serving as reasons is counted the carry signal that the time delay chain loop provides, as the high position output of time-to-digit converter.
Described control compensation source comprises low drop out voltage regurator LDO, current source buffer, PMOS current mirror, NMOS current mirror, bias voltage efferent duct and current setting resistance; Described low drop out voltage regurator LDO connects PMOS current mirror, current source buffer, NMOS current mirror and current setting resistance successively, and internal work voltage AVDD and a series of reference voltage are provided; Described current source buffer and current setting resistance are connected to each other, and effect produces the original reference electric current, behind PMOS current mirror and NMOS current mirror mirror image, by bias voltage efferent duct output voltage signal V
BP
Be provided with the PMOS compensating pipe with shunting action between described PMOS current mirror and low drop out voltage regurator LDO, its grid connects low drop out voltage regurator LDO, and drain electrode connects the PMOS current mirror.
Be provided with the NMOS compensating pipe with shunting action between described NMOS current mirror and low drop out voltage regurator LDO, its grid connects low drop out voltage regurator LDO, and drain electrode connects the NMOS current mirror.
The supply voltage of described bias voltage efferent duct meets supply voltage VDD.
Described low drop out voltage regurator LDO is made of a reference source BANDGAP, error amplifier, efferent duct and divider resistance; The termination of a reference source BANDGAP is gone into the negative pole of error amplifier input, the other end inserts the current source buffer, the positive pole of error amplifier input inserts between the divider resistance, the grid of error amplifier output termination efferent duct, the drain electrode of efferent duct connects divider resistance successively, carries out dividing potential drop and output.
Principle of the present invention is as follows:
Realize the low level counting by the time delay chain loop, its core is made of the individual buffer of n (n is a positive integer), every grade of buffer has a transmission delay time Δ t, realized that through each buffer behind the 2n Δ t upset of one-period gets back to the state before the 2n Δ t, its period T=2n Δ t, the dateout of buffer is by latches; The carry end of low counter is exported to high-positioned counter by the data latching of afterbody buffer, low counter operation one-period high-positioned counter counting adds up 1, the latch data carry of afterbody buffer, can guarantee that in that time that stops to count the circulation and the carry of low data are mated.
The cycle that counter is sent here the time delay chain loop is that the signal of T is counted, and each time T counter adds up 1, as the high position of time-to-digit converter TDC; Time T is the 2n doubly (n is a time delay chain loop progression) of least count precision Δ t, chooses suitable n, guarantees that counter can be that the signal of T is made correct counting to the cycle; Last position of high-positioned counter be an overflow position, and when counter meter during to a last bit flipping, i.e. expression is counted and gone beyond the scope.
Time delay chain loop for the cmos circuit realization, the transmission delay Δ t of each grade buffer can change when external condition changes, the external environment condition variation mainly contains variations in temperature, process deviation during the mains voltage variations one-level is manufactured, under the effect of compensating control source, the fluctuation range of Δ t is dwindled greatly, makes time-to-digit converter TDC reading that good consistency be arranged under various conditions.
A kind of high-performance time-digital converter circuit structure of the present invention has following advantage:
1, accuracy of timekeeping height, minimum time resolution are first-level buffer device transmission delay.
2, processing speed is fast, and timing finishes, and data in real time produces, and need not the extra process time.
3, connect high-positioned counter by latch output, guaranteed the correctness of circulation and carry.
4, introduce compensating control source, guarantee at all temps voltage, the consistency of system under the deviations such as technology.
5, less demanding to each module of built-up circuit, be easy to realize.
Description of drawings
Further specify the present invention below in conjunction with the drawings and specific embodiments.
Fig. 1 is a theory diagram of the present invention;
Fig. 2 is the circuit theory diagrams of the time delay chain loop among the present invention;
Fig. 3 is the timing waveform of the time delay chain loop among the present invention;
Fig. 4 is the circuit theory diagrams of the buffer among the present invention;
Fig. 5 is the circuit theory diagrams of the counter among the present invention;
Fig. 6 is the timing waveform of the counter among the present invention;
Fig. 7 is the circuit theory diagrams of the compensation source circuit among the present invention.
Embodiment
As shown in Figure 1, a kind of high-performance time-digital converter circuit structure, it comprises the time delay chain loop (10) that produces low data, a counter (20) and a compensating control source (30) that produces high position data.
As shown in Figure 2, time delay chain loop (10) is by delay unit loop (101), one group of comparator (102), and one group of latch (103), encoder (104) and initialization unit (105) constitute.
Delay unit loop (10) is made of the individual buffer Buffer of n (n is a positive integer), each buffer Buffer has positive and negative two differential input ends and positive and negative two difference output ends, the in-phase end of every grade of buffer Buffer and next stage buffer Buffer links to each other, the negative input end of the positive output termination first order buffer Buffer of afterbody buffer Buffer, the positive input terminal of negative output termination first order buffer Buffer is realized anti-phase; The output of every grade of buffer Buffer becomes double-end signal into single-ended signal through latch Latch output by a comparator C OMP, afterbody latch Latch output carry signal is as carry termination high-positioned counter (20), and latch Latch exports after encoded device (104) encoding process low level as time-to-digit converter TDC.
During initial condition, after time-to-digit converter TDC enabled, first order buffer Buffer was in off-state, i.e. input can't be transmitted to output; On adopting one, initialization unit (105) draws the simple structure of a P pipe and a drop-down N pipe, to the set of first order buffer Buffer output signal, for example anode is put electronegative potential, negative terminal is put high potential, because other buffer Buffer at different levels are conductings, differential signal can conduct down always, and this moment, all comparator C OMP were output as electronegative potential (being designated as 0).
After initial signal STA provided, initialization unit (105) was closed, first order buffer Buffer conducting; Because the input of the signal of afterbody buffer Buffer output reversal connection first order buffer Buffer, through one-level transmission delay time Δ t, first order output switching activity, first order comparator C OMP is output as high potential (being designated as 1), pass through one-level transmission delay time Δ t again, second level output switching activity; By that analogy, the transmission delay sequential as shown in Figure 3.Comparator C OMP is through latch Latch output, and latch Latch output variation in time sees the following form.
| Time | b1b2b3b4……b(n-1)bn |
| 0 | 0000……00 |
| Δt | 1000……00 |
| 2Δt | 1100……00 |
| …… | …… |
| nΔt | 1111……11 |
| (n+1)Δt | 0111……11 |
| …… | …… |
| (2n-1)Δt | 0000……01 |
| 2nΔt | 0000……00 |
After end signal END provided, the data in this moment were latched device Latch and latch, and end signal END signal is transferred among the latch Latch at different levels with the form of clock trees, guaranteed that all latch Latch are at the synchronization latch data.
As shown in Figure 4, buffer Buffer is made of P-channel field-effect transistor (PEFT) pipe, signaling switch EN, metal-oxide-semiconductor MP1, MP2, MN1, MN2, MN3, MN4; Supply voltage VDD connects the source electrode of P-channel field-effect transistor (PEFT) pipe, the voltage signal VBP of compensating control source inserts the grid of P-channel field-effect transistor (PEFT) pipe, the drain electrode of P-channel field-effect transistor (PEFT) pipe is connected respectively to the source electrode of metal-oxide-semiconductor MP1, MP2 by signaling switch EN, the drain electrode of metal-oxide-semiconductor MP1, MP2 meets output OUT-and output OUT+ respectively, and the grid of metal-oxide-semiconductor MP1, MP2 meets input IN+, IN-respectively; Adopting the input of P-channel field-effect transistor (PEFT) pipe, is because the P-channel field-effect transistor (PEFT) pipe can be accomplished in the independent well, reduces its interference of outer bound pair.Higher precision needs littler transmission delay, for littler power consumption realizes littler transmission delay, the metal-oxide-semiconductor size is got little as far as possible, in this high speed circuit, depend primarily on gate capacitance the flip-flop transition of metal-oxide-semiconductor and discharge and recharge the equivalent RC time-delay on the metal wire in time of threshold voltage and the domain, littler metal-oxide-semiconductor has been realized littler gate capacitance, and shorter thinner line is realized littler RC time-delay, thereby realizes littler transmission delay; The source electrode of metal-oxide-semiconductor MN1, MN2, MN3, MN4 is connected to each other, then ground connection; The grid of metal-oxide-semiconductor MN1, MN3 is connected to each other, and connects the drain electrode of metal-oxide-semiconductor MN2, MN3 then successively, meets output OUT-, and the grid of metal-oxide-semiconductor MN2, MN4 is connected to each other, and connects the drain electrode of metal-oxide-semiconductor MN4, MN1 then successively, meets output OUT+; Form the fully differential structure of both-end input both-end output.Voltage-controlled current source converts bias voltage to electric current, the control transmission time-delay.Differential configuration can reduce common mode disturbances on the one hand, can select homophase transmission or anti-phase transmission on the other hand, and by signaling switch EN control MOS switch, before STA provided, this switch of the first order disconnected other these switch closures at different levels.
Comparator C OMP is common hysteresis comparator, needs fast speeds, need consider in the time of design with less size and bigger electric current.
Latch Latch is half of principal and subordinate's d type flip flop, and operate as normal is in conducting state, and output equals input.When latch signal arrives (being the END signal here), this input signal constantly is locked in the inverter loop, no matter imports how saltus step, and output no longer changes.
The effect of encoder is that the data transaction that will be latched into becomes binary coding, advises that this progression gets 2 k power, and coding output then is the k+1 position like this.With k=3 is example, and at this moment n=8 has 8 grades of delay units.Coding sees the following form.
| Time | b1b2b3b4 b5b6b7b8 | Coding output |
| 0 | 00000000 | 0000 |
| Δt | 10000000 | 0001 |
| 2Δt | 11000000 | 0010 |
| 3Δt | 11100000 | 0011 |
| 4Δt | 11110000 | 0100 |
| 5Δt | 11111000 | 0101 |
| 6Δt | 11111100 | 0110 |
| 7Δt | 11111110 | 0111 |
| 8Δt | 11111111 | 1000 |
| 9Δt | 01111111 | 1001 |
| 10Δt | 00111111 | 1010 |
| 11Δt | 00011111 | 1011 |
| 12Δt | 00001111 | 1100 |
| 13Δt | 00000111 | 1101 |
| 14Δt | 00000011 | 1110 |
| 15Δt | 00000001 | 1111 |
| 16Δt | 00000000 | 0000 carry |
As shown in Figure 5, counter (20) is by the individual ripple counter that constitutes along the d type flip flop that triggers of jumping down of m (m is a positive integer).When afterbody buffer Buffer output bn jumps to 0 through one-period by 1 among Fig. 2, carry signal carry provides one and jumps the edge down, the first order Qk+1 redirect of ripple counter, when Qk+1 jumps to 0 through one-period by 1, second level Qk+2 redirect, by that analogy, the cycle of carry is counted, its sequential as shown in Figure 6.
When ripple counter highest order Qk+m jumps to 0 by 1, m+1 d type flip flop effect, OF is output as 1 expression and exceeds count range.
D type flip flop Dff is common principal and subordinate's d type flip flop, and following jumping is along triggering, and this connected mode is when previous stage saltus step one-period, and back one-level saltus step half period realizes binary counting.Here do not giving unnecessary details its structure.
The high bit timer that the low bit timer sum counter (20) that is made of delay unit loop (10) constitutes can be good at finishing the function of a time-to-digit converter, but along with the outer power voltage fluctuation, variations in temperature and process deviation, at the time-to-digit converter TDC reading of a set time section also will one in a big way in fluctuation.
Causing the reading fluctuation mainly is the time-delay fluctuation of delay unit loop (101).Because what each delay unit loop (101) adopted is a kind of voltage-controlled current source control, at emulation under the constant current conditions (not with temperature, voltage, the electric current of technological fluctuation) we know that time delay chain loop (10) mainly is with the fluctuation of metal-oxide-semiconductor model, and are subjected to temperature and mains fluctuations very little.To a set time section simulation time digital quantizer TDC reading, (N manages at a slow speed at FF (quick N pipe, P pipe fast, a kind of extreme process corner) and SS, P pipe at a slow speed, another extreme process corner) the time-to-digit converter TDC reading that obtains under is than the deviation nearly 20% of TT (typical case).The FF reading is more than TT 20%, and the SS reading is less than TT 20%.So we need such compensating control source, at first it is a constant-current source, and it can reduce electric current under the situation of FF simultaneously, and increases electric current under the SS situation.
As shown in Figure 7, compensating control source (30) comprises low drop out voltage regurator LDO (301), current source buffer (302), PMOS compensating pipe (303), NMOS compensating pipe (304), PMOS current mirror (305), NMOS current mirror (306), bias voltage efferent duct (307) and current setting resistance (308).Low drop out voltage regurator LDO (301) connects PMOS compensating pipe (303), PMOS current mirror (305), current source buffer (302), NMOS compensating pipe (304), NMOS current mirror (306) and current setting resistance (308) successively.
Low drop out voltage regurator LDO (301) produces zero-temperature coefficient voltage V by one
BGA reference source BANDGAP, error amplifier, efferent duct and divider resistance constitute.Low drop out voltage regurator LDO (301) will produce an internal work voltage AVDD and a series of reference voltage, and all voltages are zero-temperature coefficient.
Current source buffer (302) and current setting resistance (308) effect produce the original reference electric current.If very high to the current value requirement, then current setting resistance (308) is used non-essential resistance, at this moment reference voltage V
REFBe zero-temperature coefficient voltage.If allow the electric current of certain deviation, then current setting resistance (308) is used internal resistance, at this moment reference voltage V
REFFor possessing the reference voltage of uniform temp coefficient, can draw the voltage of specified temp coefficient by a reference source BANDGAP inside with this internal resistance.Can offset the temperature coefficient of electric current like this, the inherent variability of electric current only is the resistance process deviation.
This original reference electric current through current mirror (305) and current mirror (306) twice mirror image after, convert current signal to voltage signal V by biased electrical pressure pipe (307)
BPThe bias voltage V of buffer in the connection layout 2
BPThe supply voltage of buffer meets same current potential VDD in the supply voltage of biased electrical pressure pipe (307) and the time delay chain loop.PMOS current mirror (305) is located the PMOS compensating pipe (303) of a shunting action, and the source class of PMOS compensating pipe (303) connects the reference voltage V that low drop out voltage regurator LDO (301) divider resistance produces
1Suitable V is set
1Make PMOS compensating pipe (303) that a constant gate source voltage V be arranged
1-V
AVDD, if the PMOS pipe works under the fast process corner, then should extract more electric current (with respect to typical case) in the place, make the electric current that finally flows to buffer shown in Figure 4 diminish, to offset in the buffer time-delay that PMOS pipe fast causes less than normal thereby increase time-delay; If the PMOS pipe works under the slow process corner, then should the place extract electric current (with respect to typical case) still less, make that the electrorheological that finally flows to buffer shown in Figure 4 is big, to offset in the buffer time-delay that PMOS pipe at a slow speed causes bigger than normal thereby reduce to delay time.NMOS current mirror (306) is located the NMOS compensating pipe (304) of a shunting action, and the source class of NMOS compensating pipe (304) connects the reference voltage V that low drop out voltage regurator LDO (301) divider resistance produces
2, make NMOS compensating pipe (304) that a constant gate source voltage V be arranged
2, if the NMOS pipe works under the fast process corner, then should extract more electric current (with respect to typical case) in the place, make the electric current that finally flows to buffer shown in Figure 4 diminish, to offset in the buffer time-delay that NMOS pipe fast causes less than normal thereby increase time-delay; If the NMOS pipe works under the slow process corner, then should the place extract electric current (with respect to typical case) still less, make that the electrorheological that finally flows to buffer shown in Figure 4 is big, to offset in the buffer time-delay that NMOS pipe at a slow speed causes bigger than normal thereby reduce to delay time.
Following table is for using the emulation reading of different driven with current sources TDC of the present invention to regular time section timing different process angle under certain technology.(seeing the following form)
| Process corner | FF | TT | SS |
| Common constant-current source | 648 | 523 | 437 |
| Compensating current element | 511 | 523 | 501 |
Know easily that by last table after the technological compensa tion technology of application at delay unit loop (101), time-to-digit converter TDC reading has good consistency under different process.
More than show and described basic principle of the present invention and principal character and advantage thereof.The technical staff of the industry should understand; the present invention is not restricted to the described embodiments; that describes in the foregoing description and the specification just illustrates principle of the present invention; without departing from the spirit and scope of the present invention; the present invention also has various changes and modifications, and these changes and improvements all fall in the claimed scope of the invention.The claimed scope of the present invention is defined by appending claims and equivalent thereof.
Claims (10)
1, a kind of high-performance time-digital converter circuit structure is characterized in that, it comprises the time delay chain loop that produces low data, counter and compensating control source that produces high position data; Carried out the low level counting and given described counter with this signal with specific periodic transfer by described time delay chain loop, described counter adds up to the signal time in this specific cycle, as the high position of time-to-digit converter; Described compensating control source compensates, controls the voltage signal of described time delay chain loop.
2, circuit framework according to claim 1 is characterized in that: described time delay chain loop is made of delay unit loop, comparator, latch, encoder and initialization unit; Initial signal STA makes the conducting of described delay unit loop by described initialization unit, and described delay unit loop is converted to digital signal by comparator, and by latch output, the afterbody latch is exported as carry signal; End signal END makes data latching that described latch will this moment and latched data is transferred to encoder, by encoder with data transaction and as the low level output of time-to-digit converter.
3, circuit framework according to claim 2, it is characterized in that: described delay unit loop is connected and composed by some fully differential buffers, described afterbody buffer is connected with first order buffer is anti-phase, and remaining every grade buffer is connected together with back first-level buffer device.
4, circuit framework according to claim 3 is characterized in that: described buffer is made of P-channel field-effect transistor (PEFT) pipe, signaling switch EN, metal-oxide-semiconductor MP1, MP2, MN1, MN2, MN3, MN4; The source electrode of metal-oxide-semiconductor MN1, MN2, MN3, MN4 is connected to each other, then ground connection; The grid of metal-oxide-semiconductor MN1, MN3 is connected to each other, and connects the drain electrode of metal-oxide-semiconductor MN2, MN3 then successively, meets output OUT-, and the grid of metal-oxide-semiconductor MN2, MN4 is connected to each other, and connects the drain electrode of metal-oxide-semiconductor MN4, MN1 then successively, meets output OUT+; Supply voltage VDD connects the source electrode of P-channel field-effect transistor (PEFT) pipe, the voltage signal VBP of compensating control source inserts the grid of P-channel field-effect transistor (PEFT) pipe, the drain electrode of P-channel field-effect transistor (PEFT) pipe is connected respectively to the source electrode of metal-oxide-semiconductor MP1, MP2 by signaling switch EN, the drain electrode of metal-oxide-semiconductor MP1, MP2 meets output OUT-and output OUT+ respectively, the grid of metal-oxide-semiconductor MP1, MP2 meets input IN+, IN-respectively, form the fully differential structure of both-end input both-end output, delay time by the voltage-controlled current source control transmission.
5, circuit framework according to claim 1 is characterized in that: the described counter ripple counter that several d type flip flops constitute of serving as reasons, the carry signal that the time delay chain loop provides is counted, as the high position output of time-to-digit converter.
6, circuit framework according to claim 1 is characterized in that: described control compensation source comprises low drop out voltage regurator LDO, current source buffer, PMOS current mirror, NMOS current mirror, bias voltage efferent duct and current setting resistance; Described low drop out voltage regurator LDO connects PMOS current mirror, current source buffer, NMOS current mirror and current setting resistance successively, and internal work voltage AVDD and a series of reference voltage are provided; Described current source buffer and current setting resistance are connected to each other, and effect produces the original reference electric current, behind PMOS current mirror and NMOS current mirror mirror image, by bias voltage efferent duct output voltage signal VBP.
7, circuit framework according to claim 6, it is characterized in that: between described PMOS current mirror and low drop out voltage regurator LDO, be provided with PMOS compensating pipe with shunting action, its grid connects low drop out voltage regurator LDO, and drain electrode connects the PMOS current mirror.
8, circuit framework according to claim 6, it is characterized in that: between described NMOS current mirror and low drop out voltage regurator LDO, be provided with NMOS compensating pipe with shunting action, its grid connects low drop out voltage regurator LDO, and drain electrode connects the NMOS current mirror.
9, circuit framework according to claim 6 is characterized in that: the supply voltage of described bias voltage efferent duct meets supply voltage VDD.
10, circuit framework according to claim 6 is characterized in that: described low drop out voltage regurator LDO is made of a reference source BANDGAP, error amplifier, efferent duct and divider resistance; The termination of a reference source BANDGAP is gone into the negative pole of error amplifier input, the other end inserts the current source buffer, the positive pole of error amplifier input inserts between the divider resistance, the grid of error amplifier output termination efferent duct, the drain electrode of efferent duct connects divider resistance successively, carries out dividing potential drop and output.
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Cited By (25)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101924558A (en) * | 2009-04-24 | 2010-12-22 | 索尼公司 | Binary conversion circuit and method, AD converter, solid-state imaging device and camera system |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US5331295A (en) * | 1993-02-03 | 1994-07-19 | National Semiconductor Corporation | Voltage controlled oscillator with efficient process compensation |
| US5905412A (en) * | 1997-05-21 | 1999-05-18 | National Semiconductor Corporation | Process compensation method for CMOS current controlled ring oscillators |
| JP3616268B2 (en) * | 1999-02-10 | 2005-02-02 | Ｎｅｃエレクトロニクス株式会社 | Delay circuit for ring oscillator |
-
2007
- 2007-03-12 CN CNB2007100379770A patent/CN100539428C/en active Active
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2008
- 2008-03-11 EP EP08102491.1A patent/EP1971032B1/en not_active Not-in-force
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Also Published As
| Publication number | Publication date |
|---|---|
| EP1971032A3 (en) | 2010-02-03 |
| EP1971032B1 (en) | 2013-06-19 |
| EP1971032A2 (en) | 2008-09-17 |
| CN100539428C (en) | 2009-09-09 |
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