CN103248363B - Simulation arrives digital conversion method to digital conversion circuit and simulation - Google Patents
Simulation arrives digital conversion method to digital conversion circuit and simulation Download PDFInfo
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- CN103248363B CN103248363B CN201210024433.1A CN201210024433A CN103248363B CN 103248363 B CN103248363 B CN 103248363B CN 201210024433 A CN201210024433 A CN 201210024433A CN 103248363 B CN103248363 B CN 103248363B
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Abstract
A kind of simulation arrives digital conversion method to digital conversion circuit and simulation, and this simulation comprises a reference circuit and an AD converter to digital conversion circuit. Reference circuit provides a basic voltage, its one end ground connection. AD converter receives a mimic input signal and basic voltage signal. AD converter comprises one first direct current buffer cell and digital conversion nuclear unit is arrived in a simulation. First direct current buffer cell internal receipt one compensation voltage signal and the data voltage signal to be digitized, to export two changeover control signals. These two changeover control signals and one that simulation receives the first direct current buffer cell to digital conversion nuclear unit simulate digital conversion input range voltage signal, to export a numerical code. Aforesaid compensation voltage signal, data voltage signal and simulation have to digital conversion input range voltage signal and to add basic voltage signal.
Description
Technical field
The present invention relates to a kind of simulation to digital conversion technique, it is possible to reduce the conversion mistake that the variation due to technique, voltage, temperature or noise etc. is produced.
Background technology
The information form of digitizing is current very general mode, is beneficial to store data or data processing. For the electronic installation of video, it needs to convert the signal of simulation to numerary signal, for the process of rear end. Simulate digital conversion circuit is indispensable circuit in the electronic installation of digitizing.
But, owing to the AD converter analog-to-digitalconverter (ADC) of video formula is easily subject to technique (process, P) voltage (Voltage, V), temperature (Temperature, T) and the variation of noise (noise) affected, make ADC export code (digitalcode) deviation or error result can be produced.
Fig. 1 illustrates tradition simulation to digital conversion circuit block schematic diagram. Consulting Fig. 1, just simulation is to the operation mechanism of digital conversion circuit, and it needs a reference circuit (ReferenceCircuit) 50 in order to produce required " operating voltage " and " working current " to each AD converter 100. For three AD converters, it is denoted as ADC1, ADC2, ADC3.
In each AD converter 100, give simulation to digital conversion nuclear unit (ADCcore) 118 by the simulation of gain unit (GainBlock) 102 generation demand to digital conversion input range (ADCinputrange) voltage signal 104, to control the scope to be digitized.
Each AD converter 100 also comprises a compensating unit (OffsetBlock) 108 be connected with gain unit 102, to receive another the voltage signal 106 exported with gain unit 102, and produce a compensation voltage signal with ADC_VIM and represent, it is through the voltage stabilizing of an outside voltage stabilizing electrical equipment 110, and its magnitude of voltage is Voffset.
Each AD converter 100 also comprises clamp voltage unit (Clampvoltageblock) 112.Produced the output to compensating unit 108 by gain unit 102 and also inputed to clamp voltage unit 112, to produce the clamp voltage signal of pincers demand. One multiplexer (MUX) 114 receives clamp voltage signal and ground connection voltage and exports a clamp voltage Vclamp, and it is also via the voltage stabilizing of electrical condenser 120 of outside.
Each AD converter 100 also receives the analog voltage signal Vin of input, it is input to inside via external capacitive 122, simultaneously by a derailing switch 124, the clamp voltage Vclamp exported by multiplexer (MUX) 114, each input signal is added a DC level, and produce data voltage signal, indicate with ADC_VIP.
Each AD converter 100 also comprises a direct current buffer cell (DC_buffer) 116, and it receives data voltage signal ADC_VIP and compensation voltage signal ADC_VIM. After the voltage signal of this ADC_VIP and ADC_VIM is input to direct current buffer cell 116, digital conversion nuclear unit 118 is exported to via direct current buffer cell 116, produce the different sizes of the analog voltage signal Vin of corresponding input again via its computing, and export the numerical code after conversion. At this, analog voltage signal Vin may be red turquoise (RGB) color ash rank signal or the color system of YPbPr under color signal.
Above-mentioned AD converter 100 is under the influence of change of technique, voltage, temperature (PVT) or noise, the operating voltage that reference circuit produces or working current can change by it, so the voltage signal of ADC_VIP and ADC_VIM and simulation to digital conversion input range signal also can produce change. If when the otherness between these signals is not consistence, incorrect numerical code will be produced.
How to improve the exactness of the numerical code that quanxtizer 100 exports, it is need research and development further.
Summary of the invention
The present invention provides a kind of simulation to digital conversion circuit and method, it is possible to reduce the result of the conversion mistake that the variation due to technique, voltage, temperature or noise etc. is produced.
The present invention provides a kind to simulate digital conversion circuit. This circuit comprises a reference circuit and an AD converter. Reference circuit provides a basic voltage, its one end ground connection. AD converter receives a mimic input signal and basic voltage signal. AD converter comprises one first direct current buffer cell and digital conversion nuclear unit is arrived in a simulation. First direct current buffer cell internal receipt one compensation voltage signal and the data voltage signal to be digitized, to export two changeover control signals. These two changeover control signals and one that simulation receives the first direct current buffer cell to digital conversion nuclear unit simulate digital conversion input range voltage signal, to export a numerical code. Aforesaid compensation voltage signal, data voltage signal and simulation have to digital conversion input range voltage signal and to add basic voltage signal.
The present invention provides a kind to simulate digital conversion method. This method comprises and utilizes a reference circuit, it is provided that a basic voltage, one end ground connection of this basic voltage signal. Again this basic voltage signal is inputed to an AD converter, so that a direct current buffer cell of this AD converter inside and the multiple control voltage signals simulating digital conversion nuclear unit are all referenced to this basic voltage, to export a turnover number character code.
For the above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate accompanying drawing to be described in detail below.
Accompanying drawing explanation
Fig. 1 illustrates tradition simulation to digital conversion circuit block schematic diagram.
Fig. 2 illustrates according to one embodiment of the invention, and simulation is to digital conversion circuit schematic diagram.
[main element nomenclature]
50: reference circuit
100: AD converter
102: gain unit
104: simulation is to digital conversion input range voltage signal
106: voltage signal
108: compensating unit
110,120: electrical condenser
112: clamp voltage unit
114: multiplexer (MUX)
116: direct current buffer cell
118: simulation is to digital conversion nuclear unit
122: electrical condenser
124: derailing switch
200: AD converter
202: direct current buffer cell
204,210: totalizer
206: compensating unit
208: gain unit
212: simulation is to digital conversion input range voltage signal
214: multiplexer
216: direct current buffer cell
218: circuit box
Embodiment
The present invention proposes simulation to digital conversion circuit and method, it is possible to reduce the result of the conversion mistake that the variation due to technique, voltage, temperature or noise etc. is produced.
Hereinafter for some embodiments, the present invention is described, but the present invention is not limited only to illustrated embodiment.
Fig. 2 illustrates according to one embodiment of the invention, and simulation is to digital conversion circuit schematic diagram. Consult Fig. 2, produce the operating voltage of demand, working current and basic voltage Vbase to each AD converter 200 by reference circuit 50, such as, be three and represent with ADC1-ADC3. The basic voltage Vbase that reference circuit 50 produces, its one end ground connection, and such as can input basic voltage Vbase through a direct current buffer cell 202. That is basic voltage Vbase contains the variation of reference circuit 50 caused by various factors.
In each AD converter 200, gain unit 208 produces two voltage signals according to demand, one of them output voltage signal is used for the compensation voltage signal ADC_VIM and data voltage signal ADC_VIP of follow-up generation, and another output voltage signal is used for follow-up generation simulation to digital conversion input range voltage signal 212. This compensation voltage signal ADC_VIM, data voltage signal ADC_VIP can add basic voltage Vbase with simulation to digital conversion input range voltage signal 212, so can so that P, V, T or power supply noise etc. be had more consistent change with reference circuit 50 by AD converter 200, it is possible to reduce the mistake of the turnover number character code exported by digital conversion nuclear unit 118.
Associate and after producing basic voltage Vbase, follow-up relatively detailed circuit knot and processing mode illustrate as follows with ground voltage via reference circuit 50.
For the simulation of demand to digital conversion input range voltage signal 212, the voltage signal that gain unit 208 produces, via a totalizer 210, is added with basic voltage Vbase and obtains simulation to digital conversion input range voltage signal 212.
Each AD converter 200 also comprises a compensating unit 206, its receive by gain unit 208 a voltage signal of output. The voltage signal that compensating unit 206 exports is compensated voltage signal ADC_VIM being added with basic voltage Vbase via a totalizer 204. Compensation voltage signal ADC_VIM also can do voltage stabilizing via the voltage regulation capacitor 110 of outside, and the magnitude of voltage after voltage stabilizing is Voffset.
This compensation voltage signal ADC_VIM be direct current buffer cell (DC_buffer) 116 input signal its one.
Each AD converter 200 also comprises multiplexer (MUX) 214 and direct current buffer cell 216. The compensation voltage signal and the basic voltage Vbase that export by totalizer 204 are input to multiplexer 214. The output of multiplexer 214 is exporting a clamp voltage signal Vclamp via direct current buffer cell 216. This clamp voltage signal Vclamp can obtain voltage stabilizing through the voltage regulation capacitor 120 with outside, adds thereafter the data signal of input again via a derailing switch 124, and its mechanism is as follows.
One input endpoint of each AD converter 200 can via an electrical condenser 122 input analog voltage signal Vin to inner. When analog voltage signal Vin inputs, trip switch device 124 carries out pincers braking and does, and the analog voltage signal Vin of each input is added that a volts DS is to produce data voltage signal ADC_VIP. This volts DS is exactly the voltage exported by direct current buffer cell 216, and it also contains the variation of basic voltage Vbase.
In each AD converter 200, the voltage signal of ADC_VIP and ADC_VIM is input to simulation to digital conversion nuclear unit 118 via direct current buffer cell 116 again, then produces the numerical value of the different digital code of corresponding different Vin size via its computing.
At the above-mentioned circuit box 218 being connected with outside, it is the source of induction external noise, but its current potential is identical with signal ADC_VIM. When have noise from power supply or ground voltage again or AD converter outside produce time, signal ADC_VIP also can followed by signal ADC_VIM and change together.
The figure image signal of analog voltage signal Vin can be such as again RGB, YPbPr or combined type figure image signal (CVBS) etc.
According to one embodiment of the invention, under technique, voltage, temperature (P, V, T) or the influence of change of noise, the operating voltage that reference circuit 50 produces and working current can change by it. And voltage signal ADC_VIP and the ADC_VIM in AD converter 200 also can produce variation. Therebetween otherness is consistent, and follows basic voltage Vbase mono-and change. When have noise from power supply or ground voltage, again or circuit outside produce time, voltage signal ADC_VIP can followed by voltage signal ADC_VIM and change together. Digital conversion input range voltage signal is also followed basic voltage Vbase mono-simultaneously and is changed. So, the turnover number character code exported by digital conversion nuclear unit 118, relatively not easily follows change, to lower the generation of mistake.
The present invention simulates digital conversion circuit and makes multiple control voltage signals of digital conversion nuclear unit 116 be referenced to the basic voltage Vbase produced by reference circuit, to export a turnover number character code, so lower and export code and make a mistake the probability with extent of deviation.
The method that the present invention just processes, it utilizes a reference circuit, it is provided that a basic voltage, one end ground connection of this basic voltage signal. Again this basic voltage signal is inputed to an AD converter, so that a direct current buffer cell of this AD converter inside and the multiple control voltage signals simulating digital conversion nuclear unit are all referenced to this basic voltage, to export a turnover number character code.
Reference circuit first can provide this basic voltage signal after direct current cushions.
Although the present invention discloses as above with embodiment; so itself and be not used to limit the present invention; without departing from the spirit and scope of the present invention, when doing a little change and retouching, therefore protection scope of the present invention is when being as the criterion depending on the appended claims person of being defined for those skilled in the art.
Claims (9)
1. simulation is to a digital conversion circuit, comprising:
One reference circuit a, it is provided that basic voltage, one end ground connection of this basic voltage signal; And
One AD converter, receives a mimic input signal and this basic voltage signal,
Wherein this AD converter comprises:
One first direct current buffer cell, internal receipt one compensation voltage signal and the data voltage signal to be digitized, to export two changeover control signals; And
One simulation is to digital conversion nuclear unit, digital conversion input range voltage signal is arrived in these two changeover control signals and the simulation that receive this first direct current buffer cell, to export a numerical code, wherein this compensation voltage signal, this data voltage signal and this simulation all add this basic voltage signal to digital conversion input range voltage signal.
2. simulation as claimed in claim 1 is to digital conversion circuit, wherein this reference circuit, first through one the 2nd direct current buffer cell, to provide this basic voltage signal.
3. simulation as claimed in claim 1 is to digital conversion circuit, and wherein this AD converter also comprises:
One gain unit, produces one first voltage signal and one the 2nd voltage signal;
One compensating unit, receives this first voltage signal;
One first totalizer, receives an output of this basic voltage signal and this compensating unit, and to export this compensation voltage signal, this compensation voltage signal inputs to this first direct current buffer cell after voltage stabilizing;
One multiplexer, receives this compensation voltage signal and this basic voltage signal;
One the 2nd direct current buffer cell, receives an output of this multiplexer, and to export a clamp voltage, wherein this clamp voltage signal is added to this mimic input signal of input after voltage stabilizing and produces this data voltage signal to this first direct current buffer cell;
One the 2nd totalizer, receives the 2nd voltage signal and this basic voltage signal of this gain unit, with export this simulation to digital conversion input range voltage signal to this simulation to digital conversion nuclear unit.
4. simulation as claimed in claim 3 is to digital conversion circuit, and wherein this reference circuit is first through one the 3rd direct current buffer cell, to provide this basic voltage signal.
5. simulation as claimed in claim 3 is to digital conversion circuit, also comprises a switch, in order to this clamp voltage after voltage stabilizing is added this mimic input signal.
6. simulation as claimed in claim 3 is to digital conversion circuit, also comprises a compensation voltage stabilizing electrical condenser, is connected with the end point of this AD converter, with to this compensation voltage signal voltage stabilizing.
7. simulation as claimed in claim 3 is to digital conversion circuit, also comprises a pincers voltage regulation capacitor, is connected with the end point of this AD converter, with to this clamp voltage signal voltage stabilizing.
8. simulation is to a digital conversion method, comprising:
Utilize a reference circuit, it is provided that a basic voltage, one end ground connection of this basic voltage signal; And
This basic voltage signal is inputed to an AD converter, so that a direct current buffer cell of this AD converter inside and the multiple control voltage signals simulating digital conversion nuclear unit are all referenced to this basic voltage, to export a turnover number character code.
9. simulation as claimed in claim 8 is to digital conversion method, and wherein this reference circuit first provides this basic voltage signal after direct current cushions.
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| CN201210024433.1A CN103248363B (en) | 2012-02-03 | 2012-02-03 | Simulation arrives digital conversion method to digital conversion circuit and simulation |
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| CN201210024433.1A CN103248363B (en) | 2012-02-03 | 2012-02-03 | Simulation arrives digital conversion method to digital conversion circuit and simulation |
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| CN103248363A CN103248363A (en) | 2013-08-14 |
| CN103248363B true CN103248363B (en) | 2016-06-08 |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5371552A (en) * | 1991-10-31 | 1994-12-06 | North American Philips Corporation | Clamping circuit with offset compensation for analog-to-digital converters |
| EP1251507A2 (en) * | 2001-04-17 | 2002-10-23 | Sony Corporation | Asymmetry correcting circuit and information reproducing apparatus using the same |
| TW200541223A (en) * | 2004-06-02 | 2005-12-16 | Mstar Semiconductor Inc | Video signal processing system with a dynamic adc calibration loop and related methods |
| US7116261B1 (en) * | 2005-05-09 | 2006-10-03 | Texas Instruments Incorporated | Method and apparatus for accurate inverse-linear voltage/current generator |
| CN101043215A (en) * | 2007-03-12 | 2007-09-26 | 启攀微电子（上海）有限公司 | High-performance time-digital converter circuit structure |
| TW201014339A (en) * | 2008-09-17 | 2010-04-01 | Realtek Semiconductor Corp | Method and analog front-end processing apparatus for pin-sharing |
-
2012
- 2012-02-03 CN CN201210024433.1A patent/CN103248363B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5371552A (en) * | 1991-10-31 | 1994-12-06 | North American Philips Corporation | Clamping circuit with offset compensation for analog-to-digital converters |
| EP1251507A2 (en) * | 2001-04-17 | 2002-10-23 | Sony Corporation | Asymmetry correcting circuit and information reproducing apparatus using the same |
| TW200541223A (en) * | 2004-06-02 | 2005-12-16 | Mstar Semiconductor Inc | Video signal processing system with a dynamic adc calibration loop and related methods |
| US7116261B1 (en) * | 2005-05-09 | 2006-10-03 | Texas Instruments Incorporated | Method and apparatus for accurate inverse-linear voltage/current generator |
| CN101043215A (en) * | 2007-03-12 | 2007-09-26 | 启攀微电子（上海）有限公司 | High-performance time-digital converter circuit structure |
| TW201014339A (en) * | 2008-09-17 | 2010-04-01 | Realtek Semiconductor Corp | Method and analog front-end processing apparatus for pin-sharing |
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| CN103248363A (en) | 2013-08-14 |
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