CN204906363U - Flash analog to digital conversion circuit - Google Patents
Flash analog to digital conversion circuit Download PDFInfo
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- CN204906363U CN204906363U CN201520519329.9U CN201520519329U CN204906363U CN 204906363 U CN204906363 U CN 204906363U CN 201520519329 U CN201520519329 U CN 201520519329U CN 204906363 U CN204906363 U CN 204906363U
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- switch
- comparator
- bit register
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- flashad
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Abstract
The utility model discloses a flash analog to digital conversion circuit compares with traditional flash ADC circuit, has increased signal detecting element, carries out the comparison through the difference to twice sampled signal in front and back, is less than the AD conversion that less figure place then only need be carried out to a certain threshold value as if it to the consumption of single AD conversion has been reduced. The utility model discloses obviously improve ADC conversion rate, reduced the consumption, reached the effect of straining denoising sound simultaneously.
Description
Technical field
The utility model relates to electronic circuit technology field, particularly relates to a kind of Flash analog to digital conversion circuit.
Background technology
In integrated circuit (IC) system, A/D converter is the important bridge of connecting analog system and digital information processing system, Digital Signal Processing is in the extensive use of high-definition picture, Hi-Fi audio signal and wireless communication field, make the ADC (Analog-to-digitalconverter based on CMOS technology, analog to digital converter) demand day by day increase, especially to the ADC of high speed, high accuracy, low-power consumption, low cost.FlashAD change-over circuit advantage is that circuit structure and principle are simple, and be convenient to realize, conversion speed is very fast, is therefore widely used.
Along with the rise of the application such as portable set and wearable device, the requirement of application system to data processing speed and low-power consumption is more and more higher.Analog to digital converter, as the bridge of connecting analog signal and digital signal in application system, is indispensable important component part, and the power consumption reducing analog to digital converter is the direction that engineers is being made great efforts always.Signal in addition in real application systems is generally continually varying tempolabile signal, therefore for the situation of switching rate far above output signal frequency, the input analog signal of ADC should be more or less the same at the numerical value in double sampling moment, if there is the situation that difference is larger, can noise be thought, thus filtering in addition.Figure 1 shows that the schematic diagram that there is noise in the input signal of ADC, wherein solid line is input analog signal, and dotted arrow is each signal sampling, when front and back double sampling signal occur comparatively big difference time think and occurred noise.
Before FlashADC design be all generally be universal by circuit design, do not design for concrete application scenario and application system, therefore power consumption is higher.
Summary of the invention
In view of FlashADC is higher to signal converted power consumption, and do not have the function of filtered noise, the utility model object is to provide a kind of Flash analog to digital conversion circuit, on the ADC basis of existing degree of precision, reduce power consumption, and make ADC self have certain filter to make an uproar function.
A kind of Flash analog to digital conversion circuit, comprise FlashAD converting unit, logical-sequential control unit and detecting signal unit, described FlashAD converting unit provides control signal for described logical-sequential control unit, described detecting signal unit is connected by switch with described FlashAD converting unit, described logical-sequential control unit provides control signal for FlashAD converting unit and detecting signal unit, described detecting signal unit comprises with lower part: sampling holder, analog subtracter, absolute value block, comparator, zero-crossing comparator, numeral plus/minus musical instruments used in a Buddhist or Taoist mass, M bit register, N bit register, N position output register and the first switch, second switch, 7th switch, 8th switch, 9th switch and the tenth switch, wherein, described sampling holder, described analog subtracter and described absolute value block are electrically connected successively, the output of described analog subtracter is connected with described zero-crossing comparator simultaneously, the output of described absolute value block is connected with the negative input end of described comparator, the positive input terminal of described comparator inputs the first reference signal, the output of comparator is connected with described FlashAD converting unit, the other end of described FlashAD converting unit is connected to described N bit register by described 7th switch, is connected to described M bit register by the 8th switch, the output of described M bit register and described N bit register is connected to described digital plus/minus musical instruments used in a Buddhist or Taoist mass, the output of described digital plus/minus musical instruments used in a Buddhist or Taoist mass is connected by the tenth switch with described N position output register, and described N bit register is also directly connected with described N position output register by described 9th switch, before described first switch is positioned at described sampling holder, before described second switch is positioned at described analog subtracter.
In some cases, the output of described comparator is the first control signal, be used for controlling described 7th switch, the 8th switch, the 9th switch and the tenth switch, also control the switch in described FlashAD converting unit simultaneously, the output of described zero-crossing comparator is the second control signal, is used for controlling described digital plus/minus musical instruments used in a Buddhist or Taoist mass.
In other situations, the output of described comparator and described zero-crossing comparator is all connected to described logical-sequential control unit, and described logical-sequential control unit exports the first control signal and the second control signal.
Before described FlashAD converting unit comprises encoder and is connected in parallel on described encoder 2
nindividual comparator and be connected to the 2nd
mthe positive input terminal of-1 comparator and the 2nd
mthe 3rd switch between the positive input terminal of comparator, be connected to described first reference signal and the 2nd
mthe 4th switch between the positive input terminal of-1 comparator, be connected to the 2nd
mthe negative input end of-1 comparator and the 2nd
mthe 5th switch between the negative input end of comparator, be connected to described comparator negative input end and the 2nd
mthe 6th switch between the negative input end of-1 comparator; Described first reference signal enters the described 2nd through described 4th switch
mthe positive input terminal of-1 comparator, described second reference signal enters the described 2nd
mthe positive input terminal of comparator; Described encoder is connected with described M bit register with described N bit register respectively by the 7th switch, the 8th switch; Described 3rd switch, the 4th switch, the 5th switch and the 6th switch control by the first control signal.
The value of M is less than the value of N.
Described first reference signal is 1/2 of the second reference signal
n-M.
The beneficial effect that the utility model has:
1, power consumption is reduced; Traditional N position FlashADC needs 2
n-1individual analog comparator works simultaneously, and compares the difference of front and back double sampling signal in the utility model, if it is less than a certain threshold value, only needs the AD conversion of carrying out M position, and namely 2
m-1individual analog comparator works simultaneously, thus effectively reduces the power consumption of circuit.
2, filtered noise; Traditional FlashADC does not have the function of filtered noise, therefore must add the module of filtering and making an uproar in system, thus add the complexity of system.In the utility model, the difference of front and back double sampling signal is compared, if it is greater than a certain threshold value (namely having occurred abrupt change), think noise, now do not need to carry out AD conversion, but with last time AD conversion result as this output, reach the effect of filtering noise (signal abrupt change).
Accompanying drawing explanation
Fig. 1 is the signal schematic representation that there is noise in the input signal of traditional ADC;
Fig. 2 is the schematic diagram of the utility model embodiment;
Fig. 3 is the another kind of operating state schematic diagram of Fig. 2 embodiment.
Embodiment
In order to make the purpose of this utility model, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the utility model is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the utility model, and be not used in restriction the utility model.
As shown in Figures 2 and 3, be traditional FlashADC circuit chief component in dot-dash wire frame, i.e. FlashAD converting unit and logical-sequential control unit, through FlashAD converting unit change and the digital signal exported as the control signal being supplied to logical-sequential control unit.Innovation of the present utility model is to add detecting signal unit, be connected with sampling holder, analog subtracter, absolute value block, comparator in turn, comparator exports control signal C1, connects zero-crossing comparator after analog subtracter simultaneously, and zero-crossing comparator exports control signal C2.Detecting signal unit also comprises M bit register, N bit register, and the digital plus/minus musical instruments used in a Buddhist or Taoist mass be connected with them, the N position output register that is connected with digital plus/minus musical instruments used in a Buddhist or Taoist mass, and N bit register and N position output register are directly connected simultaneously.C1 is used for the switch in control chart 2, C2 control figure plus/minus musical instruments used in a Buddhist or Taoist mass.
As shown in Figure 2, AD conversion is controlled the analog signal of input stored in sampling holder by logical-sequential control device first, and SW3, SW5 and SW7 are closed realize once complete N position AD conversion, SW3, SW5 and SW7, stored in N bit register, then disconnect by AD conversion result; From second time AD conversion, adopt following steps to carry out AD conversion:
(1) SW1 disconnects, and SW2 closes, and SW3 ~ SW10 disconnects, and the analog signal that the last time stored inputs is subtracted each other, with level V after result being taken absolute value in the analog signal of current input and sampling holder
ref/ 2
n-Mcompare and produce control signal C1, by zero-crossing comparator, whether zero be greater than to result simultaneously and carry out judgement generation control signal C2;
(2) if C1 is 1, then SW4, SW6 and SW8 are closed, and SW3, SW5 and SW7 disconnect, and now the output voltage of analog subtracter are carried out to the AD conversion of M position, by transformation result stored in M bit register; If C1 is 0, disconnect SW2, the closed analog signal of SW1 to current input stores, SW4, SW6 and SW8 disconnect simultaneously, SW3, SW5 and SW7 close, and now the analog signal of current input are carried out to the AD conversion of complete N position, by transformation result stored in N bit register;
(3) close if C1 is 1, SW10, SW9 disconnects, if C2 is 1, N bit register and M bit register is carried out add operation, if C2 is 0, N bit register and M bit register is carried out subtraction operation, and result exported stored in N position output register; If C1 is 0, then SW10 disconnects, and SW9 closes, and directly the data in N bit register is exported stored in N position output register;
(4) if C1 is 1, by the data assignment of N position output register to N bit register; If C1 is 0, then without operation.
As shown in Figure 3, C1 is not as the signal of control switch SW5 with Fig. 2 difference.Its principle is as follows:
AD conversion is controlled the analog signal of input stored in sampling holder by logical-sequential control device first, and SW3, SW5 and SW6 are closed realize once complete N position AD conversion, SW3, SW5 and SW6, stored in N bit register, then disconnect by AD conversion result; From second time AD conversion, adopt following steps to carry out AD conversion:
(1) SW1 disconnects, and SW2 closes, and SW3 ~ SW10 disconnects, and the analog signal that the last time stored inputs is subtracted each other, with level V after result being taken absolute value in the analog signal of current input and sampling hold circuit
ref/ 2
n-Mcompare and produce control signal C1, by zero-crossing comparator, whether zero be greater than to result simultaneously and carry out judgement generation control signal C2.
(2) if C1 is 1, represent and be input as useful signal, then SW4, SW6 and SW8 close, and now the output voltage of analog subtracter are carried out to the AD conversion of M position, by transformation result stored in M bit register; If C1 is 0, represents and be input as noise, simultaneously SW4, SW6 and SW8 disconnect, and now do not carry out AD conversion to the analog signal of current input, but directly using last time AD conversion result as this transformation result, the data namely in N bit register remain unchanged;
(3) if C1 is 1, then SW10 closes, and SW9 disconnects, if C2 is 1, N bit register and M bit register is carried out add operation, if C2 is 0, N bit register and M bit register is carried out subtraction operation, and result exported stored in N position output register; If C1 is 0, then SW10 disconnects, and SW9 closes, and directly the data in N bit register is exported stored in N position output register;
(4) if C1 is 1, by the data assignment of N position output register to N bit register; If C1 is 0, then without operation.
Claims (5)
1. a Flash analog to digital conversion circuit, it is characterized in that: comprise FlashAD converting unit, logical-sequential control unit and detecting signal unit, described FlashAD converting unit provides control signal for described logical-sequential control unit, described detecting signal unit is connected by switch with described FlashAD converting unit, described logical-sequential control unit provides control signal for FlashAD converting unit and detecting signal unit, described detecting signal unit comprises with lower part: sampling holder, analog subtracter, absolute value block, comparator, zero-crossing comparator, numeral plus/minus musical instruments used in a Buddhist or Taoist mass, M bit register, N bit register, N position output register and the first switch, second switch, 7th switch, 8th switch, 9th switch and the tenth switch, wherein,
Described sampling holder, described analog subtracter and described absolute value block are electrically connected successively, the output of described analog subtracter is connected with described zero-crossing comparator simultaneously, the output of described absolute value block is connected with the negative input end of described comparator, the positive input terminal of described comparator inputs the first reference signal, the output of comparator is connected with described FlashAD converting unit, the other end of described FlashAD converting unit is connected to described N bit register by described 7th switch, is connected to described M bit register by the 8th switch; The output of described M bit register and described N bit register is connected to described digital plus/minus musical instruments used in a Buddhist or Taoist mass, the output of described digital plus/minus musical instruments used in a Buddhist or Taoist mass is connected by the tenth switch with described N position output register, and described N bit register is also directly connected with described N position output register by described 9th switch; Before described first switch is positioned at described sampling holder, before described second switch is positioned at described analog subtracter.
2. Flash analog to digital conversion circuit according to claim 1, it is characterized in that: the output of described comparator is the first control signal, be used for controlling described 7th switch, the 8th switch, the 9th switch and the tenth switch, also control the switch in described FlashAD converting unit simultaneously, the output of described zero-crossing comparator is the second control signal, is used for controlling described digital plus/minus musical instruments used in a Buddhist or Taoist mass.
3. Flash analog to digital conversion circuit according to claim 1, it is characterized in that: the output of described comparator and described zero-crossing comparator is all connected to described logical-sequential control unit, and described logical-sequential control unit exports the first control signal and the second control signal.
4. Flash analog to digital conversion circuit according to claim 2, is characterized in that: before described FlashAD converting unit comprises encoder and is connected in parallel on described encoder 2
nindividual comparator and be connected to the 2nd
mthe positive input terminal of-1 comparator and the 2nd
mthe 3rd switch between the positive input terminal of comparator, be connected to described first reference signal and the 2nd
mthe 4th switch between the positive input terminal of-1 comparator, be connected to the 2nd
mthe negative input end of-1 comparator and the 2nd
mthe 5th switch between the negative input end of comparator, be connected to described comparator negative input end and the 2nd
mthe 6th switch between the negative input end of-1 comparator; Described first reference signal enters the described 2nd through described 4th switch
mthe positive input terminal of-1 comparator; Described encoder is connected with described M bit register with described N bit register respectively by the 7th switch, the 8th switch; Described 3rd switch, the 4th switch, the 5th switch and the 6th switch control by the first control signal.
5. Flash analog to digital conversion circuit according to claim 4, is characterized in that: the value of M is less than the value of N.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520519329.9U CN204906363U (en) | 2015-07-16 | 2015-07-16 | Flash analog to digital conversion circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520519329.9U CN204906363U (en) | 2015-07-16 | 2015-07-16 | Flash analog to digital conversion circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204906363U true CN204906363U (en) | 2015-12-23 |
Family
ID=54928507
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201520519329.9U Withdrawn - After Issue CN204906363U (en) | 2015-07-16 | 2015-07-16 | Flash analog to digital conversion circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN204906363U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105007077A (en) * | 2015-07-16 | 2015-10-28 | 南京邮电大学 | Flash analog-to-digital conversion circuit |
| CN108551344A (en) * | 2018-03-29 | 2018-09-18 | 上海集成电路研发中心有限公司 | Double sampled analog-to-digital conversion circuit |
-
2015
- 2015-07-16 CN CN201520519329.9U patent/CN204906363U/en not_active Withdrawn - After Issue
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105007077A (en) * | 2015-07-16 | 2015-10-28 | 南京邮电大学 | Flash analog-to-digital conversion circuit |
| CN105007077B (en) * | 2015-07-16 | 2018-03-02 | 南京邮电大学 | A kind of Flash analog to digital conversion circuits |
| CN108551344A (en) * | 2018-03-29 | 2018-09-18 | 上海集成电路研发中心有限公司 | Double sampled analog-to-digital conversion circuit |
| CN108551344B (en) * | 2018-03-29 | 2022-04-01 | 上海集成电路研发中心有限公司 | Double-sampling analog-to-digital conversion circuit |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| EE01 | Entry into force of recordation of patent licensing contract |
Assignee: Jiangsu Nanyou IOT Technology Park Ltd. Assignor: Nanjing Post & Telecommunication Univ. Contract record no.: 2016320000210 Denomination of utility model: Flash analog-to-digital conversion circuit Granted publication date: 20151223 License type: Common License Record date: 20161114 |
|
| LICC | Enforcement, change and cancellation of record of contracts on the licence for exploitation of a patent or utility model | ||
| EC01 | Cancellation of recordation of patent licensing contract |
Assignee: Jiangsu Nanyou IOT Technology Park Ltd. Assignor: Nanjing Post & Telecommunication Univ. Contract record no.: 2016320000210 Date of cancellation: 20180116 |
|
| EC01 | Cancellation of recordation of patent licensing contract | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20151223 Effective date of abandoning: 20180302 |
|
| AV01 | Patent right actively abandoned |