CN204859152U - Successive approximation type analog to digital conversion circuit based on signal autocorrelation nature - Google Patents
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Abstract
The utility model discloses a successive approximation type analog to digital conversion circuit based on signal autocorrelation nature compares with traditional SAR ADC circuit, has increased signal autocorrelation nature detecting element, carries out the comparison through the difference to twice sampled signal in front and back, is less than the AD conversion that less figure place then only need be carried out to a certain threshold value as if it to the consumption of single AD conversion has been reduced. The utility model discloses obviously improve ADC conversion rate, reduced the consumption, reached the effect of straining denoising sound simultaneously.
Description
Technical Field
The utility model relates to an electronic circuit technical field especially relates to a successive approximation type analog-to-digital conversion circuit based on signal autocorrelation.
Background
In an integrated circuit system, an a/D converter is an important bridge for connecting an Analog system and a digital signal processing system, and the wide application of digital signal processing technology in the fields of high-resolution images, high-fidelity audio signals and wireless communication has led to an increasing demand for an Analog-to-digital converter (ADC) based on a CMOS process, especially for an ADC with high speed, high precision, low power consumption and low cost. The resolution of an SAR (successive approximation register) a/D conversion circuit is high, the area is small, the power consumption is relatively low, but the speed is slow compared with other types of ADCs.
With the rise of application fields such as portable devices and wearable devices, the requirements of application systems on data processing speed and low power consumption are higher and higher. The analog-to-digital converter is an indispensable important component as a bridge for connecting an analog signal and a digital signal in an application system, and reducing the power consumption of the analog-to-digital converter is the direction in which engineers are always striving. In addition, signals in a practical application system are generally slowly-varying signals which change continuously, so that for the case that the conversion rate is far higher than the frequency of an output signal, the values of the input analog signal of the ADC at two sampling moments should have a small difference, and if the difference is large, the difference can be regarded as noise, so as to be filtered. Fig. 1 is a schematic diagram showing noise in an input signal of an ADC, where a solid line represents an input analog signal, a dotted arrow represents each signal sampling, and noise is considered to occur when a large difference occurs between two sampled signals.
Disclosure of Invention
In view of the low power consumption of the sar ADC, the ADC does not have the function of noise filtering, and the ADC has a certain noise filtering function.
A successive approximation type analog-to-digital conversion circuit based on signal autocorrelation comprises an AD conversion unit and a logic time sequence controller, wherein the AD conversion unit generates logic time sequence signals and provides the logic time sequence signals for the logic time sequence controller, the successive approximation type analog-to-digital conversion circuit further comprises a signal autocorrelation detection unit, the logic time sequence controller provides control signals for the AD conversion unit and the signal autocorrelation detection unit, and the signal autocorrelation detection unit comprises the following parts: the digital adder-subtractor comprises a sampling holder, an analog subtractor, an absolute value module, an M-bit DAC, a first comparator, a zero-crossing comparator, a digital adder-subtractor, an M-bit register, an N-bit output register, a first switch, a second switch, a seventh switch, an eighth switch, a ninth switch and a tenth switch; the sampling holder, the analog subtractor and the absolute value module are sequentially and electrically connected, the output end of the analog subtractor is simultaneously connected with the zero-crossing comparator, the output end of the absolute value module is simultaneously connected with the negative input ends of the M-bit DAC and the first comparator, the positive input end of the first comparator inputs a first reference signal, the output end of the M-bit register is connected to the digital adder/subtractor, the output end of the digital adder/subtractor is connected with the N-bit output register through a ninth switch, the output end of the M-bit register is also connected with the M-bit DAC, and the tenth switch is connected with the AD conversion unit; the first switch is located before the sample holder, the second switch is located before the analog subtractor, the seventh switch is located between the absolute value block and the M-bit DAC, and the eighth switch is located between the M-bit DAC and the AD conversion unit.
In some cases, an output of the first comparator is a first control signal for controlling the seventh switch, the eighth switch, the ninth switch, the tenth switch and the switch in the AD conversion unit, and an output of the zero-crossing comparator is a second control signal for controlling the digital adder/subtractor.
Alternatively, the output terminals of the first comparator and the zero-crossing comparator are connected to the logic timing controller, and the logic timing controller outputs a first control signal and a second control signal.
The AD conversion unit comprises an N-bit DAC, a second comparator, an N-bit register, a third switch, a fourth switch, a fifth switch and a sixth switch, wherein an output signal of the N-bit DAC enters a negative input end of the second comparator, an output end of the N-bit register is connected to the N-bit DAC, meanwhile, the output end of the N-bit register is connected with the N-bit output register through the tenth switch, and a reference signal is input to a positive input end of the second comparator; the third switch and the fourth switch are connected in parallel to the positive input end of the second comparator and are controlled by a first control signal; the reference signal entering the positive input of the second comparator is the second reference signal when the third switch is closed and the fourth switch is open, the reference signal entering the positive input of the second comparator is the first reference signal when the third switch is open and the fourth switch is closed, the fifth switch is located before the N-bit DAC, the sixth switch is located between the N-bit DAC and the negative input of the second comparator, and the eighth switch and the sixth switch are coupled to the negative input of the second comparator.
The value of M is less than the value of N.
1/2 where the first reference signal is a second reference signalN-M。
The utility model discloses still provide another kind of successive approximation type analog-to-digital conversion circuit based on signal autocorrelation, including AD converting element and logic time schedule controller, AD converting element produces logic time schedule signal, provides logic time schedule controller, AD converting element includes N position/M position DAC, second comparator, N position register, third switch, fourth switch, fifth switch, sixth switch and eighth switch, N position/M position DAC's output signal gets into the negative input end of second comparator, N position register's output is connected through the sixth switch N position/M position DAC, the positive input end input reference signal of second comparator; the third switch and the fourth switch are connected in parallel to the positive input end of the second comparator and are controlled by a first control signal; when the third switch is closed and the fourth switch is opened, the reference signal entering the positive input terminal of the second comparator is the second reference signal, when the third switch is opened and the fourth switch is closed, the reference signal entering the positive input terminal of the second comparator is the first reference signal, and the fifth switch is positioned in front of the N-bit/M-bit DAC; the logic timing controller provides control signals for the AD conversion unit and the signal autocorrelation detection unit, and the signal autocorrelation detection unit comprises the following parts: the digital adder-subtractor comprises a sampling holder, an analog subtractor, an absolute value module, a first comparator, a zero-crossing comparator, a digital adder-subtractor, an N-bit output register, a first switch, a second switch, a seventh switch, a ninth switch and a tenth switch; wherein,
the sampling holder, the analog subtractor and the absolute value module are electrically connected in sequence, the output end of the analog subtractor is simultaneously connected with the zero-crossing comparator, the output end of the absolute value module is simultaneously connected with the negative input ends of the N-bit/M-bit DAC and the first comparator, the positive input end of the first comparator inputs a first reference signal, the output end of the M-bit register is connected to the digital adder/subtractor, the output end of the digital adder/subtractor is connected with the N-bit output register through a ninth switch, the output end of the M-bit register is connected with the N-bit/M-bit DAC through an eighth switch, and the tenth switch is located between the N-bit register and the N-bit output register; the first switch is located before the sample holder, the second switch is located before the analog subtractor, the seventh switch is located between the absolute value module and the N-bit/M-bit DAC, the output of the first comparator is a first control signal for controlling all switches except the first switch and the second switch, and the output of the zero-crossing comparator is a second control signal for controlling the digital adder/subtractor.
The utility model discloses beneficial effect who has:
1. and comparing the difference value of the two sampling signals before and after, and if the difference value is less than a certain threshold value, only M-bit AD conversion is needed, so that the power consumption of single AD conversion is reduced.
2. By utilizing the autocorrelation of the input analog signal, the N-bit SARADC only needs to carry out M-bit AD conversion in one AD conversion, so that the conversion rate of the signal is improved.
3. By comparing the difference between the two previous sampling signals and the two subsequent sampling signals, if the difference is greater than a certain threshold (namely, a steep change occurs), the signals are considered as noise, so that the AD conversion is not needed, and the result of the last AD conversion is used as the output of the time, thereby achieving the effect of filtering the noise (the signal steep change).
Drawings
FIG. 1 is a signal diagram illustrating the presence of noise in the input signal of a conventional ADC;
fig. 2 is a schematic diagram of an embodiment of the present invention;
FIG. 3 is a schematic diagram of another operating state of the embodiment of FIG. 2;
fig. 4 is a schematic diagram of another embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
As shown in fig. 2 and 3, inside the dotted line frame are a conventional N-bit sar adc circuit, i.e., an AD conversion unit and a logic timing controller, and the digital signal converted and output by the AD conversion unit is used as a control signal supplied to the logic timing controller. The utility model discloses an innovation lies in having increased signal autocorrelation detecting element, has connected gradually the sampling and has kept ware, simulation subtracter, absolute value module, first comparator, and first comparator output control signal C1 connects zero-crossing comparator behind the simulation subtracter simultaneously, zero-crossing comparator output control signal C2. And an M-bit DAC is connected behind the absolute value module and is connected with the negative input end of a second comparator in the AD conversion unit. The signal autocorrelation detection unit also comprises an M-bit register, a digital adder/subtractor and an N-bit output register which are sequentially connected in the rear, wherein the output end of the M-bit register is connected with the input end of the M-bit DAC, and the N-bit register in the AD conversion unit is directly connected with the N-bit output register. C1 is used to control the switch in fig. 2, and C2 controls the digital adder/subtractor.
Example 1
FIG. 2 shows an operating state of the circuit, in which the first AD conversion is controlled by the logic timing controller to store the input analog signal into the sample holder, and SW3, SW5 and SW6 are closed to implement a complete N-bit AD conversion, the AD conversion result is stored into the N-bit register, and then SW3, SW5 and SW6 are opened; AD conversion is performed by the following steps from the second AD conversion,
SW1 is turned off, SW2 is turned on, SW3 to SW10 are turned off, the currently input analog signal is subtracted from the previously input analog signal stored in the sample hold circuit, the absolute value of the result is taken, and the sum is compared with the level Vref/2N-MComparing to generate a control signal C1, and judging whether the result is greater than zero by a zero-crossing comparator to generate a control signal C2;
if the C1 is 1, the SW4, the SW7 and the SW8 are closed, the SW3, the SW5 and the SW6 are opened, at this time, M-bit AD conversion is performed on the output voltage of the analog subtractor (after the M-bit DAC finishes voltage signal sampling, the SW2 and the SW7 are opened, and the SW1 is closed to store the currently input analog signal), and the conversion result is stored in the M-bit register; if the C1 is 0, switching off the SW2 and the SW7, switching on the SW1 to store the currently input analog signal, simultaneously switching off the SW4, the SW7 and the SW8, and switching on the SW3, the SW5 and the SW6, at the moment, carrying out complete N-bit AD conversion on the currently input analog signal, and storing a conversion result into an N-bit register;
if C1 is 1, SW9 is closed, SW10 is opened, if C2 is 1, the N-bit register and the M-bit register are added, if C2 is 0, the N-bit register and the M-bit register are subtracted, and the result is stored in an N-bit output register to be output; if C1 is 0, SW9 is opened, SW10 is closed, and the data in the N-bit register is directly stored into the N-bit output register for output;
if C1 is 1, assigning the data of the N-bit output register to the N-bit register; if C1 is 0, then there is no operation.
Fig. 3 shows another operation state of the present embodiment, which is different from fig. 2 in that C1 is not used as a signal for controlling the switches SW3, SW5 and SW 6. The principle is as follows:
first AD conversion is controlled by a logic time sequence controller to store input analog signals into a sampling retainer, SW3, SW5 and SW6 are closed to realize complete N-bit AD conversion, the AD conversion result is stored into an N-bit register, and then SW3, SW5 and SW6 are disconnected; AD conversion is performed by the following steps from the second AD conversion,
SW1 is turned off, SW2 is turned on, SW3 to SW10 are turned off, the currently input analog signal is subtracted from the previously input analog signal stored in the sample holder, and the result is subtracted from the level Vref/2N-MComparing to generate control signal C1, judging whether the result is greater than zero by zero-crossing comparator to generate control signal C2,
if the C1 is 1 (the input is an effective signal at this time), the SW4, the SW7 and the SW8 are closed, M-bit AD conversion is performed on the output voltage of the analog subtractor (after the M-bit DAC finishes voltage signal sampling, the SW2 and the SW7 are opened, and the SW1 is closed to store the currently input analog signal), and the conversion result is stored in an M-bit register; if C1 is 0 (the input is noise), SW2 and SW7 are turned off, SW1 is turned on to store the currently input analog signal, and SW4, SW7 and SW8 are turned off, so that the currently input analog signal is not subjected to AD conversion, but the result of the last AD conversion is directly used as the conversion result of the current time, that is, the data in the N-bit register is kept unchanged;
if the C1 is 1 (the input is an effective signal), the SW9 is closed, the SW10 is opened, if the C2 is 1, the N-bit register and the M-bit register are added, if the C2 is 0, the N-bit register and the M-bit register are subtracted, and the result is stored in the N-bit output register to be output; if C1 is 0 (the input is noise at this time), SW9 is opened, SW10 is closed, and the data in the N-bit register is directly stored in the N-bit output register for output;
if C1 is 1 (the input is valid signal at this time), assigning the data of the N-bit output register to the N-bit register; if C1 is 0 (the input is noise at this time), then there is no operation.
Example 2
As shown in fig. 4, the difference from embodiment 1 is that an N-bit DAC and an M-bit DAC are combined into one DAC, that is, an N-bit/M-bit DAC, the number of conversion bits thereof is controlled by a first control signal C1, first AD conversion is controlled by a logic timing controller to store the input analog signal in a sample holder, and SW3, SW5 and SW6 are closed to implement one complete N-bit AD conversion, the AD conversion result is stored in an N-bit register, and then SW3, SW5 and SW6 are opened; AD conversion is performed by the following steps from the second AD conversion,
SW1 is turned off, SW2 is turned on, SW3 to SW10 are turned off, the currently input analog signal is subtracted from the previously input analog signal stored in the sample hold circuit, the absolute value of the result is taken, and the sum is compared with the level Vref/2N-MComparing to generate a control signal C1, and judging whether the result is greater than zero by a zero-crossing comparator to generate a control signal C2;
if C1 is 1, M-bit DA conversion is realized by the N-bit/M-bit DAC, SW4, SW7 and SW8 are closed, SW3, SW5 and SW6 are opened, M-bit AD conversion is carried out on the output voltage of the analog subtractor at the moment (SW 2 and SW7 are opened after the M-bit DAC finishes voltage signal sampling, SW1 is closed to store the currently input analog signal), and the conversion result is stored in an M-bit register; if the C1 is 0, the N-bit/M-bit DAC realizes N-bit DA conversion, the SW2 and the SW7 are disconnected, the SW1 is closed to store the currently input analog signal, meanwhile, the SW4, the SW7 and the SW8 are disconnected, the SW3, the SW5 and the SW6 are closed, complete N-bit AD conversion is carried out on the currently input analog signal, and the conversion result is stored in an N-bit register;
if C1 is 1, SW9 is closed, SW10 is opened, if C2 is 1, the N-bit register and the M-bit register are added, if C2 is 0, the N-bit register and the M-bit register are subtracted, and the result is stored in an N-bit output register to be output; if C1 is 0, SW9 is opened, SW10 is closed, and the data in the N-bit register is directly stored into the N-bit output register for output;
if C1 is 1, assigning the data of the N-bit output register to the N-bit register; if C1 is 0, then there is no operation.
Similar to embodiment 1, when C1 is not used as a signal for controlling switches SW3, SW5 and SW6, the circuit has a function of filtering noise, and the principle is the same as embodiment 1 and is not repeated.
The utility model utilizes the initial A/D conversion to detect the approximate range of the slowly-changed input signal, thereby selectively reducing the digit conversion and reducing the ADC power consumption; meanwhile, the result of last AD conversion is used as the output of the time, so that the effect of filtering noise (abrupt signal change) is achieved.
Claims (7)
1. A successive approximation type analog-to-digital conversion circuit based on signal autocorrelation comprises an AD conversion unit and a logic time sequence controller, wherein the AD conversion unit generates digital signals and provides the digital signals for the logic time sequence controller, and the successive approximation type analog-to-digital conversion circuit is characterized by further comprising a signal autocorrelation detection unit, the logic time sequence controller provides control signals for the AD conversion unit and the signal autocorrelation detection unit, and the signal autocorrelation detection unit comprises the following parts: the digital adder-subtractor comprises a sampling holder, an analog subtractor, an absolute value module, an M-bit DAC, a first comparator, a zero-crossing comparator, a digital adder-subtractor, an M-bit register, an N-bit output register, a first switch, a second switch, a seventh switch, an eighth switch, a ninth switch and a tenth switch; wherein,
the sampling holder, the analog subtractor and the absolute value module are electrically connected in sequence, the output end of the analog subtractor is simultaneously connected with the zero-crossing comparator, the output end of the absolute value module is simultaneously connected with the negative input ends of the M-bit DAC and the first comparator, the positive input end of the first comparator inputs a first reference signal, the output end of the M-bit register is connected to the digital adder/subtractor, the output end of the digital adder/subtractor is connected with the N-bit output register through a ninth switch, the output end of the M-bit register is also connected with the M-bit DAC, and the tenth switch is connected with the AD conversion unit; the first switch is located before the sample holder, the second switch is located before the analog subtractor, the seventh switch is located between the absolute value block and the M-bit DAC, and the eighth switch is located between the M-bit DAC and the AD conversion unit.
2. The signal autocorrelation-based successive approximation type analog-to-digital conversion circuit as claimed in claim 1, wherein: the output of the first comparator is a first control signal for controlling the seventh switch, the eighth switch, the ninth switch, the tenth switch and the switch in the AD conversion unit, and the output of the zero-crossing comparator is a second control signal for controlling the digital adder/subtractor.
3. The signal autocorrelation-based successive approximation type analog-to-digital conversion circuit as claimed in claim 1, wherein: the output ends of the first comparator and the zero-crossing comparator are connected to the logic time sequence controller, and the logic time sequence controller outputs a first control signal and a second control signal.
4. The signal autocorrelation-based successive approximation type analog-to-digital conversion circuit as claimed in claim 1, 2 or 3, wherein: the AD conversion unit comprises an N-bit DAC, a second comparator, an N-bit register, a third switch, a fourth switch, a fifth switch and a sixth switch, wherein an output signal of the N-bit DAC enters a negative input end of the second comparator, an output end of the N-bit register is connected to the N-bit DAC, meanwhile, the output end of the N-bit register is connected with the N-bit output register through the tenth switch, and a reference signal is input to a positive input end of the second comparator; the third switch and the fourth switch are connected in parallel to the positive input end of the second comparator and are controlled by a first control signal; the reference signal entering the positive input of the second comparator is the second reference signal when the third switch is closed and the fourth switch is open, the reference signal entering the positive input of the second comparator is the first reference signal when the third switch is open and the fourth switch is closed, the fifth switch is located before the N-bit DAC, the sixth switch is located between the N-bit DAC and the negative input of the second comparator, and the eighth switch and the sixth switch are coupled to the negative input of the second comparator.
5. The signal autocorrelation-based successive approximation type analog-to-digital conversion circuit of claim 3, wherein: the value of M is less than the value of N.
6. The signal autocorrelation-based successive approximation type analog-to-digital conversion circuit of claim 4, wherein: 1/2 where the first reference signal is a second reference signalN-M。
7. The signal autocorrelation-based successive approximation type analog-to-digital conversion circuit as claimed in claim 1, wherein: the analog-to-digital converter comprises an AD conversion unit and a logic time sequence controller, wherein the AD conversion unit generates a logic time sequence signal and provides the logic time sequence signal for the logic time sequence controller, the AD conversion unit comprises an N/M DAC, a second comparator, an N register, a third switch, a fourth switch, a fifth switch, a sixth switch and an eighth switch, an output signal of the N/M DAC enters a negative input end of the second comparator, an output end of the N register is connected to the N/M DAC through the sixth switch, and a reference signal is input to a positive input end of the second comparator; the third switch and the fourth switch are connected in parallel to the positive input end of the second comparator and are controlled by a first control signal; when the third switch is closed and the fourth switch is opened, the reference signal entering the positive input terminal of the second comparator is the second reference signal, when the third switch is opened and the fourth switch is closed, the reference signal entering the positive input terminal of the second comparator is the first reference signal, and the fifth switch is positioned in front of the N-bit/M-bit DAC; the logic timing controller provides control signals for the AD conversion unit and the signal autocorrelation detection unit, and the signal autocorrelation detection unit comprises the following parts: the digital adder-subtractor comprises a sampling holder, an analog subtractor, an absolute value module, a first comparator, a zero-crossing comparator, a digital adder-subtractor, an N-bit output register, a first switch, a second switch, a seventh switch, a ninth switch and a tenth switch; wherein,
the sampling holder, the analog subtractor and the absolute value module are electrically connected in sequence, the output end of the analog subtractor is simultaneously connected with the zero-crossing comparator, the output end of the absolute value module is simultaneously connected with the negative input ends of the N-bit/M-bit DAC and the first comparator, the positive input end of the first comparator inputs a first reference signal, the output end of the M-bit register is connected to the digital adder/subtractor, the output end of the digital adder/subtractor is connected with the N-bit output register through a ninth switch, the output end of the M-bit register is connected with the N-bit/M-bit DAC through an eighth switch, and the tenth switch is located between the N-bit register and the N-bit output register; the first switch is located before the sample holder, the second switch is located before the analog subtractor, the seventh switch is located between the absolute value module and the N-bit/M-bit DAC, the output of the first comparator is a first control signal for controlling all switches except the first switch and the second switch, and the output of the zero-crossing comparator is a second control signal for controlling the digital adder/subtractor.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105071810A (en) * | 2015-07-16 | 2015-11-18 | 南京邮电大学 | Successive approximation register analog-to-digital conversion circuit based on signal autocorrelation |
| CN108462479A (en) * | 2018-02-05 | 2018-08-28 | 南京邮电大学 | Image-reject filter based on modified Gm-C and its construction method |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105071810A (en) * | 2015-07-16 | 2015-11-18 | 南京邮电大学 | Successive approximation register analog-to-digital conversion circuit based on signal autocorrelation |
| CN105071810B (en) * | 2015-07-16 | 2018-04-20 | 南京邮电大学 | Successive approximation modulus conversion circuit based on signal autocorrelation |
| CN108462479A (en) * | 2018-02-05 | 2018-08-28 | 南京邮电大学 | Image-reject filter based on modified Gm-C and its construction method |
| CN108462479B (en) * | 2018-02-05 | 2021-06-18 | 南京邮电大学 | Image rejection filter based on improved Gm-C and construction method thereof |
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Assignee: Jiangsu Nanyou IOT Technology Park Ltd. Assignor: Nanjing Post & Telecommunication Univ. Contract record no.: 2016320000210 Date of cancellation: 20180116 |
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| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20151209 Termination date: 20180716 |