CN204859152U - Successive Approximation Analog-to-Digital Conversion Circuit Based on Signal Autocorrelation - Google Patents

Abstract

The utility model discloses a successive approximation analog-to-digital conversion circuit based on signal autocorrelation, which is different from the traditional SAR? Compared with the ADC circuit, the signal autocorrelation detection unit is added. By comparing the difference between the two sampling signals before and after, if it is less than a certain threshold, only a small number of AD conversions are required, thereby reducing the single-shot Power consumption of AD conversion. The utility model obviously improves the conversion speed of the ADC, reduces the power consumption, and simultaneously achieves the effect of filtering out the noise.

Description

Successive Approximation Analog-to-Digital Conversion Circuit Based on Signal Autocorrelation

technical field

The utility model relates to the technical field of electronic circuits, in particular to a successive approximation analog-to-digital conversion circuit based on signal autocorrelation.

Background technique

In the integrated circuit system, the A/D converter is an important bridge connecting the analog system and the digital signal processing system. The wide application of digital signal processing technology in the fields of high-resolution images, high-fidelity audio signals and wireless The demand for advanced ADC (Analog-to-digital converter, analog-to-digital converter) is increasing day by day, especially for ADCs with high speed, high precision, low power consumption and low cost. SAR (Successive Approximation Register, successive approximation type) A/D conversion circuit has a higher resolution than other types of ADCs, a small area, and relatively low power consumption, but the speed is slow.

With the rise of application fields such as portable devices and wearable devices, application systems have higher and higher requirements for data processing speed and low power consumption. As a bridge connecting analog signals and digital signals in the application system, the analog-to-digital converter is an indispensable and important part. Reducing the power consumption of the analog-to-digital converter is the direction that engineers have been working hard on. In addition, the signals in the actual application system are generally continuously changing slowly changing signals, so for the case where the conversion rate is much higher than the frequency of the output signal, the value of the ADC input analog signal at the two sampling times should have little difference. If the value is larger, it can be considered as noise and thus filtered out. Figure 1 shows a schematic diagram of noise in the input signal of the ADC. The solid line is the input analog signal, and the dotted arrow is each signal sampling. When there is a large difference between the two sampling signals before and after, it is considered that there is noise.

Contents of the invention

In view of the fact that SARADC has low signal conversion speed and high power consumption, and does not have the function of filtering noise, the purpose of this utility model is to provide an analog-to-digital conversion circuit based on the existing high-precision ADC, improve the ADC speed, Reduce power consumption, and enable the ADC itself to have a certain noise filtering function.

A successive approximation analog-to-digital conversion circuit based on signal autocorrelation, including an AD conversion unit and a logic timing controller, the AD conversion unit generates a logic timing signal, which is provided to the logic timing controller, and also includes signal autocorrelation detection unit, the logic timing controller provides control signals for the AD conversion unit and the signal autocorrelation detection unit, and the signal autocorrelation detection unit includes the following parts: sample holder, analog subtractor, absolute value module, M-bit DAC , a first comparator, a zero-crossing comparator, a digital adder/subtractor, an M-bit register, an N-bit output register, and a first switch, a second switch, a seventh switch, an eighth switch, a ninth switch, and a tenth switch; Wherein, the sample-and-hold device, the analog subtractor and the absolute value module are electrically connected in sequence, the output terminal of the analog subtractor is connected with the zero-crossing comparator at the same time, and the output terminal of the absolute value module Simultaneously connected with the negative input terminal of the M-bit DAC and the first comparator, the positive input terminal of the first comparator inputs the first reference signal, and the output terminal of the M-bit register is connected to the digital plus /subtractor, the output end of the digital adder/subtractor is connected to the N-bit output register through the ninth switch, the output end of the M-bit register is also connected to the M-bit DAC, and the tenth switch is connected to the M-bit DAC. The AD conversion unit is connected; the first switch is located before the sample-and-hold device, the second switch is located before the analog subtracter, and the seventh switch is located between the absolute value module and the M-bit DAC Between, the eighth switch is located between the M-bit DAC and the AD conversion unit.

In some cases, the output of the first comparator is a first control signal, which is used to control the seventh switch, the eighth switch, the ninth switch, the tenth switch and the switches in the AD conversion unit, so The output of the zero-crossing comparator is the second control signal, which is used to control the digital adder/subtractor.

In another case, the output terminals of the first comparator and the zero-crossing comparator are both connected to the logic timing controller, and the logic timing controller outputs the first control signal and the second control signal.

The AD conversion unit includes an N-bit DAC, a second comparator, an N-bit register, a third switch, a fourth switch, a fifth switch, and a sixth switch, and the output signal of the N-bit DAC enters the second comparator The negative input end of the N-bit register, the output end of the N-bit register is connected to the N-bit DAC, and is connected to the N-bit output register through the tenth switch, and the positive input end of the second comparator inputs a reference signal ; The third switch and the fourth switch are connected in parallel to the positive input terminal of the second comparator, controlled by the first control signal; when the third switch is closed and the fourth switch is open, enter the second comparator The reference signal at the positive input terminal is the second reference signal, when the third switch is open and the fourth switch is closed, the reference signal entering the positive input terminal of the second comparator is the first reference signal, and the fifth switch is at the Before the N-bit DAC, the sixth switch is located between the N-bit DAC and the negative input terminal of the second comparator, and the eighth switch and the sixth switch are connected in parallel to the second comparator the negative input terminal.

The value of M is smaller than the value of N.

The first reference signal is 1/2 ^NM of the second reference signal.

The utility model also provides another successive approximation analog-to-digital conversion circuit based on signal autocorrelation, including an AD conversion unit and a logic timing controller, and the AD conversion unit generates a logic timing signal, which is provided to the logic timing controller , the AD conversion unit includes an N-bit/M-bit DAC, a second comparator, an N-bit register, a third switch, a fourth switch, a fifth switch, a sixth switch, and an eighth switch, and the N-bit/M-bit The output signal of the DAC enters the negative input terminal of the second comparator, the output terminal of the N-bit register is connected to the N-bit/M-bit DAC through the sixth switch, and the positive input terminal of the second comparator is input Reference signal; the third switch and the fourth switch are connected in parallel to the positive input terminal of the second comparator, controlled by the first control signal; when the third switch is closed and the fourth switch is open, the second The reference signal at the positive input terminal of the comparator is the second reference signal, when the third switch is open and the fourth switch is closed, the reference signal entering the positive input terminal of the second comparator is the first reference signal, and the fifth switch is at Before the N bit/M bit DAC; also include a signal autocorrelation detection unit, the logic timing controller provides control signals for the AD conversion unit and the signal autocorrelation detection unit, and the signal autocorrelation detection unit includes the following Section: sample-and-hold, analog subtracter, absolute value block, first comparator, zero-crossing comparator, digital adder/subtractor, N-bit output register, and first switch, second switch, seventh switch, ninth switch and the tenth switch; where,

The sample-and-hold device, the analog subtractor and the absolute value module are electrically connected in sequence, the output terminal of the analog subtractor is connected to the zero-crossing comparator at the same time, and the output terminal of the absolute value module is connected to the The N-bit/M-bit DAC is connected to the negative input terminal of the first comparator at the same time, the positive input terminal of the first comparator inputs the first reference signal, and the output terminal of the M-bit register is connected to the digital An adder/subtractor, the output end of the digital adder/subtractor is connected to the N-bit output register through a ninth switch, and the output end of the M-bit register is connected to the N-bit/M-bit DAC through an eighth switch , the tenth switch is located between the N-bit register and the N-bit output register; the first switch is located before the sample-and-hold device, the second switch is located before the analog subtractor, and the The seventh switch is located between the absolute value module and the N-bit/M-bit DAC, and the output of the first comparator is a first control signal, which is used to control all switches except the first switch and the second switch , the output of the zero-crossing comparator is a second control signal used to control the digital adder/subtractor.

The beneficial effect that the utility model has:

1. Comparing the difference between two sampling signals before and after, if it is less than a certain threshold, only M-bit AD conversion is required, thereby reducing the power consumption of a single AD conversion.

2. Utilizing the autocorrelation of the input analog signal, the N-bit SARADC actually only needs to perform M-bit AD conversion during an AD conversion, so the signal conversion rate is improved.

3. By comparing the difference between the two sampling signals before and after, if it is greater than a certain threshold (that is, there is a sudden change), it is considered to be noise, so that AD conversion is not required, but the result of the last AD conversion is used as this Times of output, so as to achieve the effect of filtering noise (signal abrupt change).

Description of drawings

FIG. 1 is a schematic diagram of a signal in which noise exists in an input signal of a traditional ADC;

Fig. 2 is a schematic diagram of an embodiment of the utility model;

Fig. 3 is a schematic diagram of another working state of the embodiment in Fig. 2;

Fig. 4 is a schematic diagram of another embodiment of the utility model.

Detailed ways

In order to make the purpose, technical solution and advantages of the utility model clearer, the utility model will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the utility model, and are not intended to limit the utility model.

As shown in Figure 2 and Figure 3, the traditional N-bit SARADC circuit in the dotted line box is the AD conversion unit and the logic timing controller. The digital signal converted and output by the AD conversion unit is used as the control for the logic timing controller Signal. The innovation of the utility model lies in the addition of a signal autocorrelation detection unit, which is sequentially connected with a sample holder, an analog subtracter, an absolute value module, and a first comparator. The first comparator outputs a control signal C1, and the analog subtractor is connected simultaneously A zero-crossing comparator, the zero-crossing comparator outputs a control signal C2. An M-bit DAC is connected behind the absolute value module, and the M-bit DAC is connected to the negative input terminal of the second comparator in the AD conversion unit. The signal autocorrelation detection unit also includes an M-bit register, a digital adder/subtractor and an N-bit output register connected in sequence, wherein the output of the M-bit register is connected to the M-bit DAC input, and the N-bit in the AD conversion unit register is directly connected to the N-bit output register. C1 is used to control the switch in Figure 2, and C2 controls the digital adder/subtractor.

Example 1

Figure 2 shows a working state of this circuit. The first AD conversion is controlled by the logic sequence controller to store the input analog signal into the sample-and-hold device, and close SW3, SW5 and SW6 to realize a complete N-bit AD Conversion, the AD conversion result is stored in the N-bit register, and then SW3, SW5 and SW6 are disconnected; from the second AD conversion, the following steps are used for AD conversion,

SW1 is disconnected, SW2 is closed, SW3~SW10 are disconnected, the current input analog signal is subtracted from the last input analog signal stored in the sample-and-hold circuit, and the absolute value of the result is compared with the level V _ref /2 ^NM The comparison generates the control signal C1, and at the same time, the zero-crossing comparator judges whether the result is greater than zero to generate the control signal C2;

If C1 is 1, then SW4, SW7, and SW8 are closed, and SW3, SW5, and SW6 are open. At this time, M-bit AD conversion is performed on the output voltage of the analog subtractor (when the M-bit DAC completes voltage signal sampling, switch off SW2 and SW7, close SW1 to store the current input analog signal), store the conversion result in the M-bit register; if C1 is 0, open SW2 and SW7, close SW1 to store the current input analog signal, and at the same time SW4, SW7 and SW8 is disconnected, SW3, SW5 and SW6 are closed, at this time, a complete N-bit AD conversion is performed on the current input analog signal, and the conversion result is stored in the N-bit register;

If C1 is 1, SW9 is closed, SW10 is open, if C2 is 1, the N-bit register and the M-bit register are added, if C2 is 0, the N-bit register and the M-bit register are subtracted, and the result is stored Input the N-bit output register for output; if C1 is 0, then SW9 is disconnected, SW10 is closed, and the data in the N-bit register is directly stored in the N-bit output register for output;

If C1 is 1, assign the data of the N-bit output register to the N-bit register; if C1 is 0, there is no operation.

FIG. 3 shows another working state of this embodiment. The difference from FIG. 2 is that C1 is not used as a signal for controlling switches SW3, SW5 and SW6. The principle is as follows:

The first AD conversion is controlled by the logic timing controller to store the input analog signal into the sample-and-hold device, and close SW3, SW5 and SW6 to realize a complete N-bit AD conversion, and the AD conversion result is stored in the N-bit register, and then Disconnect SW3, SW5 and SW6; from the second AD conversion, use the following steps to perform AD conversion,

SW1 is disconnected, SW2 is closed, SW3~SW10 are disconnected, the current input analog signal is subtracted from the last input analog signal stored in the sample-and-hold, and the absolute value of the result is compared with the level V _ref /2 ^NM The comparison generates the control signal C1, and at the same time, the zero-crossing comparator judges whether the result is greater than zero to generate the control signal C2.

If C1 is 1 (the input is a valid signal at this time), then SW4, SW7 and SW8 are closed, and M-bit AD conversion is performed on the output voltage of the analog subtracter (when the M-bit DAC completes the voltage signal sampling, open SW2 and SW7, close SW1 stores the current input analog signal), and stores the conversion result into the M-bit register; if C1 is 0 (the input is noise at this time), disconnect SW2 and SW7, close SW1 to store the current input analog signal, and at the same time SW4, SW7 and SW8 are disconnected. At this time, the AD conversion of the current input analog signal is not performed, but the result of the last AD conversion is directly used as the conversion result of this time, that is, the data in the N-bit register remains unchanged;

If C1 is 1 (the input is a valid signal at this time), SW9 is closed, and SW10 is opened. If C2 is 1, the N-bit register and the M-bit register are added. If C2 is 0, the N-bit register and the M-bit register are added. Perform a subtraction operation, and store the result in the N-bit output register for output; if C1 is 0 (the input is noise at this time), then SW9 is turned off, SW10 is closed, and the data in the N-bit register is directly stored in the N-bit output register output;

If C1 is 1 (the input is a valid signal at this time), assign the data of the N-bit output register to the N-bit register; if C1 is 0 (the input is noise at this time), there is no operation.

Example 2

As shown in Figure 4, the difference from Embodiment 1 is that the N-bit DAC and the M-bit DAC are combined into one DAC, that is, the N-bit/M-bit DAC, the number of conversion bits of which is controlled by the first control signal C1, the first AD The conversion is controlled by a logic sequence controller, and the input analog signal is stored in the sample-and-hold device, and SW3, SW5, and SW6 are closed to realize a complete N-bit AD conversion, and the AD conversion result is stored in the N-bit register, and then SW3 , SW5 and SW6 are disconnected; from the second AD conversion, the following steps are used for AD conversion,

SW1 is disconnected, SW2 is closed, SW3~SW10 are disconnected, the current input analog signal is subtracted from the last input analog signal stored in the sample-and-hold circuit, and the absolute value of the result is compared with the level V _ref /2 ^NM The comparison generates the control signal C1, and at the same time, the zero-crossing comparator judges whether the result is greater than zero to generate the control signal C2;

If C1 is 1, the N-bit/M-bit DAC realizes M-bit DA conversion, SW4, SW7, and SW8 are closed, and SW3, SW5, and SW6 are opened. At this time, M-bit AD conversion is performed on the output voltage of the analog subtractor (when After the M-bit DAC completes the voltage signal sampling, disconnect SW2 and SW7, close SW1 to store the current input analog signal), and store the conversion result in the M-bit register; if C1 is 0, the N-bit/M-bit DAC realizes N-bit DA Convert, open SW2 and SW7, close SW1 to store the current input analog signal, at the same time SW4, SW7 and SW8 are open, SW3, SW5 and SW6 are closed, at this time complete N-bit AD for the current input analog signal Convert, store the conversion result in an N-bit register;

If C1 is 1, SW9 is closed, SW10 is open, if C2 is 1, the N-bit register and the M-bit register are added, if C2 is 0, the N-bit register and the M-bit register are subtracted, and the result is stored Input the N-bit output register for output; if C1 is 0, then SW9 is disconnected, SW10 is closed, and the data in the N-bit register is directly stored in the N-bit output register for output;

If C1 is 1, assign the data of the N-bit output register to the N-bit register; if C1 is 0, there is no operation.

Similar to Embodiment 1, when C1 is not used as a signal for controlling the switches SW3, SW5 and SW6, the circuit has the function of filtering noise, and the principle is the same as that of Embodiment 1, which will not be repeated here.

The utility model uses the initial A/D conversion to detect the approximate range of the slow-changing input signal, thereby selectively reducing the conversion of digits and reducing the power consumption of the ADC; at the same time, the result of the last AD conversion is used as the output of this time, thereby To achieve the effect of filtering noise (signal abrupt change).

Claims (7)

1. A successive approximation type analog-to-digital conversion circuit based on signal autocorrelation comprises an AD conversion unit and a logic time sequence controller, wherein the AD conversion unit generates digital signals and provides the digital signals for the logic time sequence controller, and the successive approximation type analog-to-digital conversion circuit is characterized by further comprising a signal autocorrelation detection unit, the logic time sequence controller provides control signals for the AD conversion unit and the signal autocorrelation detection unit, and the signal autocorrelation detection unit comprises the following parts: the digital adder-subtractor comprises a sampling holder, an analog subtractor, an absolute value module, an M-bit DAC, a first comparator, a zero-crossing comparator, a digital adder-subtractor, an M-bit register, an N-bit output register, a first switch, a second switch, a seventh switch, an eighth switch, a ninth switch and a tenth switch; wherein,

the sampling holder, the analog subtractor and the absolute value module are electrically connected in sequence, the output end of the analog subtractor is simultaneously connected with the zero-crossing comparator, the output end of the absolute value module is simultaneously connected with the negative input ends of the M-bit DAC and the first comparator, the positive input end of the first comparator inputs a first reference signal, the output end of the M-bit register is connected to the digital adder/subtractor, the output end of the digital adder/subtractor is connected with the N-bit output register through a ninth switch, the output end of the M-bit register is also connected with the M-bit DAC, and the tenth switch is connected with the AD conversion unit; the first switch is located before the sample holder, the second switch is located before the analog subtractor, the seventh switch is located between the absolute value block and the M-bit DAC, and the eighth switch is located between the M-bit DAC and the AD conversion unit.

2. The signal autocorrelation-based successive approximation type analog-to-digital conversion circuit as claimed in claim 1, wherein: the output of the first comparator is a first control signal for controlling the seventh switch, the eighth switch, the ninth switch, the tenth switch and the switch in the AD conversion unit, and the output of the zero-crossing comparator is a second control signal for controlling the digital adder/subtractor.

3. The signal autocorrelation-based successive approximation type analog-to-digital conversion circuit as claimed in claim 1, wherein: the output ends of the first comparator and the zero-crossing comparator are connected to the logic time sequence controller, and the logic time sequence controller outputs a first control signal and a second control signal.

4. The signal autocorrelation-based successive approximation type analog-to-digital conversion circuit as claimed in claim 1, 2 or 3, wherein: the AD conversion unit comprises an N-bit DAC, a second comparator, an N-bit register, a third switch, a fourth switch, a fifth switch and a sixth switch, wherein an output signal of the N-bit DAC enters a negative input end of the second comparator, an output end of the N-bit register is connected to the N-bit DAC, meanwhile, the output end of the N-bit register is connected with the N-bit output register through the tenth switch, and a reference signal is input to a positive input end of the second comparator; the third switch and the fourth switch are connected in parallel to the positive input end of the second comparator and are controlled by a first control signal; the reference signal entering the positive input of the second comparator is the second reference signal when the third switch is closed and the fourth switch is open, the reference signal entering the positive input of the second comparator is the first reference signal when the third switch is open and the fourth switch is closed, the fifth switch is located before the N-bit DAC, the sixth switch is located between the N-bit DAC and the negative input of the second comparator, and the eighth switch and the sixth switch are coupled to the negative input of the second comparator.

5. The signal autocorrelation-based successive approximation type analog-to-digital conversion circuit of claim 3, wherein: the value of M is less than the value of N.

6. The signal autocorrelation-based successive approximation type analog-to-digital conversion circuit of claim 4, wherein: 1/2 where the first reference signal is a second reference signal^N-M。

7. The signal autocorrelation-based successive approximation type analog-to-digital conversion circuit as claimed in claim 1, wherein: the analog-to-digital converter comprises an AD conversion unit and a logic time sequence controller, wherein the AD conversion unit generates a logic time sequence signal and provides the logic time sequence signal for the logic time sequence controller, the AD conversion unit comprises an N/M DAC, a second comparator, an N register, a third switch, a fourth switch, a fifth switch, a sixth switch and an eighth switch, an output signal of the N/M DAC enters a negative input end of the second comparator, an output end of the N register is connected to the N/M DAC through the sixth switch, and a reference signal is input to a positive input end of the second comparator; the third switch and the fourth switch are connected in parallel to the positive input end of the second comparator and are controlled by a first control signal; when the third switch is closed and the fourth switch is opened, the reference signal entering the positive input terminal of the second comparator is the second reference signal, when the third switch is opened and the fourth switch is closed, the reference signal entering the positive input terminal of the second comparator is the first reference signal, and the fifth switch is positioned in front of the N-bit/M-bit DAC; the logic timing controller provides control signals for the AD conversion unit and the signal autocorrelation detection unit, and the signal autocorrelation detection unit comprises the following parts: the digital adder-subtractor comprises a sampling holder, an analog subtractor, an absolute value module, a first comparator, a zero-crossing comparator, a digital adder-subtractor, an N-bit output register, a first switch, a second switch, a seventh switch, a ninth switch and a tenth switch; wherein,

the sampling holder, the analog subtractor and the absolute value module are electrically connected in sequence, the output end of the analog subtractor is simultaneously connected with the zero-crossing comparator, the output end of the absolute value module is simultaneously connected with the negative input ends of the N-bit/M-bit DAC and the first comparator, the positive input end of the first comparator inputs a first reference signal, the output end of the M-bit register is connected to the digital adder/subtractor, the output end of the digital adder/subtractor is connected with the N-bit output register through a ninth switch, the output end of the M-bit register is connected with the N-bit/M-bit DAC through an eighth switch, and the tenth switch is located between the N-bit register and the N-bit output register; the first switch is located before the sample holder, the second switch is located before the analog subtractor, the seventh switch is located between the absolute value module and the N-bit/M-bit DAC, the output of the first comparator is a first control signal for controlling all switches except the first switch and the second switch, and the output of the zero-crossing comparator is a second control signal for controlling the digital adder/subtractor.