CN111934687A - High-energy-efficiency analog-to-digital converter and control method thereof - Google Patents

High-energy-efficiency analog-to-digital converter and control method thereof Download PDF

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CN111934687A
CN111934687A CN202011095330.5A CN202011095330A CN111934687A CN 111934687 A CN111934687 A CN 111934687A CN 202011095330 A CN202011095330 A CN 202011095330A CN 111934687 A CN111934687 A CN 111934687A
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capacitor
reference voltage
setting
comparison
weighting
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CN111934687B (en
Inventor
胡云峰
陈李胜
胡乐星
文毅
陈卉
张华斌
周锦鹏
李华炎
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Shenzhen Legendary Technology Co ltd
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University of Electronic Science and Technology of China Zhongshan Institute
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/002—Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed

Abstract

The invention discloses an energy-efficient analog-to-digital converter and a control method thereof, wherein the energy-efficient analog-to-digital converter comprises a first input end, a second input end, a capacitor array analog-to-digital converter, a comparator and a successive approximation register, wherein the capacitor array analog-to-digital converter comprises a normal phase capacitor array and a reverse phase capacitor array; the positive phase capacitor array comprises a first capacitor array and a second capacitor array, the reverse phase capacitor array comprises a third capacitor array and a fourth capacitor array, and the reverse phase capacitor array comprises a third capacitor array and a fourth capacitor array. According to the invention, the number of capacitors with high capacitance values can be reduced by multiplexing the second capacitor array and the fourth capacitor array, so that the purposes of reducing the process size of the capacitor array analog-to-digital converter and reducing the power consumption of the capacitor array analog-to-digital converter are achieved. The invention can be widely applied to the technical field of electronic circuits.

Description

High-energy-efficiency analog-to-digital converter and control method thereof
Technical Field
The invention relates to the technical field of electronic circuits, in particular to an energy-efficient analog-to-digital converter and a control method thereof.
Background
The successive approximation type analog-to-digital converter is an analog-to-digital converter structure with medium and high precision, medium conversion rate and low power consumption, and mainly comprises an analog-to-digital converter, a comparator and a successive approximation register, wherein when the structure of the analog-to-digital converter is realized by adopting a capacitor array, the capacitor array is realized by adopting a binary weighted capacitor array, as the capacitance value of the binary weighted capacitor array is exponentially increased, the capacitance value of the capacitor presents a situation of rapid explosion increase along with the increase of the digits of the successive approximation type analog-to-digital converter, the volume of the capacitor is further increased (generally, the larger the capacitance value of the capacitor is), the difficulty is undoubtedly brought to the manufacturing process of the successive approximation type analog-to-digital converter, in addition, as the capacitance value of the capacitor presents the exponential increase, under the condition that the capacitance value, the more power is consumed.
Disclosure of Invention
In order to solve the above technical problems, an object of the present invention is to provide an energy efficient analog to digital converter and a control method thereof.
In a first aspect, an embodiment of the present invention provides an energy-efficient analog-to-digital converter, including a first input end, a second input end, a capacitor array analog-to-digital converter, a comparator, and a successive approximation shift register, where the capacitor array analog-to-digital converter includes a normal-phase capacitor array and a reverse-phase capacitor array;
the positive phase capacitor array comprises a first capacitor array and a second capacitor array, the first capacitor array comprises N-4 first weighting capacitors, and the capacitance value of the ith first weighting capacitor is 2iC, wherein i is more than or equal to 1 and less than or equal to N-4, N is the digit of the capacitor array analog-to-digital converter and is more than or equal to 5, C represents a unit capacitor, and the second capacitor array comprises a first capacitor and a second capacitor;
the reverse-phase capacitor array comprises a third capacitor array and a fourth capacitor array, the third capacitor array comprises N-4 second weighting capacitors, and the capacitance value of the ith second weighting capacitor is 2iC, wherein i is more than or equal to 1 and less than or equal to N-4, N is the digit of the capacitor array analog-to-digital converter and is more than or equal to 5, C represents a unit capacitor, and the fourth capacitor array comprises a third capacitor and a fourth capacitor;
the upper plate of the first capacitor is connected to a first reference voltage or a second reference voltage or ground, the upper plate of the second capacitor is connected to the first reference voltage or the second reference voltage or ground, the lower plate of the first capacitor is connected to the positive input end of the comparator, the lower plate of the first capacitor is also connected to the first input end, the lower plate of the second capacitor is connected to the positive input end of the comparator, and the lower plate of the second capacitor is also connected to the first input end;
the upper plate of each first weighting capacitor is connected to a first reference voltage or ground, the lower plate of each first weighting capacitor is connected to a first input end, and the lower plate of each first weighting capacitor is also connected to the non-inverting input end of a comparator;
the upper plate of the third capacitor is connected to a first reference voltage or a second reference voltage or ground, the upper plate of the fourth capacitor is connected to the first reference voltage or the second reference voltage or ground, the lower plate of the third capacitor is connected to the inverting input end of the comparator, the lower plate of the third capacitor is also connected to the second input end, the lower plate of the fourth capacitor is connected to the inverting input end of the comparator, and the lower plate of the fourth capacitor is also connected to the second input end;
the upper plate of each second weighting capacitor is connected to a first reference voltage or ground, the lower plate of each second weighting capacitor is connected to a second input end, and the lower plate of each second weighting capacitor is also connected to the inverting input end of the comparator;
and the output end of the comparator is connected with the input end of the successive approximation shift register.
Further, the high-energy-efficiency analog-to-digital converter further comprises a sampling switch, the sampling switch comprises a first sampling switch and a second sampling switch, one end of the first sampling switch is connected with the first input end, the other end of the first sampling switch is connected with the input end of the positive phase capacitor array, one end of the second sampling switch is connected with the second input end, and the other end of the second sampling switch is connected with the input end of the negative phase capacitor array.
Further, the positive phase capacitor array also comprises a plurality of bidirectional switches and three-way switches;
connecting the upper plate of each first weighting capacitor to a first reference voltage or ground through the bidirectional switch;
the upper plate of the first capacitor is connected to a first reference voltage or a second reference voltage or ground through the three-way switch, and the upper plate of the second capacitor is connected to the first reference voltage or the second reference voltage or ground.
Further, the positive phase capacitor array also comprises a plurality of bidirectional switches and three-way switches;
connecting the upper plate of each first weighting capacitor to a first reference voltage or ground through the bidirectional switch;
the upper plate of the first capacitor is connected to a first reference voltage or a second reference voltage or ground through the three-way switch, and the upper plate of the second capacitor is connected to the first reference voltage or the second reference voltage or ground.
Furthermore, the inverse capacitor array also comprises a plurality of bidirectional switches and three-way switches;
the upper plate of each second weighting capacitor is connected to a first reference voltage or ground through the bidirectional switch;
the upper plate of the third capacitor is connected to the first reference voltage or the second reference voltage or the ground through the three-way switch, and the upper plate of the fourth capacitor is connected to the first reference voltage or the second reference voltage or the ground.
In a second aspect, the present application provides a control method applied to the above-mentioned high-energy-efficiency analog-to-digital converter, including the following steps:
A. sampling: setting the reference voltage of the (N-4) th first weighting capacitor as ground, setting the reference voltage of the first weighting capacitors in the first capacitor array except the (N-4) th first weighting capacitor as a first reference voltage, setting the reference voltage of the first capacitor as a first reference voltage, and setting the reference voltage of the second capacitor as a first reference voltage;
setting the reference voltage of the (N-4) th second weighting capacitor as ground, setting the reference voltage of the second weighting capacitors except the (N-4) th second weighting capacitor in the third capacitor array as a first reference voltage, setting the reference voltage of the third capacitor as the first reference voltage, and setting the reference voltage of the fourth capacitor as the first reference voltage;
differential signals enter the capacitor array analog-to-digital converter from the first input end and the second input end to obtain a positive phase holding signal and a negative phase holding signal;
B. comparison 1: the comparator compares the positive phase holding signal and the negative phase holding signal for the first time and outputs a first comparison result D (1);
C. comparison at the 2 nd time: according to the result of the first comparison D (1),
when D (1) =1, setting the reference voltage of the (N-4) th second weighting capacitor as the first reference voltage;
when D (1) =0, setting the reference voltage of the (N-4) th first weighting capacitor as a first reference voltage;
the comparator performs the 2 nd comparison and outputs a 2 nd comparison result D (2);
D. the jth comparison: according to the j-1 th comparison result D (j-1), wherein j is more than or equal to 3 and less than or equal to N-3, and N is more than 5 as a constraint condition,
when D (j-1) =1, setting the reference voltage of the (N-2-j) th first weighting capacitor as ground;
when D (j-1) =0, setting the reference voltage of the (N-2-j) th second weighting capacitor as ground;
the comparator carries out the jth comparison and outputs a jth comparison result D (j);
E. j is increased by 1, step D is executed, the constraint condition is determined to be not satisfied, and the step D is finished;
F. comparison N-2: according to the comparison result D (N-3) of the N-3 th time,
when D (N-3) =1, setting the reference voltage of the second capacitor to ground;
when D (N-3) =0, the reference voltage of the fourth capacitance is set to ground;
the comparator carries out the N-2 comparison and outputs the N-2 comparison result D (N-2);
G. n-1 comparison: according to the (N-3) th comparison result D (N-3) and the (N-2) th comparison result D (N-2),
when D (N-3) =1, setting the reference voltages of the third capacitor and the fourth capacitor to a second reference voltage;
when D (N-3) =0, setting the reference voltages of the first capacitor and the second capacitor to a second reference voltage;
when D (N-3) D (N-2) =11, setting the reference voltage of the first capacitor to ground;
when D (N-3) D (N-2) =00, setting the reference voltage of the third capacitor to ground;
the comparator carries out the comparison for the (N-1) th time and outputs a comparison result D (N-1) for the (N-1) th time;
H. and (4) comparison for the Nth time: according to the N-3 th comparison result D (N-3) and the N-1 st comparison result D (N-1),
when D (N-3) D (N-1) =11, setting the reference voltage of the third capacitor as a first reference voltage;
when D (N-3) D (N-1) =00, setting the reference voltage of the first capacitor as a first reference voltage;
when D (N-3) D (N-1) =10, setting the reference voltage of the second capacitor as a second reference voltage, and setting the reference voltages of the third capacitor and the fourth capacitor as a first reference voltage;
when D (N-3) D (N-1) =01, setting the reference voltage of a fourth capacitor as a second reference voltage, and setting the reference voltages of the first capacitor and the second capacitor as a first reference voltage;
the comparator performs an nth comparison and outputs an nth comparison result D (N).
Further, the value of N is 5, and the control method comprises the following steps:
sampling: setting the reference voltage of the 1 st first weighting capacitor as ground, setting the reference voltage of the first capacitor as a first reference voltage, and setting the reference voltage of the second capacitor as a first reference voltage;
setting the reference voltage of a 1 st second weighting capacitor as ground, the reference voltage of the third capacitor as a first reference voltage, and the reference voltage of the fourth capacitor as a first reference voltage;
differential signals enter the capacitor array analog-to-digital converter from the first input end and the second input end to obtain a positive phase holding signal and a negative phase holding signal;
comparison 1: the comparator compares the positive phase holding signal and the negative phase holding signal for the first time and outputs a first comparison result D (1);
comparison at the 2 nd time: according to the result of the first comparison D (1),
when D (1) =1, setting the reference voltage of the 1 st second weighting capacitor as the first reference voltage;
when D (1) =0, the reference voltage of the 1 st first weighting capacitor is set as the first reference voltage;
the comparator performs the 2 nd comparison and outputs a 2 nd comparison result D (2);
comparison No. 3: according to the 2 nd comparison result D (2),
when D (2) =1, the reference voltage of the second capacitor is set to ground;
when D (2) =0, the reference voltage of the fourth capacitance is set to ground;
the comparator performs the 3 rd comparison and outputs a 3 rd comparison result D (3);
comparison 4: based on the 2 nd comparison result D (2) and the 3 rd comparison result D (3),
when D (2) =1, setting the reference voltages of the third capacitor and the fourth capacitor to a second reference voltage;
when D (2) =0, setting the reference voltages of the first capacitor and the second capacitor to a second reference voltage;
when D (2) D (3) =11, the reference voltage of the first capacitor is set to ground;
when D (2) D (3) =00, the reference voltage of the third capacitor is set to ground;
the comparator performs the 4 th comparison and outputs a 4 th comparison result D (4);
comparison 5: based on the 2 nd comparison result D (2) and the 4 th comparison result D (4),
when D (2) D (4) =11, setting the reference voltage of the third capacitor as a first reference voltage;
when D (2) D (4) =00, setting the reference voltage of the first capacitor as a first reference voltage;
when D (2) =10, the reference voltage of the second capacitor is set to a second reference voltage, and the reference voltages of the third capacitor and the fourth capacitor are set to a first reference voltage;
when D (2) D (4) =01, setting the reference voltage of the fourth capacitor as a second reference voltage, and setting the reference voltages of the first capacitor and the second capacitor as a first reference voltage;
the comparator performs the 5 th comparison and outputs the nth comparison result D (5).
The invention has the beneficial effects that:
according to the invention, the second capacitor array comprising the first capacitor and the second capacitor is arranged in the normal phase capacitor array, the fourth capacitor array comprising the third capacitor and the fourth capacitor is arranged in the reverse phase capacitor array, and the second capacitor array and the fourth capacitor array are multiplexed, so that the number of capacitors with high capacitance values can be reduced, and the purposes of reducing the process size of the capacitor array analog-to-digital converter and reducing the power consumption of the capacitor array analog-to-digital converter are achieved.
Drawings
FIG. 1 is a schematic circuit diagram of an energy efficient ADC according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a sampling and first comparison of a 5-bit energy efficient analog to digital converter according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a second comparison of a 5-bit energy efficient analog to digital converter in accordance with an embodiment of the present invention;
FIG. 4 is a third comparative schematic diagram of a 5-bit energy efficient analog-to-digital converter in accordance with an embodiment of the present invention;
FIG. 5 is a fourth comparative schematic diagram of a 5-bit energy efficient analog-to-digital converter in accordance with an embodiment of the present invention;
FIG. 6 is a fifth comparative schematic diagram of a 5-bit energy efficient analog-to-digital converter in accordance with an embodiment of the present invention.
Detailed Description
Reference will now be made in detail to the present preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout.
In the present invention, if directions (up, down, left, right, front, and rear) are described, it is only for convenience of describing the technical solution of the present invention, and it is not intended or implied that the technical features referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, it is not to be construed as limiting the present invention.
In the invention, the meaning of "a plurality" is one or more, the meaning of "a plurality" is more than two, and the terms of "more than", "less than", "more than" and the like are understood to exclude the number; the terms "above", "below", "within" and the like are understood to include the instant numbers. In the description of the present invention, if there is description of "first" and "second" only for the purpose of distinguishing technical features, it is not to be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features or implicitly indicating the precedence of the indicated technical features.
In the present invention, unless otherwise specifically limited, the terms "disposed," "mounted," "connected," and the like are to be understood in a broad sense, and for example, may be directly connected or indirectly connected through an intermediate; can be fixedly connected, can also be detachably connected and can also be integrally formed; may be mechanically coupled, may be electrically coupled or may be capable of communicating with each other; either as communication within the two elements or as an interactive relationship of the two elements. The specific meaning of the above-mentioned words in the present invention can be reasonably determined by those skilled in the art in combination with the detailed contents of the technical solutions.
The invention will be further explained and explained with reference to the drawings and the embodiments in the description.
Referring to fig. 1, an embodiment of the present invention provides an energy-efficient digital-to-analog converter, which includes a first input end, a second input end, a capacitor array analog-to-digital converter, a comparator 3, and a successive approximation shift register, where the capacitor array analog-to-digital converter includes a positive phase capacitor array 21 and a negative phase capacitor array 22;
the positive phase capacitor array 21 includes a first capacitor array 211 and a second capacitor array 212, the first capacitor array 211 includes N-4 first weighting capacitors, and a capacitance value of the ith first weighting capacitor is 2iC, wherein i is more than or equal to 1 and less than or equal to N-4, N is the digit of the capacitor array analog-to-digital converter and is more than or equal to 5, C represents a unit capacitor (the first weighted capacitor included in the first capacitor array 211 is C1-CN-4, and the corresponding capacitance value is 21C~2N-4C) The second capacitor array 212 includes a first capacitor CAP1And a second capacitor CAP2；
The inverse capacitor array 22 includes a third capacitor array 221 and a fourth capacitor array 222, the second capacitor array includes N-4 second weighting capacitors, and the capacitance value of the ith second weighting capacitor is 2iC, wherein i is more than or equal to 1 and less than or equal to N-4, N is the digit of the capacitor array analog-to-digital converter and is more than or equal to 5, C represents a unit capacitor, (the second weighting capacitor included in the third capacitor array 221 is C1-CN-4, and the corresponding capacitance value is 21C~2N-4C) The fourth capacitor array 222 includes a third capacitor CAP3And a fourth capacitor CAP4；
First capacitor CAP1Is connected to a first reference voltageV refOr a second reference voltage 3V ref/4 or ground gnd, second capacitance CAP2Is connected to a first reference voltageV refOr a second reference voltage 3V ref/4 or ground gnd, first capacitance CAP1The lower pole plate of the capacitor is connected with the positive phase input end of the comparator 3 and the first capacitor CAP1The lower plate of the capacitor is also connected to the first input terminal, and the second capacitor CAP2The lower pole plate of the capacitor is connected with the positive phase input end of the comparator 3 and the second capacitor CAP2The lower pole plate of (2) is also connected to the first input end;
the upper plate of each first weighting capacitor is connected to a first reference voltageV refOr ground gnd, the lower plate of each first weighting capacitor being connected to the first input terminal, the lower plate of each first weighting capacitor being further connected to the non-inverting input terminal of the comparator 3;
third capacitor CAP3Is connected to a first reference voltageV refOr a second reference voltage 3V ref/4 or ground gnd, fourth capacitance CAP4Is connected to a first reference voltageV refOr a second reference voltage 3V ref/4 or ground gnd, third capacitance CAP3The lower pole plate of the capacitor is connected with the inverting input end of the comparator 3 and the third capacitor CAP3Is further connected to the second input terminal, a fourth capacitor CAP4Is connected to the inverting input of the comparator 3, a fourth capacitor CAP4The lower pole plate of the first switch is also connected to the second input end;
the upper plate of each second weighting capacitor is connected to a first reference voltageV refOr gnd, the lower plate of each second weighting capacitor is connected with the second input end, and the lower plate of each second weighting capacitor is also connected with the inverting input end of the comparator 3;
the output end of the comparator 3 is connected with the input end of the successive approximation shift register.
Specifically, the control method of the energy-efficient analog-to-digital converter provided by this embodiment is as follows:
A. sampling: the positive-phase capacitor array 21 and the negative-phase capacitor array 22 are equivalent to a sample-and-hold circuit, and the reference voltage of the N-4 th first weighting capacitor of the first capacitor array is set to ground gnd, and the reference voltages of the remaining first weighting capacitors are set to first reference voltagesV refA first capacitor CAP1A second capacitor CAP2Is also set to the first reference voltageV refIn the same manner, the reference voltage of the (N-4) th second weighting capacitor is set to ground gnd, and the reference voltages of the remaining second weighting capacitors are set to the first reference voltageV refA third capacitor CAP3A fourth capacitor CAP4Is also set to the first reference voltageV ref. Differential signal VipAnd VinInputting a differential signal V into the capacitor array analog-to-digital converter from a first input end and a second input end of the capacitor array analog-to-digital converteripAnd VinThe differential signal VipAnd VinAfter passing through the positive phase capacitor array 21 and the negative phase capacitor array 22, a positive phase holding signal and a negative phase holding signal are respectively obtained at the positive phase input end and the negative phase input end of the comparator 3;
B. comparison 1: after obtaining the positive phase holding signal and the negative phase holding signal, the comparator 3 performs a first comparison and outputs a first comparison result D (1);
C. comparison at the 2 nd time: on the basis of the first comparison result D (1),
when D (1) =1, the reference voltage of the N-4 th second weighting capacitor in the third capacitor array is set as the first reference voltageV ref；
When D (1) =0, the reference voltage of the (N-4) th first weighting capacitor in the first capacitor array is set as the first reference voltageV ref；
The comparator 3 performs a second comparison and outputs a second comparison result D (2);
D. the jth comparison: according to the j-1 th comparison result D (j-1), wherein j is more than or equal to 3 and less than or equal to N-3, and N is more than 5 as a constraint condition,
when D (j-1) =1, setting the reference voltage of the (N-2-j) th first weighting capacitor in the first capacitor array as ground;
when D (j-1) =0, the reference voltage of the (N-2-j) th second weighting capacitor in the third capacitor array is set to ground;
the comparator 3 carries out the jth comparison and outputs a jth comparison result D (j);
E. j is increased by 1, step D is executed until the constraint condition is not satisfied, and the step D is executed;
F. comparison N-2: according to the comparison result D (N-3) of the N-3 th time,
when D (N-3) =1, the second capacitor CAP in the second capacitor array is connected to the first capacitor array2Is set to ground gnd;
when D (N-3) =0, the fourth capacitor CAP in the fourth capacitor array is connected to the second capacitor array4Is set to ground gnd;
the comparator 3 performs the N-2 th comparison and outputs the N-2 th comparison result D (N-2);
G. n-1 comparison: based on the N-3 th comparison result D (N-3) and the N-2 nd comparison result D (N-2),
when D (N-3) =1, the third capacitor CAP in the fourth capacitor array is connected to the second capacitor array3And a fourth capacitor CAP4Is set to a second reference voltage 3V ref/4；
When D (N-3) =0, the first capacitor CAP in the second capacitor array is connected1And a second capacitor CAP2Is set to a second reference voltage 3V ref/4；
When D (N-3) D (N-2) =11, the first capacitor CAP in the second capacitor array is used1Is set to ground gnd;
when D (N-3) D (N-2) =00, the third capacitor CAP in the fourth capacitor array is used3Is set to ground gnd;
the comparator 3 performs the N-1 th comparison and outputs the N-1 th comparison result D (N-1);
H. and (4) comparison for the Nth time: the N-3 th comparison result D (N-3) and the N-1 st comparison result D (N-1)
When D (N-3) D (N-1) =11, the fourth electrode is connectedThird capacitor CAP in capacitor array3Is set to a first reference voltageV ref；
When D (N-3) D (N-1) =00, the first capacitor CAP in the second capacitor array is used1Is set to a first reference voltageV ref；
When D (N-3) D (N-1) =10, the second capacitor CAP in the second capacitor array is connected2Is set to a second reference voltage 3V ref/4, connecting the third capacitor CAP in the fourth capacitor array3And a fourth capacitor CAP4Is set to a first reference voltageV ref；
When D (N-3) D (N-1) =01, the fourth capacitor CAP in the fourth capacitor array is used4Is set to a second reference voltageV ref4, connecting the first capacitor CAP in the second capacitor array1And a second capacitor CAP2Is set to a first reference voltageV ref；
The comparator 3 performs the nth comparison and outputs the nth comparison result D (N).
The present embodiment provides a control method for controlling an N-bit high-energy efficient analog-to-digital converter (N)>5) In the process of comparing the comparator 3 from 1 st to (N-3) th times, the reference voltage of the first or second weighting capacitor is changed bit by bit, and when the comparator compares for the N-2 th time, the second capacitor CAP is changed2Or a fourth capacitor CAP4The second capacitor CAP is utilized again when the last 2 comparisons are made2And a fourth capacitor CAP4The reference voltage comparison process, therefore, the comparator 3 of the present application can multiplex the capacitances of the second capacitor array and the fourth capacitor array (the second capacitor CAP) when performing the comparison2And a fourth capacitor CAP4) The capacitance values of the second capacitor array capacitor and the fourth capacitor array capacitor are smaller, so that the use of capacitors with higher capacitance values is reduced, namely, the use of large-volume capacitors is avoided as much as possible, thereby reducing the difficulty of the manufacturing process of the successive approximation new analog-to-digital converter, and the capacitance values of the second capacitor array capacitor and the fourth capacitor array capacitor are smaller, thereby reducing the cost of the successive approximation new analog-to-digital converterThe power consumption of the capacitor array analog-to-digital converter is reduced.
In order to more clearly illustrate the technical solution of the present application, the present application further provides another embodiment, where N takes a value of 5, so as to obtain a 5-bit high-performance analog-to-digital converter, and a corresponding control method is as follows:
referring to fig. 2, since the 5-bit high performance adc is used, there is only one capacitor in the first capacitor array and the fourth capacitor array, i.e. C1, and the first capacitor CAP is included in the second capacitor array1And a second capacitor CAP2The fourth capacitor array includes a third capacitor CAP3And a fourth capacitor CAP4。
Sampling: setting the reference voltage of the 1 st first weighting capacitor to ground gnd, and setting the first capacitor CAP1Is set to a first reference voltageV refA second capacitor CAP2Is set to a first reference voltageV ref；
Setting the reference voltage of the 1 st second weighting capacitor to ground gnd, and setting the third capacitor CAP3Is set to a first reference voltageV refA fourth capacitor CAP4Is set to a first reference voltageV ref；
Differential signal VipAnd VinInto the capacitor array analog-to-digital converter to obtain a positive hold signal and a negative hold signal at the positive input terminal and the negative input terminal of the comparator 3.
Comparison 1: after obtaining the positive phase holding signal and the negative phase holding signal, the comparator 3 performs a first comparison and outputs a first comparison result D (1);
referring to fig. 3, the 2 nd comparison: on the basis of the first comparison result D (1),
when D (1) =1, the reference voltage of the 1 st second weighting capacitor in the third capacitor array is set as the first reference voltageV ref；
When D (1) =0, the reference voltage of the 1 st first weighting capacitor in the first capacitor array is set as the first reference voltageV ref；
The comparator 3 performs a second comparison and outputs a second comparison result D (2);
referring to fig. 4, comparison 3: on the basis of the result of the second comparison D (2),
when D (2) =1, the second capacitor CAP in the second capacitor array is connected to the first capacitor array2Is set to ground gnd;
when D (2) =0, the fourth capacitor CAP in the fourth capacitor array is connected to the second capacitor array4Is set to ground gnd;
the comparator 3 performs the third comparison and outputs a second comparison result D (3);
referring to fig. 5, comparison 4: based on the 2 nd comparison result D (2) and the 3 rd comparison result D (3),
when D (2) =1, the third capacitor CAP in the fourth capacitor array is connected to the second capacitor array3And a fourth capacitor CAP4Is set to a second reference voltage 3V ref/4；
When D (2) =0, the first capacitor CAP in the second capacitor array is connected to the second capacitor array1And a second capacitor CAP2Is set to a second reference voltage 3V ref/4；
When D (2) D (3) =11, the first capacitor CAP in the second capacitor array is replaced with the second capacitor CAP1Is set to ground gnd;
when D (3) D (2) =00, the third capacitor CAP in the fourth capacitor array is replaced with the third capacitor CAP3Is set to ground gnd;
the comparator 3 performs the 4 th comparison and outputs a 4 th comparison result D (4);
referring to fig. 6, comparison 5: a 2 nd comparison result D (2) and a 4 th comparison result D (4),
when D (2) D (4) =11, the third capacitor CAP in the fourth capacitor array is replaced with the third capacitor CAP3Is set to a first reference voltageV ref；
When D (2) D (4) =00, the first capacitor CAP in the second capacitor array is replaced with the second capacitor CAP1Is set to a first reference voltageV ref；
When D (2) D (4) =10, the second capacitor is connectedSecond capacitor CAP in capacitor array2Is set to a second reference voltage 3V ref/4, third capacitance CAP3And a fourth capacitor CAP4Is set to a first reference voltageV ref；
When D (2) D (4) =01, the fourth capacitor CAP in the fourth capacitor array is replaced with the fourth capacitor CAP4Is set to a second reference voltage 3V ref/4, first capacitance CAP1And a second capacitor CAP2Is set to a first reference voltageV ref；
The comparator 3 performs the 5 th comparison and outputs a 5 th comparison result D (5).
Compared with the conventional 5-bit successive approximation type analog-to-digital converter, the positive phase capacitor array 21 includes 5 capacitors with capacitance values of 21C、22C、23C、24C、25C. The positive phase capacitor array 21 of the present application only needs to include the first capacitor CAP1A second capacitor CAP2And a first weighting capacitor C1, the capacitance values are C, C and 2 in turn1And C, under the condition of realizing the function of the successive approximation type analog-to-digital converter, the capacitor with a large capacitance value is avoided, the process size of the analog-to-digital converter is reduced, and the power consumption is reduced.
Further as an alternative implementation, referring to fig. 1, the energy efficient analog-to-digital converter further includes a sampling switch 1, the sampling switch 1 includes a first sampling switch S1 and a second sampling switch S2, one end of the first sampling switch S1 is connected to the first input terminal, the other end of the first sampling switch S1 is connected to the input terminal of the non-inverting capacitor array 21, one end of the second sampling switch S2 is connected to the second input terminal, and the other end of the second sampling switch S2 is connected to the input terminal of the inverting capacitor array 22.
Specifically, the application is also provided with a sampling switch 1, and the differential signal V is controlled by the sampling switch 1ipAnd VinWhen the differential signal V is inputipAnd VinInputting the signal into the capacitor array analog-to-digital converter, disconnecting the sampling switch 1 and differentiating the signal VipAnd VinThrough capacitive array analog-to-digital conversionThe comparators may be held at the non-inverting and inverting inputs of the comparator 3.
As a further optional implementation, the positive phase capacitor array 21 further includes a plurality of bidirectional switches and three-way switches; the upper plate of each first weighting capacitor is connected to a first reference voltage through a bidirectional switchV refOr gnd;
realizing the first capacitor CAP through a three-way switch1Is connected to a first reference voltageV refOr a second reference voltage 3V ref/4 or ground gnd, and a second capacitance CAP2Is connected to a first reference voltageV refOr a second reference voltage 3V refAnd/4 or gnd.
Specifically, the present application provides a method for controlling the first weighting capacitor and the first capacitor CAP in the positive phase capacitor array 211And a second capacitor CAP2The specific implementation manner of switching the reference voltage is that the reference voltage of the capacitor in the normal phase capacitor array 21 can be flexibly and conveniently switched by arranging the bidirectional switch and the three-phase switch.
As a further optional implementation, the inverting capacitor array 22 further includes a plurality of bidirectional switches and three-way switches;
the upper plate of each second weighting capacitor is connected to the first reference voltage through a bidirectional switchV refOr gnd;
third capacitor CAP realized by three-way switch3Is connected to a first reference voltageV refOr a second reference voltage 3V ref/4 or ground gnd, and a fourth capacitance CAP4Is connected to a first reference voltageV refOr a second reference voltage 3V refAnd/4 or gnd.
Specifically, in the same manner, a bidirectional switch and a three-way switch are also provided in the inverting capacitor array 22, so that the capacitors in the inverting capacitor array 22 can flexibly switch the reference voltage.
While the preferred embodiments of the present invention have been illustrated and described, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (6)

1. The high-energy-efficiency analog-to-digital converter is characterized by comprising a first input end, a second input end, a capacitor array analog-to-digital converter, a comparator and a successive approximation shift register, wherein the capacitor array analog-to-digital converter comprises a normal phase capacitor array and a reverse phase capacitor array;
the positive phase capacitor array comprises a first capacitor array and a second capacitor array, the first capacitor array comprises N-4 first weighting capacitors, and the capacitance value of the ith first weighting capacitor is 2iC, wherein i is more than or equal to 1 and less than or equal to N-4, N is the digit of the capacitor array analog-to-digital converter and is more than or equal to 5, C represents a unit capacitor, and the second capacitor array comprises a first capacitor and a second capacitor;
the reverse-phase capacitor array comprises a third capacitor array and a fourth capacitor array, the third capacitor array comprises N-4 second weighting capacitors, and the capacitance value of the ith second weighting capacitor is 2iC, wherein i is more than or equal to 1 and less than or equal to N-4, N is the digit of the capacitor array analog-to-digital converter and is more than or equal to 5, C represents a unit capacitor, and the fourth capacitor array comprises a third capacitor and a fourth capacitor;
the upper plate of the first capacitor is connected to a first reference voltage or a second reference voltage or ground, the upper plate of the second capacitor is connected to the first reference voltage or the second reference voltage or ground, the lower plate of the first capacitor is connected to the positive input end of the comparator, the lower plate of the first capacitor is also connected to the first input end, the lower plate of the second capacitor is connected to the positive input end of the comparator, and the lower plate of the second capacitor is also connected to the first input end;
the upper plate of each first weighting capacitor is connected to a first reference voltage or ground, the lower plate of each first weighting capacitor is connected to a first input end, and the lower plate of each first weighting capacitor is also connected to the non-inverting input end of a comparator;
the upper plate of the third capacitor is connected to a first reference voltage or a second reference voltage or ground, the upper plate of the fourth capacitor is connected to the first reference voltage or the second reference voltage or ground, the lower plate of the third capacitor is connected to the inverting input end of the comparator, the lower plate of the third capacitor is also connected to the second input end, the lower plate of the fourth capacitor is connected to the inverting input end of the comparator, and the lower plate of the fourth capacitor is also connected to the second input end;
the upper plate of each second weighting capacitor is connected to a first reference voltage or ground, the lower plate of each second weighting capacitor is connected to a second input end, and the lower plate of each second weighting capacitor is also connected to the inverting input end of the comparator;
and the output end of the comparator is connected with the input end of the successive approximation shift register.
2. The energy-efficient analog-to-digital converter according to claim 1, further comprising a sampling switch, wherein the sampling switch comprises a first sampling switch and a second sampling switch, one end of the first sampling switch is connected to the first input terminal, the other end of the first sampling switch is connected to the input terminal of the positive phase capacitor array, one end of the second sampling switch is connected to the second input terminal, and the other end of the second sampling switch is connected to the input terminal of the negative phase capacitor array.
3. The energy efficient analog-to-digital converter according to claim 1, wherein the positive phase capacitor array further comprises a plurality of bidirectional switches and three-way switches;
connecting the upper plate of each first weighting capacitor to a first reference voltage or ground through the bidirectional switch;
the upper plate of the first capacitor is connected to a first reference voltage or a second reference voltage or ground through the three-way switch, and the upper plate of the second capacitor is connected to the first reference voltage or the second reference voltage or ground.
4. The energy efficient analog to digital converter of claim 1, wherein the inverting capacitor array further comprises a plurality of bi-directional switches and three-directional switches;
the upper plate of each second weighting capacitor is connected to a first reference voltage or ground through the bidirectional switch;
the upper plate of the third capacitor is connected to the first reference voltage or the second reference voltage or the ground through the three-way switch, and the upper plate of the fourth capacitor is connected to the first reference voltage or the second reference voltage or the ground.
5. A control method applied to an energy-efficient analog-to-digital converter according to claim 1, comprising the steps of:
A. sampling: setting the reference voltage of the (N-4) th first weighting capacitor as ground, setting the reference voltage of the first weighting capacitors in the first capacitor array except the (N-4) th first weighting capacitor as a first reference voltage, setting the reference voltage of the first capacitor as a first reference voltage, and setting the reference voltage of the second capacitor as a first reference voltage;
setting the reference voltage of the (N-4) th second weighting capacitor as ground, setting the reference voltage of the second weighting capacitors except the (N-4) th second weighting capacitor in the third capacitor array as a first reference voltage, setting the reference voltage of the third capacitor as the first reference voltage, and setting the reference voltage of the fourth capacitor as the first reference voltage;
differential signals enter the capacitor array analog-to-digital converter from the first input end and the second input end to obtain a positive phase holding signal and a negative phase holding signal;
B. comparison 1: the comparator compares the positive phase holding signal and the negative phase holding signal for the first time and outputs a first comparison result D (1);
C. comparison at the 2 nd time: according to the result of the first comparison D (1),
when D (1) =1, setting the reference voltage of the (N-4) th second weighting capacitor as the first reference voltage;
when D (1) =0, setting the reference voltage of the (N-4) th first weighting capacitor as a first reference voltage;
the comparator performs the 2 nd comparison and outputs a 2 nd comparison result D (2);
D. the jth comparison: according to the j-1 th comparison result D (j-1), wherein j is more than or equal to 3 and less than or equal to N-3, and N is more than 5 as a constraint condition,
when D (j-1) =1, setting the reference voltage of the (N-2-j) th first weighting capacitor as ground;
when D (j-1) =0, setting the reference voltage of the (N-2-j) th second weighting capacitor as ground;
the comparator carries out the jth comparison and outputs a jth comparison result D (j);
E. j is increased by 1, step D is executed, the constraint condition is determined to be not satisfied, and the step D is finished;
F. comparison N-2: according to the comparison result D (N-3) of the N-3 th time,
when D (N-3) =1, setting the reference voltage of the second capacitor to ground;
when D (N-3) =0, the reference voltage of the fourth capacitance is set to ground;
the comparator carries out the N-2 comparison and outputs the N-2 comparison result D (N-2);
G. n-1 comparison: according to the (N-3) th comparison result D (N-3) and the (N-2) th comparison result D (N-2),
when D (N-3) =1, setting the reference voltages of the third capacitor and the fourth capacitor to a second reference voltage;
when D (N-3) =0, setting the reference voltages of the first capacitor and the second capacitor to a second reference voltage;
when D (N-3) D (N-2) =11, setting the reference voltage of the first capacitor to ground;
when D (N-3) D (N-2) =00, setting the reference voltage of the third capacitor to ground;
the comparator carries out the comparison for the (N-1) th time and outputs a comparison result D (N-1) for the (N-1) th time;
H. and (4) comparison for the Nth time: according to the N-3 th comparison result D (N-3) and the N-1 st comparison result D (N-1),
when D (N-3) D (N-1) =11, setting the reference voltage of the third capacitor as a first reference voltage;
when D (N-3) D (N-1) =00, setting the reference voltage of the first capacitor as a first reference voltage;
when D (N-3) D (N-1) =10, setting the reference voltage of the second capacitor as a second reference voltage, and setting the reference voltages of the third capacitor and the fourth capacitor as a first reference voltage;
when D (N-3) D (N-1) =01, setting the reference voltage of a fourth capacitor as a second reference voltage, and setting the reference voltages of the first capacitor and the second capacitor as a first reference voltage;
the comparator performs an nth comparison and outputs an nth comparison result D (N).
6. The control method according to claim 5, wherein said N takes a value of 5, said control method comprising the steps of:
sampling: setting the reference voltage of a 1 st first weighting capacitor as ground, setting the reference voltage of the first capacitor as a first reference voltage, and setting the reference voltage of the second capacitor as a first reference voltage;
setting the reference voltage of a 1 st second weighting capacitor as ground, the reference voltage of the third capacitor as a first reference voltage, and the reference voltage of the fourth capacitor as a first reference voltage;
differential signals enter the capacitor array analog-to-digital converter from the first input end and the second input end to obtain a positive phase holding signal and a negative phase holding signal;
comparison 1: the comparator compares the positive phase holding signal and the negative phase holding signal for the first time and outputs a first comparison result D (1);
comparison at the 2 nd time: according to the result of the first comparison D (1),
when D (1) =1, setting the reference voltage of the 1 st second weighting capacitor as the first reference voltage;
when D (1) =0, the reference voltage of the 1 st first weighting capacitor is set as the first reference voltage;
the comparator performs the 2 nd comparison and outputs a 2 nd comparison result D (2);
comparison No. 3: according to the 2 nd comparison result D (2),
when D (2) =1, the reference voltage of the second capacitor is set to ground;
when D (2) =0, the reference voltage of the fourth capacitance is set to ground;
the comparator performs the 3 rd comparison and outputs a 3 rd comparison result D (3);
comparison 4: according to the 2 nd comparison result D (2) and the 3 rd comparison result D (3),
when D (2) =1, setting the reference voltages of the third capacitor and the fourth capacitor to a second reference voltage;
when D (2) =0, setting the reference voltages of the first capacitor and the second capacitor to a second reference voltage;
when D (2) D (3) =11, the reference voltage of the first capacitor is set to ground;
when D (2) D (3) =00, the reference voltage of the third capacitor is set to ground;
the comparator performs the 4 th comparison and outputs a 4 th comparison result D (4);
comparison 5: based on the 2 nd comparison result D (2) and the 4 th comparison result D (4),
when D (2) D (4) =11, setting the reference voltage of the third capacitor as a first reference voltage;
when D (2) D (4) =00, setting the reference voltage of the first capacitor as a first reference voltage;
when D (2) =10, the reference voltage of the second capacitor is set to a second reference voltage, and the reference voltages of the third capacitor and the fourth capacitor are set to a first reference voltage;
when D (2) D (4) =01, setting the reference voltage of the fourth capacitor as a second reference voltage, and setting the reference voltages of the first capacitor and the second capacitor as a first reference voltage;
the comparator performs the 5 th comparison and outputs the nth comparison result D (5).
CN202011095330.5A 2020-10-14 2020-10-14 High-energy-efficiency analog-to-digital converter and control method thereof Active CN111934687B (en)

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