CN111934689B - High-precision analog-to-digital converter and conversion method - Google Patents
High-precision analog-to-digital converter and conversion method Download PDFInfo
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- CN111934689B CN111934689B CN202011010209.8A CN202011010209A CN111934689B CN 111934689 B CN111934689 B CN 111934689B CN 202011010209 A CN202011010209 A CN 202011010209A CN 111934689 B CN111934689 B CN 111934689B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
- H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/002—Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
Abstract
The invention discloses a high-precision analog-to-digital converter, which comprises a first input end, a second input end, a normal phase capacitor array, an inverse phase capacitor array, a comparator and a shift register, wherein the first input end is connected with the second input end; the first input end is further connected to the non-inverting input end of the comparator through the positive phase capacitor array, the second input end is further connected to the inverting input end of the comparator through the inverting capacitor array, and the output end of the comparator is connected with the input end of the shift register. The voltage can be switched during comparison through the positive phase capacitor array and the negative phase capacitor array, so that the comparator executes first comparison under the condition of not consuming any switching energy, the energy consumed by comparing the capacitor arrays each time is smaller than that consumed by a traditional structure, and the average switching power consumption of the capacitor arrays can be effectively reduced. The invention can be widely applied to the technical field of electronic circuits.
Description
Technical Field
The invention relates to the technical field of electronic circuits, in particular to a high-precision analog-to-digital converter and a conversion method.
Background
The successive approximation type analog-to-digital converter is an analog-to-digital converter structure with medium and high precision, medium conversion rate and ultra-low power consumption. For sensors, portable devices and biological applications, analog-to-digital converters are required to be able to operate at low supply voltages. However, as the power supply voltage decreases, the gain of the circuit is limited, and the structure of the successive approximation type analog-to-digital converter includes only a comparator, a digital-to-analog converter, and a successive approximation register without a circuit for providing a gain. The power consumption of digital circuits is reduced with the reduction of the process size, while the power consumption of analog circuits is difficult to reduce with the progress of the process.
Disclosure of Invention
In order to solve the above technical problems, an object of the present invention is to provide a high-precision analog-to-digital converter.
In a first aspect, an embodiment of the present invention provides a high-precision analog-to-digital converter, including a first input end, a second input end, a normal-phase capacitor array, an inverse-phase capacitor array, a comparator, and a shift register;
the first input end is further connected to a non-inverting input end of the comparator through the positive phase capacitor array, the second input end is further connected to an inverting input end of the comparator through the inverting capacitor array, and an output end of the comparator is connected with an input end of the shift register;
the positive phase capacitor array comprises a positive phase high array and a positive phase low array, the first input end is further connected to a non-inverting input end of the comparator through the positive phase high array and the positive phase low array, the positive phase high array is initially connected to a reference voltage, and the positive phase low array is initially connected to the ground.
The positive phase high array comprises a first capacitor and a first capacitor group, a lower plate of the first capacitor and a lower plate of the first capacitor group are both connected to the first input end and a non-inverting input end of the comparator, an upper plate of the first capacitor is selectively connected with a reference voltage or a common mode voltage or ground through a switch, and an upper plate of the first capacitor group is selectively connected with the reference voltage or the common mode voltage or ground through the switch;
the first capacitor bank comprises N-3 capacitors, the lower pole plates of the capacitors of the first capacitor bank are connected to the first input end and the non-inverting input end of the comparator, the upper pole plates of the capacitors of the first capacitor bank are selectively connected with a reference voltage or a common mode voltage or ground through a switch respectively, wherein the capacitance value of the ith capacitor in the first capacitor bank is 2i-1C, i is more than or equal to 1 and less than or equal to N-3, N represents the digit of the digital-to-analog converter, N is more than or equal to 4, and C represents a unit capacitor;
the positive-phase low array comprises a second capacitor and a second capacitor group, a lower plate of the second capacitor and a lower plate of the second capacitor group are both connected to the first input end and the non-inverting input end of the comparator, an upper plate of the second capacitor is selectively connected with a reference voltage or a common-mode voltage or ground through a switch, and an upper plate of the second capacitor group is selectively connected with the reference voltage or the common-mode voltage or the ground through the switch;
the second capacitor group comprises N-3 capacitors, the lower pole plates of the capacitors of the second capacitor group are connected to the first input end and the non-inverting input end of the comparator, the upper pole plates of the capacitors of the second capacitor group are respectively selectively connected with reference voltage or common mode voltage or ground through a switch, and the capacitance value of the ith capacitor in the second capacitor group is 2i-1C，1≤i≤N-3。
In an embodiment of the invention, a capacitance value of the first capacitor and the second capacitor is C.
In an embodiment of the invention, the inverting capacitor array includes an inverting high array and an inverting low array, the second input terminal is further connected to the non-inverting input terminal of the comparator through the inverting high array and the inverting low array, the inverting high array is initially connected to a reference voltage, and the inverting low array is initially connected to ground.
In an embodiment of the present invention, the inverted high array includes a third capacitor and a third capacitor group, a lower plate of the third capacitor and a lower plate of the third capacitor group are both connected to the second input terminal and the inverted input terminal of the comparator, an upper plate of the third capacitor is selectively connected to the reference voltage or the common mode voltage or the ground through a switch, and an upper plate of the third capacitor group is selectively connected to the reference voltage or the common mode voltage or the ground through a switch;
in an embodiment of the present invention, the third capacitor bank includes N-3 capacitors, a lower plate of the capacitor of the third capacitor bank is connected to the second input terminal and the inverting input terminal of the comparator, and an upper plate of the capacitor of the third capacitor bank is selectively connected to a reference voltage or a common mode voltage or ground through a switch, respectively, where electricity of the ith capacitor in the third capacitor bankCapacity value of 2i-1And C, i is more than or equal to 1 and less than or equal to N-3, N represents the digit of the digital-to-analog converter, and N is more than or equal to 4.
In an embodiment of the present invention, the inverted low array includes a fourth capacitor and a fourth capacitor group, a lower plate of the fourth capacitor and a lower plate of the fourth capacitor group are both connected to the second input terminal and the inverted input terminal of the comparator, an upper plate of the fourth capacitor is selectively connected to the reference voltage or the common mode voltage or the ground through a switch, and an upper plate of the fourth capacitor group is selectively connected to the reference voltage or the common mode voltage or the ground through a switch;
in an embodiment of the present invention, the fourth capacitor group includes N-3 capacitors, a lower plate of a capacitor of the fourth capacitor group is connected to the second input terminal and the inverting input terminal of the comparator, an upper plate of a capacitor of the fourth capacitor group is selectively connected to a reference voltage or a common mode voltage or ground through a switch, respectively, where a capacitance value of an ith capacitor in the fourth capacitor group is 2i-1And C, i is more than or equal to 1 and less than or equal to N-3, N represents the digit of the digital-to-analog converter, and N is more than or equal to 4.
In an embodiment of the invention, a capacitance of the third capacitor is C.
In an embodiment of the invention, a capacitance value of the fourth capacitor is C.
In a second aspect, embodiments of the present invention provide a conversion method applied to a high-precision analog-to-digital converter, in which in comparison from 1 st to N-1 st, the in-phase input signal and the inverted input signal of the comparator maintain a common mode; in the nth comparison, the in-phase input signal and the inverted input signal are not in common mode.
The invention has the beneficial effects that:
the voltage can be switched during comparison through the positive phase capacitor array and the negative phase capacitor array, so that the comparator executes first comparison under the condition of not consuming any switching energy, the energy consumed by comparing the capacitor arrays each time is smaller than that consumed by a traditional structure, and the average switching power consumption of the capacitor arrays can be effectively reduced.
Drawings
FIG. 1 is a schematic circuit diagram of a high precision analog-to-digital converter according to an embodiment of the present invention;
FIG. 2 is a schematic comparative flow diagram of one embodiment of the present invention;
fig. 3 is a schematic diagram of the operation principle of a 4-bit analog-to-digital converter according to an embodiment of the present invention.
Detailed Description
The following further describes embodiments of the present invention with reference to the accompanying drawings:
referring to fig. 1, an embodiment of the present invention provides a high-precision analog-to-digital converter, including a first input terminal, a second input terminal, a positive phase capacitor array, a negative phase capacitor array, a comparator, and a shift register;
the first input end is further connected to a non-inverting input end of a comparator through a positive phase capacitor array, the second input end is further connected to an inverting input end of the comparator through an inverting capacitor array, and an output end of the comparator is connected with an input end of the shift register;
the positive phase capacitor array comprises a positive phase high array and a positive phase low array, a first input end is further connected to a positive phase input end of the comparator through the positive phase high array and the positive phase low array, the positive phase high array is initially connected to a reference voltage, and the positive phase low array is initially connected to the ground.
The positive phase high array comprises a first capacitor and a first capacitor group, wherein a lower plate of the first capacitor and a lower plate of the first capacitor group are connected to the first input end and a non-inverting input end of the comparator, an upper plate of the first capacitor is selectively connected with a reference voltage or a common mode voltage or ground through a switch, and an upper plate of the first capacitor group is selectively connected with the reference voltage or the common mode voltage or the ground through the switch;
the first capacitor bank comprises N-3 capacitors, the lower electrode plates of the capacitors of the first capacitor bank are connected to the first input end and the non-inverting input end of the comparator, the upper electrode plates of the capacitors of the first capacitor bank are selectively connected with a reference voltage or a common mode voltage or ground through a switch respectively, wherein the capacitance value of the ith capacitor in the first capacitor bank is 2i-1C, i is more than or equal to 1 and less than or equal to N-3, N represents digital-to-analog conversionThe number of the device bits is more than or equal to 4, and C represents a unit capacitor;
the positive-phase low array comprises a second capacitor and a second capacitor group, a lower plate of the second capacitor and a lower plate of the second capacitor group are both connected to the first input end and the non-inverting input end of the comparator, an upper plate of the second capacitor is selectively connected with a reference voltage or a common-mode voltage or ground through a switch, and an upper plate of the second capacitor group is selectively connected with the reference voltage or the common-mode voltage or the ground through the switch;
the second capacitor group comprises N-3 capacitors, the lower pole plates of the capacitors of the second capacitor group are connected to the first input end and the non-inverting input end of the comparator, the upper pole plates of the capacitors of the second capacitor group are respectively selectively connected with a reference voltage or a common mode voltage or ground through a switch, wherein the capacitance value of the ith capacitor in the second capacitor group is 2i-1C，1≤i≤N-3。
In an embodiment of the invention, the capacitance values of the first capacitor and the second capacitor are C.
In an embodiment of the invention, the inverting capacitor array includes an inverting high array and an inverting low array, the second input terminal is further connected to the non-inverting input terminal of the comparator through the inverting high array and the inverting low array, the inverting high array is located on the high potential side, and the inverting low array is located on the low potential side.
In an embodiment of the present invention, the inverted high array includes a third capacitor and a third capacitor group, a lower plate of the third capacitor and a lower plate of the third capacitor group are both connected to the second input terminal and the inverted input terminal of the comparator, an upper plate of the third capacitor is selectively connected to the reference voltage or the common mode voltage or the ground through a switch, and an upper plate of the third capacitor group is selectively connected to the reference voltage or the common mode voltage or the ground through a switch;
in an embodiment of the present invention, the third capacitor group includes N-3 capacitors, a lower plate of the capacitor of the third capacitor group is connected to the second input terminal and the inverting input terminal of the comparator, and an upper plate of the capacitor of the third capacitor group is selectively connected to the reference voltage or the common mode voltage through a switch respectivelyOr the capacitance value of the ith capacitor in the third capacitor group is 2i-1And C, i is more than or equal to 1 and less than or equal to N-3, N represents the digit of the digital-to-analog converter, and N is more than or equal to 4.
In an embodiment of the present invention, the inverted low array includes a fourth capacitor and a fourth capacitor group, a lower plate of the fourth capacitor and a lower plate of the fourth capacitor group are both connected to the second input terminal and the inverted input terminal of the comparator, an upper plate of the fourth capacitor is selectively connected to the reference voltage or the common mode voltage or the ground through a switch, and an upper plate of the fourth capacitor group is selectively connected to the reference voltage or the common mode voltage or the ground through a switch;
in an embodiment of the present invention, the fourth capacitor group includes N-3 capacitors, a lower plate of a capacitor of the fourth capacitor group is connected to the second input terminal and the inverting input terminal of the comparator, an upper plate of a capacitor of the fourth capacitor group is selectively connected to a reference voltage or a common mode voltage or ground through a switch, respectively, where a capacitance value of an ith capacitor in the fourth capacitor group is 2i-1And C, i is more than or equal to 1 and less than or equal to N-3, N represents the digit of the digital-to-analog converter, and N is more than or equal to 4.
In an embodiment of the invention, a capacitance of the third capacitor is C.
In an embodiment of the invention, a capacitance of the fourth capacitor is C.
In one embodiment of the present invention, the switch is a single-pole multi-throw switch.
Referring to fig. 2, the first stage of the present embodiment: the input signal is sampled on the top plates of all capacitors by sampling switches, the bottom plate of the high array is connected to Vref and the bottom plate of the low array is connected to gnd. After sampling, the sampling switch is closed. Then, the comparator performs the first comparison without consuming any switching energy, and outputs the most significant bit data D0.
And a second stage: the high array on the high voltage potential side and the low array on the low potential side of the first stage will be switched to Vcm (Vref/2), and the other arrays will remain unchanged. As a result, the voltage on the high voltage side is lowered by Vref/4, and the voltage on the low voltage side is raised by Vref/4. Then, the comparator performs the second comparison, and outputs the second higher data D1.
And a third stage: the corresponding capacitor on the higher voltage side is switched from Vcm to gnd according to the output of the previous comparator, while the capacitor on the other side (lower voltage side) is switched from Vcm to Vref, and then the comparator performs comparison, outputting the comparison result. For example, in the third comparison, the largest capacitor in the array connected to Vcm on the higher voltage side is switched from Vcm to gnd, while the other (lower voltage side) Vcm is switched to Vref.
The ADC repeats this process until the (N-1) th comparison is completed. During switching, the common mode voltage is unchanged. The capacitor array switching energy from the 3 rd comparator to the (N-1) th comparator is:
a fourth stage: in the nth comparison, the last capacitor of the sub-array connected to the higher voltage side Vcm switches from Vcm to gnd, while the other capacitor (the lower voltage side) remains unchanged. The capacitor array switching energy in the Nth comparison is:
for N-bit resolution, the average switching energy of the capacitor array switching energy is:
for example, as shown in fig. 3, in the first stage: the input signal is sampled on the top plates of all capacitors by sampling switches, the bottom plate of the high array is connected to Vref and the bottom plate of the low array is connected to gnd. After sampling, the sampling switch is closed. Then, the comparator performs the first comparison without consuming any switching energy, and outputs the most significant bit data D0.
And a second stage: the high array on the high voltage potential side and the low array on the low potential side of the first stage will be switched to Vcm (Vref/2), and the other arrays will remain unchanged. As a result, the voltage on the high voltage side is lowered by Vref/4, and the voltage on the low voltage side is raised by Vref/4. Then, the comparator performs the second comparison, and outputs the second higher data D1.
And a third stage: according to the output result of the second comparator, the largest capacitor in the array connected to Vcm on the higher voltage side is switched from Vcm to gnd, and the other (lower voltage side) Vcm is switched to Vref. The capacitor array switch energy of the 3 rd comparator is
A fourth stage: in the nth comparison, the last capacitor of the sub-array connected to the higher voltage side Vcm switches from Vcm to gnd, while the other capacitor (the lower voltage side) remains unchanged. In the Nth comparison, the switch energy of the capacitor array is (5)
For 4-bit resolution, the average switching energy of the capacitor array switching energy is:
from the above, the voltage can be switched during comparison by the positive phase capacitor array and the negative phase capacitor array, so that the comparator performs the first comparison without consuming any switching energy, and the energy consumed by comparing the capacitor arrays each time is smaller than that consumed by the conventional structure, thereby effectively reducing the average switching power consumption of the capacitor arrays. According to the invention, a low-complexity DAC scheme is realized through the SAR ADC according to the requirement, so that the situation that a single capacitor presents three or more reference voltages is prevented, and the power consumption can be effectively reduced.
While the preferred embodiments of the present invention have been illustrated and described, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (9)
1. A high-precision analog-to-digital converter is characterized by comprising a first input end, a second input end, a normal phase capacitor array, an inverse phase capacitor array, a comparator and a shift register;
the first input end is further connected to a non-inverting input end of the comparator through the positive phase capacitor array, the second input end is further connected to an inverting input end of the comparator through the inverting capacitor array, and an output end of the comparator is connected with an input end of the shift register;
the positive phase capacitor array comprises a positive phase high array and a positive phase low array, the first input end is further connected to a non-inverting input end of the comparator through the positive phase high array and the positive phase low array, the positive phase high array is initially connected to a reference voltage, and the positive phase low array is initially connected to the ground;
the positive phase high array comprises a first capacitor and a first capacitor group, a lower plate of the first capacitor and a lower plate of the first capacitor group are both connected to the first input end and a non-inverting input end of the comparator, an upper plate of the first capacitor is selectively connected with a reference voltage or a common mode voltage or ground through a switch, and an upper plate of the first capacitor group is selectively connected with the reference voltage or the common mode voltage or ground through the switch;
the first capacitor bank comprises N-3 capacitors, the lower pole plates of the capacitors of the first capacitor bank are connected to the first input end and the non-inverting input end of the comparator, the upper pole plates of the capacitors of the first capacitor bank are selectively connected with a reference voltage or a common mode voltage or ground through a switch respectively, wherein the capacitance value of the ith capacitor in the first capacitor bank is 2i-1C, i is more than or equal to 1 and less than or equal to N-3, N represents the digit of the digital-to-analog converter, N is more than or equal to 4, and C represents a unit capacitor；
The positive-phase low array comprises a second capacitor and a second capacitor group, a lower plate of the second capacitor and a lower plate of the second capacitor group are both connected to the first input end and the non-inverting input end of the comparator, an upper plate of the second capacitor is selectively connected with a reference voltage or a common-mode voltage or ground through a switch, and an upper plate of the second capacitor group is selectively connected with the reference voltage or the common-mode voltage or the ground through the switch;
the second capacitor group comprises N-3 capacitors, the lower pole plates of the capacitors of the second capacitor group are connected to the first input end and the non-inverting input end of the comparator, the upper pole plates of the capacitors of the second capacitor group are respectively selectively connected with reference voltage or common mode voltage or ground through a switch, and the capacitance value of the ith capacitor in the second capacitor group is 2i-1C，1≤i≤N-3；
The inverting capacitor array comprises an inverting high array and an inverting low array, the second input end is further connected to the inverting input end of the comparator through the inverting high array and the inverting low array, the inverting high array is initially connected to a reference voltage, and the inverting low array is initially connected to the ground.
2. A high accuracy analog to digital converter according to claim 1, wherein said first and second capacitors have a capacitance value of C.
3. A high accuracy analog to digital converter according to claim 1, wherein said inverted high array comprises a third capacitor and a third capacitor bank, a lower plate of said third capacitor and a lower plate of said third capacitor bank are connected to said second input terminal and said inverted input terminal of said comparator, an upper plate of said third capacitor is selectively connected to a reference voltage or a common mode voltage or ground through a switch, and an upper plate of said third capacitor bank is selectively connected to a reference voltage or a common mode voltage or ground through a switch.
4. A high accuracy analog to digital converter according to claim 3,the third capacitor bank comprises N-3 capacitors, the lower electrode plates of the capacitors of the third capacitor bank are connected to the second input end and the inverting input end of the comparator, the upper electrode plates of the capacitors of the third capacitor bank are selectively connected with reference voltage or common mode voltage or ground through switches respectively, and the capacitance value of the ith capacitor in the third capacitor bank is 2i-1And C, i is more than or equal to 1 and less than or equal to N-3, N represents the digit of the digital-to-analog converter, and N is more than or equal to 4.
5. A high accuracy analog to digital converter according to claim 1, wherein said inverted low array comprises a fourth capacitor and a fourth capacitor bank, a lower plate of said fourth capacitor and a lower plate of said fourth capacitor bank are both connected to said second input terminal and to said inverted input terminal of said comparator, an upper plate of said fourth capacitor is selectively connected to a reference voltage or a common mode voltage or ground through a switch, and an upper plate of said fourth capacitor bank is selectively connected to a reference voltage or a common mode voltage or ground through a switch.
6. A high accuracy analog-to-digital converter as claimed in claim 5, wherein said fourth capacitor set comprises N-3 capacitors, the lower plates of the capacitors of said fourth capacitor set are connected to said second input terminal and the inverting input terminal of said comparator, the upper plates of the capacitors of said fourth capacitor set are selectively connected to a reference voltage or a common mode voltage or ground through a switch, respectively, wherein the capacitance value of the ith capacitor in said fourth capacitor set is 2i-1And C, i is more than or equal to 1 and less than or equal to N-3, N represents the digit of the digital-to-analog converter, and N is more than or equal to 4.
7. A high accuracy analog to digital converter according to claim 3, wherein said third capacitor has a capacitance value of C.
8. A high accuracy analog to digital converter according to claim 5, wherein said fourth capacitor has a capacitance value of C.
9. A conversion method applied to a high-precision analog-to-digital converter according to any one of claims 1 to 8, characterized in that in the comparison from 1 st to N-1 st, the in-phase input signal and the reverse input signal of the comparator are kept in a common mode; in the nth comparison, the in-phase input signal and the inverted input signal are not in common mode.
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| CN112865796B (en) * | 2021-01-21 | 2022-05-03 | 电子科技大学中山学院 | Analog-to-digital converter and control method thereof |
| CN117118447B (en) * | 2023-10-24 | 2023-12-22 | 电子科技大学中山学院 | Successive approximation analog-to-digital converter, successive approximation analog-to-digital conversion method, successive approximation analog-to-digital conversion device, and storage medium |
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| CN111371457A (en) * | 2020-03-12 | 2020-07-03 | 东南大学 | Analog-to-digital converter and three-level switching method applied to SAR ADC |
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