CN203968109U - The compensating circuit of a kind of VGA and the front-end processing of color difference components interface signal - Google Patents
The compensating circuit of a kind of VGA and the front-end processing of color difference components interface signal Download PDFInfo
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- CN203968109U CN203968109U CN201420353497.0U CN201420353497U CN203968109U CN 203968109 U CN203968109 U CN 203968109U CN 201420353497 U CN201420353497 U CN 201420353497U CN 203968109 U CN203968109 U CN 203968109U
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Abstract
The compensating circuit that the utility model discloses a kind of VGA and the front-end processing of color difference components interface signal, comprising: an offset signal logical circuit, and input receives offset signal, and output connects biasing circuit; One biasing circuit, input connects offset signal logical circuit, and output connects Anti-aliasing Filter Circuits; One Anti-aliasing Filter Circuits, input connects biasing circuit, and output connects single-ended transfer difference circuit; One single-ended transfer difference circuit, input connects Anti-aliasing Filter Circuits, output connection mode number converter; One analog to digital converter, input connects single-ended transfer difference circuit output digit signals; One average circuit, input connects the output of described analog to digital converter, and output connects another input of described offset signal logical circuit.The utility model adjustable precision is high, and can not introduce other errors, and more high-resolution correction can be provided.
Description
Technical field
The utility model relates to a kind of compensating circuit, relates in particular to the compensating circuit of a kind of VGA and the front-end processing of color difference components interface signal.
Background technology
Because existing VGA and color difference components interface signal can enter universal display chip internal by AC coupled, rebuild benchmark by blanking level/black level of input signal.And, because the AFE (analog front end) of universal display chip itself has clamp circuit, thus can tolerate the variation that input signal is certain, but require the resistance variation enough little and input signal of clamp circuit can not be too large.
Due to VGA and color difference components interface input source itself, and transmission cable do not mate or earth resistance is crossed big city and is made input signal variation very large.In addition, circuit itself is such as the shutoff of clamp switch in clamp circuit, and earth resistance is crossed and mostly may be caused that reference signal produces well-regulated beating, thereby causes that water ripples or band appear in the image that display chip shows.
In addition, existing technology normally deals with last data or is biased circuit at the input of analog to digital converter.Last data are dealt with, may introduce last error, and degree of regulation is limited.Although and before analog to digital converter, adding biasing circuit can heighten precision, its adjustable resolution is not high.
Therefore, prior art is needed the compensating circuit of a kind of better VGA and the front-end processing of color difference components interface signal badly.
Utility model content
The utility model provides the compensating circuit of a kind of VGA and the front-end processing of color difference components interface signal, and its adjustable precision is high, and can not introduce other errors, and more high-resolution correction can be provided.
For solving the problems of the technologies described above, the utility model provides the compensating circuit of a kind of VGA and the front-end processing of color difference components interface signal, comprising:
One offset signal logical circuit, input receives offset signal, and output connects biasing circuit;
One biasing circuit, input connects offset signal logical circuit, and output connects Anti-aliasing Filter Circuits;
One Anti-aliasing Filter Circuits, input connects biasing circuit, and output connects single-ended transfer difference circuit;
One single-ended transfer difference circuit, input connects Anti-aliasing Filter Circuits, output connection mode number converter;
One analog to digital converter, input connects single-ended transfer difference circuit output digit signals;
One average circuit, input connects the output of described analog to digital converter, and output connects another input of described offset signal logical circuit.
Further, the input of offset signal logical circuit described in the utility model also receives random signal.
Further, biasing circuit described in the utility model is digital to analog converter.
Further, the input of Anti-aliasing Filter Circuits described in the utility model also connects a clamp switch.
Further, the input of Anti-aliasing Filter Circuits described in the utility model also connects an ac coupling capacitor, the be connected in parallel input of described Anti-aliasing Filter Circuits of described ac coupling capacitor and described clamp switch.
The utility model adopts average circuit to detect the mean value of the analog to digital converter output of corresponding blanking level/black level, adjust the bias of every row with existing biasing circuit, thereby the variation that erasure signal shake can cause undesirable input signal and circuit compensates.Due to the utility model multiplexing original biasing circuit, and be compensating foremost in input, instead of directly last data are dealt with or add biasing circuit at analog to digital converter front end, so the utility model can produce higher precision, effectively reduce the interference that circuit itself may be introduced.
Brief description of the drawings
Fig. 1 is the electricity of the compensating circuit of the utility model VGA and the front-end processing of color difference components interface signal
Road connection layout.
Fig. 2 is the letter of the compensating circuit of the utility model VGA and the front-end processing of color difference components interface signal
Number schematic diagram.
Fig. 3 is the circuit diagram of the utility model offset signal logical circuit.
Embodiment
Illustrating the utility model below in conjunction with the utility model accompanying drawing realizes.
Referring to Fig. 1, the utility model provides the compensating circuit of a kind of VGA and the front-end processing of color difference components interface signal, comprising:
One offset signal logical circuit, input receives offset signal, and output connects biasing circuit.
One biasing circuit, input connects offset signal logical circuit, and output connects Anti-aliasing Filter Circuits.
One Anti-aliasing Filter Circuits, input connects biasing circuit, and output connects single-ended transfer difference circuit.
One single-ended transfer difference circuit, input connects Anti-aliasing Filter Circuits, output connection mode number converter.
One analog to digital converter, input connects single-ended transfer difference circuit output digit signals.
One average circuit, input connects the output of described analog to digital converter, and output connects another input of described offset signal logical circuit.
The utility model adopts average circuit to detect the mean value of the analog to digital converter output of corresponding blanking level/black level, adjust the bias of every row with existing biasing circuit, thereby the variation that erasure signal shake can cause undesirable input signal and circuit compensates.Due to the utility model multiplexing original biasing circuit, and be compensating foremost in input, instead of directly last data are dealt with or add biasing circuit at analog to digital converter front end, so the utility model can produce higher precision, effectively reduce the interference that circuit itself may be introduced.
Further, the input of Anti-aliasing Filter Circuits described in the utility model also connects a clamp switch.
Further, the input of Anti-aliasing Filter Circuits described in the utility model also connects an ac coupling capacitor, the be connected in parallel input of described Anti-aliasing Filter Circuits of described ac coupling capacitor and described clamp switch.
Referring to Fig. 2, the clamper signal in the utility model compensating circuit obtains by line frequency signal, and reference potential average signal sends after clamper completes.For avoiding being subject to the impact of noise signal and obtaining enough precision and the convenience of circuit realization, the number of times that average circuit is general selects a Nth power accumulative frequency of 2 to average in the output signal of blanking level/black level as analog to digital converter, for example 8/16/32 etc.
In the utility model, Anti-aliasing Filter Circuits, single-ended transfer difference circuit and analog to digital converter all adopt existing circuit structure and Anti-aliasing Filter Circuits, single-ended transfer difference circuit and analog to digital converter indifference with correspondence in existing VGA and the front-end processing of color difference components interface signal, therefore the circuit structure to foregoing circuit repeats no more at this.
Further, biasing circuit described in the utility model is digital to analog converter.
Particularly, the utility model offset signal logical circuit receives offset signal and produces biasing logic signal with the mean value of the analog to digital converter output of the corresponding blanking level/black level of average circuit detecting.
The utility model is in order further to weaken the regularity of input signal interference and the possibility of the rule signal that circuit own may be introduced, and the input of offset signal logical circuit also receives random signal.
Referring to Fig. 3, described offset signal logical circuit comprises the first latch, adds/subtracter, adder and the second latch.Described biasing circuit comprises the first electric current digital to analog converter and the second electric current digital to analog converter (auxiliary current digital to analog converter).Described the first latch receives the mean value of average circuit output and is respectively line frequency or 1/4 line frequency or 1/8 line frequency or 1/2
nline frequency, N=0,2,3 ... pulse signal.The pulse signal of described the first latch output latch give described in add/subtracter, another input receiving target value of described adding/subtracter, described adding/subtracter outputs signal to described adder, another input of described adder receives biasing control word, and output pulse signal is given the first electric current digital to analog converter of described biasing circuit.Described random signal is input to the second latch, and described the second latch is receive clock frequency or 1/16 clock frequency or 1/64 clock frequency or 1/4 also
m, M=0,2,3 ... pulse signal.The output of described the second latch connects the input of described the second electric current digital to analog converter, and another input of described the second electric current digital to analog converter connects Current Control word.
In addition, the unlatching of random signal and the power of adjustment can complete by the control logic circuit of biasing circuit.Random signal generator (not shown) produces parallel random signal, and the frequency of random signal is selected in clock and clock division.By the unitary current of the second electric current D/A converting circuit in variation biasing circuit, the power of random signal is along with variation, so can produce the more high-resolution signal than ADC.
In specific implementation of the present utility model, the utility model is multiplexing original biasing circuit, biasing circuit preferably adopts digital to analog converter, and its structure, with existing circuit structure indifference, therefore repeats no more.
Ac coupling capacitor in parallel with described clamp switch in the utility model, for handing over every straight-through, further ensures signal quality.
The utility model adopts average circuit to detect the mean value of the analog to digital converter output of corresponding blanking level/black level, adjust the bias of every row with existing biasing circuit, thereby the variation that erasure signal shake can cause undesirable input signal and circuit compensates.The utility model does not need all data to do last processing, and the precision of its signal adjustment depends on the precision of biasing circuit, so the precision of its adjustment is high, and the data that can compare are done the last higher resolution correction of processing.
The foregoing is only preferred embodiment of the present utility model; not in order to limit the utility model; all within spirit of the present utility model and principle, any amendment of making, be equal to replacement, improvement etc., within all should being included in the scope of the utility model protection.
Claims (5)
1. a compensating circuit for VGA and the front-end processing of color difference components interface signal, is characterized in that, comprising:
One offset signal logical circuit, input receives offset signal, and output connects biasing circuit;
One biasing circuit, input connects offset signal logical circuit, and output connects Anti-aliasing Filter Circuits;
One Anti-aliasing Filter Circuits, input connects biasing circuit, and output connects single-ended transfer difference circuit;
One single-ended transfer difference circuit, input connects Anti-aliasing Filter Circuits, output connection mode number converter;
One analog to digital converter, input connects single-ended transfer difference circuit output digit signals;
One average circuit, input connects the output of described analog to digital converter, and output connects another input of described offset signal logical circuit.
2. compensating circuit as claimed in claim 1, is characterized in that, the input of described offset signal logical circuit also receives random signal.
3. compensating circuit as claimed in claim 1, is characterized in that, described biasing circuit is digital to analog converter.
4. compensating circuit as claimed in claim 1, is characterized in that, the input of described Anti-aliasing Filter Circuits also connects a clamp switch.
5. compensating circuit as claimed in claim 4, is characterized in that, the input of described Anti-aliasing Filter Circuits also connects an ac coupling capacitor, the be connected in parallel input of described Anti-aliasing Filter Circuits of described ac coupling capacitor and described clamp switch.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420353497.0U CN203968109U (en) | 2014-06-27 | 2014-06-27 | The compensating circuit of a kind of VGA and the front-end processing of color difference components interface signal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420353497.0U CN203968109U (en) | 2014-06-27 | 2014-06-27 | The compensating circuit of a kind of VGA and the front-end processing of color difference components interface signal |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203968109U true CN203968109U (en) | 2014-11-26 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420353497.0U Expired - Fee Related CN203968109U (en) | 2014-06-27 | 2014-06-27 | The compensating circuit of a kind of VGA and the front-end processing of color difference components interface signal |
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| CN (1) | CN203968109U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105577987A (en) * | 2015-11-19 | 2016-05-11 | 大连科迪视频技术有限公司 | VGA signal rectifier and signal rectification method |
-
2014
- 2014-06-27 CN CN201420353497.0U patent/CN203968109U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105577987A (en) * | 2015-11-19 | 2016-05-11 | 大连科迪视频技术有限公司 | VGA signal rectifier and signal rectification method |
| CN105577987B (en) * | 2015-11-19 | 2018-10-02 | 大连科迪视频技术有限公司 | A kind of VGA signals rectifier and signal antidote |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20141126 Termination date: 20160627 |