CN104270149A - Self-adaptive correction starting circuit of analog-digital converter - Google Patents
Self-adaptive correction starting circuit of analog-digital converter Download PDFInfo
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- CN104270149A CN104270149A CN201410485217.6A CN201410485217A CN104270149A CN 104270149 A CN104270149 A CN 104270149A CN 201410485217 A CN201410485217 A CN 201410485217A CN 104270149 A CN104270149 A CN 104270149A
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Abstract
The embodiment of the invention discloses a self-adaptive correction starting circuit. The self-adaptive correction starting circuit comprises a signal judging circuit, a clock controlling circuit, a delay circuit and an output circuit. The signal judging circuit judges a signal to be detected and generates a corresponding control signal to control the delay circuit. The clock controlling circuit is used for generating a clock signal needed by the circuit for normal work. The delay circuit generates a delayed enable signal and outputs the delayed enable signal to control the output circuit. The output circuit generates and outputs a corresponding correction control signal under the control of the signal judging circuit, the output signal of the delay circuit and the clock signal. According to the correction starting circuit, the function of correction starting can be realized after the signal to be detected becomes stable, the situation that a correcting circuit is also started when a signal to be detected is ineffective is effectively avoided, the correction starting circuit stops working after the correcting circuit is started, and therefore power consumption is reduced; meanwhile, a secondary correction function is further achieved.
Description
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Technical field
The present invention relates to analog to digital converter technical field, especially relate to a kind of adaptively correcting start-up circuit of analog to digital converter.
Background technology
Analog to digital converter (ADC) is the bridge that analog signal is changed to digital signal, plays very important effect in mixed-signal system.Although natural actual physics signal is all analog signal, current most signal transacting and signal storage all realize in digital field.Along with developing rapidly of CMOS integrated circuit fabrication process, the function of Digital Signal Processing is more complicated and diversified.As the interface between simulated world and digital field, Digital Signal Processing is more and more higher to ADC performance requirement, and High Performance ADC has become an indispensable part in modern signal processing system.
In order to solve the difficulty of under deep-submicron even nanometer CMOS technique ADC design, improve integrated circuit dimensions continue can contractility, Recent study person proposes various scheme.Such as Brooks proposes the circuit based on zero passage principle, has abandoned the operation of amplifying voltage signal, and voltage signal is transformed into current field by employing, then to the scheme that current signal amplifies.The ADC of current-mode that Krishna proposes in addition have employed current subtraction technology and carrys out alternative traditional voltage operational amplifier etc.These methods are in current field or time-domain Analog signals; eliminate the reduction of supply power voltage and the available signal amplitude of oscillation to signal SNR(signal to noise ratio) adverse effect that causes; but usually can with other performance index of sacrifice circuit for cost, such as chip area, bandwidth or power consumption.
Consider the trend of the lasting advantage that technique evolution brings digital circuit and mixed signal circuit development, a kind of defect, technology of improving circuit performance using digital signal processing method to compensate or correct CMOS technique Imitating circuit gets the attention and fast-developing.So-called figure adjustment technology that Here it is.This technology can break through the restriction of chip technology condition and circuit design level, mismatch (as capacitance size error), harmonic distortion (as amplifier nonlinearity) etc. in the manufacture process using DSP to be caused by Uncertainty in circuit, thus improve precision and the linearity of ADC.
And in figure adjustment technology, correct start-up circuit and there is very important effect.Correct start-up circuit and mainly after receiving analog signal, carry out certain process, and generation corrects enable signal accordingly.But correction start-up circuit of the prior art always has some shortcomings, some start-up circuit distinguishing rule is unreasonable, to such an extent as to when occurring that invalid signals arrives, the situation that correcting circuit is also activated; Some start-up circuit is also in operating state after correcting circuit normally works always, thus wastes power consumption; Although some start-up circuit in work, can not save power consumption, needs timing again at circuit, cannot normally start secondary correction function after correcting circuit normally works.
Summary of the invention
An object of the present invention is to provide a kind of correction start-up circuit that just can start correcting circuit after measured signal is stablized.
An object of the present invention be to provide one can after correcting circuit normally works out-of-work correction start-up circuit.
Technical scheme disclosed by the invention comprises:
Provide a kind of adaptively correcting start-up circuit of analog to digital converter, it is characterized in that, comprise: signal discrimination circuit 10, described signal discrimination circuit 10 receives measured signal, carries out judging and produce the first control signal EN based on result of determination to measured signal, and the analog level of supply voltage is converted to digital level; Clock control circuit 20, described clock control circuit 20 produces clock control signal CK; Delay circuit 30, described delay circuit 30 receives described first control signal EN and described clock control signal CK, and by described first at least one cycle of control signal EN time delay, exports time delay first control signal EN_delay; Output circuit 40, described output circuit produces correcting controlling signal Cali_EN and first output signal On according to described time delay first control signal EN_delay, described clock control signal CK and described first control signal EN; Wherein said clock control circuit 20 produces described clock control signal CK based on described correcting controlling signal Cali_EN, described first output signal On and clock signal clk.
In one embodiment of the present of invention, described signal discrimination circuit 10 comprises the first NAND gate 101, inverter 102 and level shifting circuit 103, wherein: the first input end of described first NAND gate 101 is connected to described measured signal test, the output of described first NAND gate 101 is connected to the input of described inverter 102; The output of described inverter 102 is connected to the input of described level shifting circuit 103, and the output of described level shifting circuit 103 exports described first control signal EN.
In one embodiment of the present of invention, described clock control circuit 20 comprises the second NAND gate 201 and first and door 202, wherein: the first input end of described second NAND gate 201 is connected to described correcting controlling signal Cali_EN, second input of described second NAND gate 201 is connected to described first output signal On, and the output of described second NAND gate 201 is connected to the second input of described first and door 202; Described first is connected to described clock signal clk with the first input end of door 202, and described first exports described clock control signal CK with the output of door 202.
In one embodiment of the present of invention, described delay circuit 30 comprises time-delay unit circuit 301, the first input end of described time-delay unit circuit 301 is connected to described clock control signal CK, and the enable input of described time-delay unit circuit 301 is connected to described first control signal EN.
In one embodiment of the present of invention, described output circuit 40 comprises second and door 401 and d type flip flop 403, wherein: described second is connected to described time delay first control signal EN_delay with the first input end of door 401, described second is connected to described first control signal EN with the second input of door 401, and described second exports described first with the output of door 401 outputs signal On and is connected to the first input end RST of described d type flip flop 403; Second input CLK of described d type flip flop 403 is connected to described clock control signal CK, and the output of described d type flip flop 403 exports described correcting controlling signal Cali_EN.
The correction start-up circuit of the embodiment of the present invention can realize correcting the function started after measured signal is stablized, effectively prevent measured signal invalid time correcting circuit situation about being also activated, then quit work after circuit start to be corrected, can power consumption be saved, meanwhile, also there is the function of secondary correction.
Accompanying drawing explanation
Fig. 1 is the structured flowchart schematic diagram of the adaptively correcting start-up circuit of the analog to digital converter of one embodiment of the invention.
Fig. 2 is the structural representation of the signal discrimination circuit of one embodiment of the invention.
Fig. 3 is the structural representation of the clock control circuit of one embodiment of the invention.
Fig. 4 is the structural representation of the delay circuit of one embodiment of the invention.
Fig. 5 is the structural representation of the output circuit of one embodiment of the invention.
Embodiment
The concrete structure of the adaptively correcting start-up circuit of the analog to digital converter of embodiments of the invention is described in detail below in conjunction with accompanying drawing.
As shown in Figure 1, in one embodiment of the present of invention, a kind of adaptively correcting start-up circuit of analog to digital converter comprises signal discrimination circuit 10, clock control circuit 20, delay circuit 30 and output circuit 40.
Signal discrimination circuit 10 receives measured signal test, judges and produce the first control signal EN based on result of determination to this measured signal test.In addition, the analog level of supply voltage is also converted to digital level by signal discrimination circuit 10.
Clock control circuit 20 is connected on output circuit 40, and correcting controlling signal Cali_EN and the first output signal On(receiving output circuit 40 generation hereinafter describes in detail).Clock control circuit 20 goes back receive clock signal clk.
Clock control circuit 20 produces clock control signal CK based on this correcting controlling signal Cali_EN, the first output signal On and clock signal clk.
Delay circuit 30 is connected to clock control circuit 20 and signal discrimination circuit 10, receives aforesaid first control signal EN and clock control signal CK, and by first at least one cycle of control signal EN time delay, thus export time delay first control signal EN_delay.
Output circuit 40 is connected to signal discrimination circuit 10, clock control circuit 20 and delay circuit 30, receives aforesaid first control signal EN, clock control signal CK and time delay first control signal EN_delay respectively from it.Output circuit 40 produces correcting controlling signal Cali_EN and first output signal On according to this time delay first control signal EN_delay, clock control signal CK and the first control signal EN.This correcting controlling signal Cali_EN is for controlling the calibration function of analog to digital converter.
Visible, in embodiments of the invention, output circuit 40 output calibration control signal Cali_EN is the time delay first control signal EN_delay co-controlling by time delay that produces of the first control signal EN of being produced by signal discrimination circuit 10 and delay circuit 30, therefore efficiently avoid the phenomenon that when invalid measured signal arrives, correcting circuit is activated.
As shown in Figure 2, in one embodiment of the present of invention, signal discrimination circuit 10 can comprise the first NAND gate 101, inverter 102 and level shifting circuit 103.
The first input end of the first NAND gate 101 is connected to measured signal test, and the output tinB of the first NAND gate 101 is connected to the input of inverter 102.
The output tin of inverter 102 is connected to the input of level shifting circuit 103, and the output of level shifting circuit 103 exports the first control signal EN.
As shown in Figure 3, in one embodiment of the present of invention, clock control circuit 20 can comprise the second NAND gate 201 and first and door 202.
The first input end of the second NAND gate 201 is connected to correcting controlling signal Cali_EN, second input of the second NAND gate 201 is connected to the first output signal On of output circuit 40 output, and the output of the second NAND gate 201 is connected to the second input of first and door 202.
First is connected to clock signal clk with the first input end of door 202, first with the output output clock control signal CK of door 202.
In the present embodiment, when there being low level in signal Cali_EN and On, the clock signal clk of input is output by clock control signal CK; When signal Cali_EN and On is high level, clock control signal CK is low level, and input clock signal clk cannot be transmitted, and delay circuit 30 and output circuit 40 are all closed, thus save power consumption.
As shown in Figure 4, in one embodiment of the present of invention, delay circuit 30 can comprise time-delay unit circuit 301, and the first input end of time-delay unit circuit 301 is connected to clock control signal CK, and the enable input of time-delay unit circuit 301 is connected to the first control signal EN.
As shown in Figure 5, in one embodiment of the present of invention, output circuit 40 comprises second and door 401 and d type flip flop 403.
Second is connected to aforesaid time delay first control signal EN_delay with the first input end of door 401, second is connected to the first control signal EN with the second input of door 401, and second exports first with the output of door 401 outputs signal On and is connected to the first input end RST of d type flip flop 403.
Second input CLK of d type flip flop 403 is connected to clock control signal CK, the output output calibration control signal Cali_EN of d type flip flop 403.
In addition, input CLR and D of d type flip flop 403 meets digital power DVDD, and input DB meets digitally DGND.
In one embodiment of the present of invention, the operation principle of this adaptively correcting start-up circuit as mentioned below.
(1) test<V is worked as
0(V
0reference potential for setting) time, in signal discrimination circuit, the output tin of inverter 102 is low level, and the output EN of level shifting circuit 103 is low level, and supply voltage is transformed into digital 3.3V from simulation 5V by level shifting circuit 103 simultaneously; In clock control circuit 20, because before correcting circuit startup, Cali_EN is always low level, therefore the output of the second NAND gate 201 is high level, first with the output CK=clk of door 202, the clock signal clk of input is output by clock control signal CK; In delay circuit 301, because Enable Pin EN(namely can control signal EN) be low level, therefore the output EN_delay of time-delay unit circuit 301 is low level; In output circuit 40, because EN and EN_delay is low level, therefore second is low level with the output On of door 401, and meanwhile, the output Cali_EN of d type flip flop 403 is low level, and correcting circuit cannot start.
(2) increase to gradually and V when test is ascending
0time equal, in signal discrimination circuit 10, the output tin of inverter 102 is high level, and the output EN of level shifting circuit 103 is high level, and supply voltage is transformed into digital 3.3V from simulation 5V by level shifting circuit 103 simultaneously; In clock control circuit 20, because Cali_EN before starting at correcting circuit is always low level, therefore the output of the second NAND gate 201 is high level, first with the output CK=clk of door 202, input clock signal clk is output by clock control signal CK; In delay circuit 30, although now Enable Pin EN is high level, what transmit due to time-delay unit circuit 301 be n(n is set delay cycle number) the first control signal EN before the individual clock cycle, therefore its to export En_delay be still low level; In output circuit 40, due to EN be high level, EN_delay is low level, therefore second is low level with the output On of door 401, and meanwhile, the output Cali_EN of d type flip flop 403 is low level, and correcting circuit cannot start.In the circuit, only have when signal differentiates electricity, the correction enabling signal Cali_EN that when what 10 enable signal (the first control signal) EN exported and delay circuit 30 exported is high level by the enable signal of time delay (time delay first control signal) EN_delay simultaneously, whole circuit exports could be high level, correcting circuit just can be activated, and therefore avoids the phenomenon that when invalid test signal (as occurred a spike) is transfused to, correcting circuit is activated.
(3) V is greater than when test is stabilized in
0state time, in signal discrimination circuit 10, the output tin of inverter 102 is high level, and the output EN of level shifting circuit 103 is high level, and simultaneously supply voltage is transformed into digital 3.3V from simulation 5V by level shifting circuit; In clock control circuit 20, because Cali_EN before starting at correcting circuit is always low level, therefore the output of the second NAND gate 201 is high level, first with the output CK=clk of door 202, input clock signal clk is output by clock control signal CK; In delay circuit 30, because Enable Pin EN is high level, although time-delay unit circuit 301 transmission is n clock cycle enable signal in the past, because circuit is stablized, namely before n clock, EN is also high level, therefore its output EN_delay is high level; In output circuit 40, because EN and EN_delay is high level, therefore second is high level with the output On of door 401, and meanwhile, the output Cali_EN of d type flip flop 403 is high level, and correcting circuit can be activated.
(4) after Cali_En is high level, correcting circuit startup, test still keeps being greater than V
0state, in signal discrimination circuit 10, the output tin of inverter 102 is high level, and the output EN of level shifting circuit 103 is high level, and simultaneously supply voltage is transformed into digital 3.3V from simulation 5V by level shifting circuit; In clock control circuit 20, because Cali_EN and On signal is high level, therefore the output of the second NAND gate 201 is low level, first is low level with the output CK of door 202, clock signal clk cannot be transmitted, so delay circuit below and output circuit are all closed, thus save power consumption.
(5) after correcting circuit normally starts, if measured signal test is reduced to again be less than V
0, then correcting circuit has been closed, and needs restarting correcting circuit.Now correction start-up circuit can repeat the work described in (1) ~ (4), carries out secondary correction.Therefore this circuit has good flexibility.
In embodiments of the invention, correct start-up circuit and just can realize correcting the function started after measured signal is stablized, effectively prevent measured signal invalid time correcting circuit situation about being also activated; Then quit work after circuit start to be corrected, thus save power consumption, meanwhile, when needs restarting correcting circuit, this correction start-up circuit also has the function of secondary correction.
Described the present invention by specific embodiment above, but the present invention is not limited to these specific embodiments.It will be understood by those skilled in the art that and can also make various amendment, equivalent replacement, change etc. to the present invention, as long as these conversion do not deviate from spirit of the present invention, all should within protection scope of the present invention.In addition, " embodiment " described in above many places represents different embodiments, can certainly by its all or part of combination in one embodiment.
Claims (5)
1. an adaptively correcting start-up circuit for analog to digital converter, is characterized in that, comprising:
Signal discrimination circuit (10), described signal discrimination circuit (10) receives measured signal, carries out judging and produce the first control signal (EN) based on result of determination to measured signal, and the analog level of supply voltage is converted to digital level;
Clock control circuit (20), described clock control circuit (20) produces clock control signal (CK);
Delay circuit (30), described delay circuit (30) receives described first control signal (EN) and described clock control signal (CK), and by described first control signal (EN) at least one cycle of time delay, export time delay first control signal (EN_delay);
Output circuit (40), described output circuit produces correcting controlling signal (Cali_EN) and the first output signal (On) according to described time delay first control signal (EN_delay), described clock control signal (CK) and described first control signal (EN);
Wherein said clock control circuit (20) produces described clock control signal (CK) based on described correcting controlling signal (Cali_EN), described first output signal (On) and clock signal (clk).
2. circuit as claimed in claim 1, is characterized in that: described signal discrimination circuit (10) comprises the first NAND gate (101), inverter (102) and level shifting circuit (103), wherein:
The first input end of described first NAND gate (101) is connected to described measured signal (test), and the output of described first NAND gate (101) is connected to the input of described inverter (102);
The output of described inverter (102) is connected to the input of described level shifting circuit (103), and the output of described level shifting circuit (103) exports described first control signal (EN).
3. as described in claim 1 or 2 circuit, is characterized in that: described clock control circuit (20) comprises the second NAND gate (201) and first and door (202), wherein:
The first input end of described second NAND gate (201) is connected to described correcting controlling signal (Cali_EN), second input of described second NAND gate (201) is connected to described first output signal (On), and the output of described second NAND gate (201) is connected to the second input of described first and door (202);
Described first is connected to described clock signal (clk) with the first input end of door (202), and described first exports described clock control signal (CK) with the output of door (202).
4. as the circuit in claims 1 to 3 as described in any one, it is characterized in that: described delay circuit (30) comprises time-delay unit circuit (301), the first input end of described time-delay unit circuit (301) is connected to described clock control signal (CK), and the enable input of described time-delay unit circuit (301) is connected to described first control signal (EN).
5. as the circuit in Claims 1-4 as described in any one, it is characterized in that: described output circuit (40) comprises second and door (401) and d type flip flop (403), wherein:
Described second is connected to described time delay first control signal (EN_delay) with the first input end of door (401), described second is connected to described first control signal (EN) with the second input of door (401), and described second exports described first with the output of door (401) outputs signal (On) and is connected to the first input end (RST) of described d type flip flop (403);
Second input (CLK) of described d type flip flop (403) is connected to described clock control signal (CK), and the output of described d type flip flop (403) exports described correcting controlling signal (Cali_EN).
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| CN201410485217.6A CN104270149B (en) | 2014-09-22 | 2014-09-22 | A kind of adaptively correcting start-up circuit of analog-digital converter |
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| CN107179801A (en) * | 2017-05-31 | 2017-09-19 | 北京集创北方科技股份有限公司 | Digital-to-analogue integrated circuit and its control method |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106680613A (en) * | 2015-11-11 | 2017-05-17 | 中车大连电力牵引研发中心有限公司 | Method and device for detecting power quality of auxiliary power system of rail transit vehicle |
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