CN105024682A - I/O interface driving circuit capable of automatically controlling noise - Google Patents

I/O interface driving circuit capable of automatically controlling noise Download PDF

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Publication number
CN105024682A
CN105024682A CN201510290280.9A CN201510290280A CN105024682A CN 105024682 A CN105024682 A CN 105024682A CN 201510290280 A CN201510290280 A CN 201510290280A CN 105024682 A CN105024682 A CN 105024682A
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China
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type transistor
interface
crystal pipe
output
type crystal
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CN201510290280.9A
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Chinese (zh)
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谢憬
程秀兰
刘婷
付宇卓
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镇江天美信息科技有限公司
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Priority to CN201510290280.9A priority Critical patent/CN105024682A/en
Publication of CN105024682A publication Critical patent/CN105024682A/en

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Abstract

The invention provides an I/O interface driving circuit capable of automatically controlling noise. The I/O interface driving circuit comprises an N-type transistor output driving circuit and a P-type transistor output driving circuit. The output signal and the input signal of an I/O interface are combined to form a combined signal for controlling the N-type transistor output driving circuit and the P-type transistor output driving circuit. Further, the combined signal is used for eliminating level bounce induced by a power end and a ground end when the output signal of the I/O interface is inverted. A first time delay circuit is used for adjusting the driving capability of the N-type transistor output driving circuit. A second time delay circuit is used for adjusting the driving capability of the P-type transistor output driving circuit. Thus, voltage overshoot of the output signal of the I/O interface is prevented; smoothness at the later inverting period of the output signal of the I/O interface is achieved; and the noise suppression capability of the I/O interface is improved.

Description

The I/O interface driving circuit of automatic control noises

Technical field

The present invention relates to IC design field, especially a kind of I/O interface driving circuit of automatic control noises.

Background technology

In large-scale digital ic design, because the peripheral hardware of advanced person is as the high-speed demand to chip signal output such as SRAM, the I/O interface output signal of chip needs to realize overturning fast.Though simple large driving force I/O interface can meet the high speed change of output signal, output signal can be caused to occur too much high-frequency noise, and produce other adverse influences.As the shake (Bounce) that power and ground induces, the time delay causing signal to arrive stable state increases, and even occurs error message; Appearance crosstalk (Crosstalk) between output signal can cause the phenomenon such as erroneous trigger and correct signal conductively-closed.The producing cause of these Noise and Interferences, be all often the large scale metal-oxide-semiconductor drives hyperenergia due to I/O interface output driving part and shortage effectively control, the output signal voltage value caused on I/O interface driving circuit produces larger sudden change, the even phenomenon of voltage overshoot (overshoot) and level shake, the IC chip that these phenomenons can make to be applied to such as wireless telecommunications system (PDA etc.) cannot meet the requirement of system to its voltage amplitude outputed signal and precision and noise limit.

Will under ensureing that the output of I/O interface can realize the prerequisite of high-speed turnover, reduce noise in output signal and on the noise of power supply and high fdrequency component on the impact of system, just must comprise the control of the aspects such as level rate of change (slew rate), voltage overshoot and level shake to the output signal of I/O interface.In common I/O interface circuit structure, just achieve the high speed change of level simply, though it has certain noise suppressing function, but its implementation only relies on the adjustment to output driving circuit driving force, i.e. metal-oxide-semiconductor size, when connecting different output loadings, it differs greatly to the control ability of the aspects such as voltage overshoot, and designer can not be allowed satisfied.

Fig. 1 is the simulation waveform figure of I/O interface input/output signal in prior art, and wherein, ordinate is the input voltage/output voltage of I/O interface, represents with V, and abscissa is the time, represents with t, and 103 is input waveform, and 104 is output waveform.As seen from Figure 1, the output signal of I/O interface there will be far above 3.3V or far below the low level voltage overshoot situation of 0V in level switching process, and there is considerable high frequency harmonic components latter stage in upset, thus causes severe noise effect; After having overturn, still there is jitter conditions in output signal level, even there will be substandard high level signal (Voh) or the low level signal (Vol) higher than standard, thus can cause the misoperation controlled peripheral hardware.

Summary of the invention

The object of the present invention is to provide a kind of I/O interface driving circuit of automatic control noises, to solve in prior art I/O interface circuit to the problem of noise inhibiting ability deficiency.

In order to achieve the above object, the invention provides a kind of I/O interface driving circuit of automatic control noises, comprise: N-type transistor output driving circuit and P-type crystal pipe output driving circuit, described N-type transistor output driving circuit is all connected with the output of I/O interface with described P-type crystal tube drive circuit;

Described N-type transistor output driving circuit comprises: the first N-type transistor, the second N-type transistor, the 3rd N-type transistor and the 4th N-type transistor;

The grid of described first N-type transistor is connected with the input of I/O interface, and the substrate of described first N-type transistor and the substrate of described second N-type transistor are connected to a first node, and the source electrode of described first N-type transistor is connected with described first node;

The source electrode of described second N-type transistor is connected with the drain electrode of described first N-type transistor, the drain electrode of described second N-type transistor is connected with the output of described I/O interface, the grid of described second N-type transistor is connected with the output of one first NOR gate by one first time delay circuit, and the input of described I/O interface is connected with two inputs of described first NOR gate respectively with output;

The described grid of the 3rd N-type transistor and the grid of the first N-type transistor are connected to a Section Point, described Section Point is connected with the input of described I/O interface, the substrate of described 3rd N-type transistor and the substrate of described 4th N-type transistor are connected to one the 3rd node, the source electrode of described 3rd N-type transistor is connected with described 3rd node, described 3rd node and described first node are connected to one the 4th node, described 4th node ground connection;

The source electrode of described 4th N-type transistor is connected with the drain electrode of described 3rd N-type transistor, the drain electrode of described 4th N-type transistor is connected with the output of described I/O interface, the grid of described 4th N-type transistor is connected with the output of one first NAND gate, and the output of described first NOR gate is connected with two inputs of described first NAND gate respectively with described 4th node;

Described P-type crystal pipe output driving circuit comprises: the first P-type crystal pipe, the second P-type crystal pipe, the 3rd P-type crystal pipe and the 4th P-type crystal pipe;

The grid of described first P-type crystal pipe is connected with the input of described I/O interface, and the substrate of described first P-type crystal pipe and the substrate of described second P-type crystal pipe are connected to one the 5th node, and the source electrode of described first P-type crystal pipe is connected with described 5th node;

The source electrode of described second P-type crystal pipe is connected with the drain electrode of described first P-type crystal pipe, the drain electrode of described second P-type crystal pipe is connected with the drain electrode of described second N-type transistor, and be connected with the output of described I/O interface, the grid of described second P-type crystal pipe is connected with the output of one second NAND gate by one second time delay circuit, and the input of described I/O interface is connected with two inputs of described second NAND gate respectively with output;

Grid and the described first P-type crystal pipe of described 3rd P-type crystal pipe are connected to one the 6th node, described 6th node is connected with the input of described I/O interface, the substrate of described 3rd P-type crystal pipe and the substrate of described 4th P-type crystal pipe are connected to one the 7th node, the source electrode of described 3rd P-type crystal pipe is connected with described 7th node, described 7th node and described 5th node are connected to one the 8th node, described 8th node ground connection;

The source electrode of described 4th P-type crystal pipe is connected with the drain electrode of described 3rd P-type crystal pipe, the drain electrode of described 4th P-type crystal pipe is connected with the drain electrode of described 4th N-type transistor, and be connected with the output of described I/O interface, the grid of described 4th P-type crystal pipe is connected with the output of one second NOR gate, and the output of described second NAND gate is connected with two inputs of described second NOR gate respectively with described 8th node.

Preferably, in the I/O interface driving circuit of above-mentioned automatic control noises, the I/O interface driving circuit of described automatic control noises also comprises one first inverter, the output of described first NOR gate is connected with the input of described first inverter after described first time delay circuit, and the output of described first inverter is connected with the grid of described second N-type transistor.

Preferably, in the I/O interface driving circuit of above-mentioned automatic control noises, the I/O interface driving circuit of described automatic control noises also comprises one second inverter, the input of described I/O interface is connected with the input of described second inverter, and the output of described second inverter is connected with described Section Point.

Preferably, in the I/O interface driving circuit of above-mentioned automatic control noises, the I/O interface driving circuit of described automatic control noises also comprises one the 3rd inverter, the output of described second NAND gate is connected with the input of described 3rd inverter after described second time delay circuit, and the output of described 3rd inverter is connected with the grid of described second P-type crystal pipe.

Preferably, in the I/O interface driving circuit of above-mentioned automatic control noises, the I/O interface driving circuit of described automatic control noises also comprises one the 4th inverter, the input of described I/O interface is connected with the input of described 4th inverter, and the output of described 4th inverter is connected with described 6th node.

Preferably, in the I/O interface driving circuit of above-mentioned automatic control noises, the breadth length ratio of described first N-type transistor and described second N-type transistor is greater than the breadth length ratio of described 3rd N-type transistor and described 4th N-type transistor.

Preferably, in the I/O interface driving circuit of above-mentioned automatic control noises, the breadth length ratio of described first N-type transistor is equal with the breadth length ratio of described second N-type transistor, and the breadth length ratio of described 3rd N-type transistor is equal with the breadth length ratio of described 4th N-type transistor.

Preferably, in the I/O interface driving circuit of above-mentioned automatic control noises, the breadth length ratio of described first P-type crystal pipe and described second P-type crystal pipe is greater than the breadth length ratio of described 3rd P-type crystal pipe and described 4th P-type crystal pipe.

Preferably, in the I/O interface driving circuit of above-mentioned automatic control noises, the breadth length ratio of described first P-type crystal pipe is equal with the breadth length ratio of described second P-type crystal pipe, and the breadth length ratio of described 3rd P-type crystal pipe is equal with the breadth length ratio of described 4th P-type crystal pipe.

Preferably, in the I/O interface driving circuit of above-mentioned automatic control noises, the I/O interface driving circuit of described automatic control noises also comprises one first resistance, and described 4th node is by described first grounding through resistance.

Preferably, in the I/O interface driving circuit of above-mentioned automatic control noises, the I/O interface driving circuit of described automatic control noises also comprises one second resistance, and described 8th node is by described second grounding through resistance.

In the I/O interface driving circuit of automatic control noises provided by the invention, the control to N-type transistor output driving circuit and P-type crystal tube drive circuit will be realized after the output signal of described I/O interface and input signal combination, simultaneously, utilize the level shake that combinations thereof signal elimination power end and ground end induce when the output signal upset of described I/O interface, and utilize described first time delay circuit to adjust the driving force of described N-type transistor output driving circuit, utilize described second time delay circuit to adjust the driving force of described P-type crystal tube drive circuit, to prevent the output signal voltage overshoot of described I/O interface, the output signal realizing described I/O interface overturns the smoothing in latter stage, improve the noise inhibiting ability of described I/O interface circuit.

Accompanying drawing explanation

Fig. 1 is the simulation waveform figure of I/O interface input/output signal in prior art;

The I/O interface driving circuit figure of automatic control noises of Fig. 2 for providing in the embodiment of the present invention;

The simulation waveform figure of the output signal of the I/O interface driving circuit of automatic control noises of Fig. 3 for providing in the embodiment of the present invention;

In figure: N1-first N-type transistor; N2-second N-type transistor; N3-the 3rd N-type transistor; N4-the 4th N-type transistor; P1-first P-type crystal pipe; P2-second P-type crystal pipe; P3-the 3rd P-type crystal pipe; P4-the 4th P-type crystal pipe; G1-first NOR gate; G2-first inverter; G3-second inverter; G4-first NAND gate; G5-second NAND gate; G6-the 3rd inverter; G7-the 4th inverter; G8-second NOR gate; R1-first resistance; R2-second resistance; A-first node; B-Section Point; C-the 3rd node; D-the 4th node; L-the 5th node; M-the 6th node; S-the 7th node; U-the 8th node; 101-first time delay circuit; 102-second time delay circuit; 103-input waveform; 104-output waveform; 105-input waveform; 106-output waveform; The input of 107-I/O interface; The output of 108-I/O interface.

Embodiment

Below in conjunction with schematic diagram, the specific embodiment of the present invention is described in more detail.According to following description and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts the form that simplifies very much and all uses non-ratio accurately, only in order to object that is convenient, the aid illustration embodiment of the present invention lucidly.

The invention provides a kind of I/O interface driving circuit of automatic control noises, as shown in Figure 2, comprise: N-type transistor output driving circuit and P-type crystal pipe output driving circuit, wherein, described N-type transistor output driving circuit comprises: the first N-type transistor N1, second N-type transistor N2, 3rd N-type transistor N3 and the 4th N-type transistor N4, the breadth length ratio of described first N-type transistor N1 and described second N-type transistor N2 is greater than the breadth length ratio of described 3rd N-type transistor N3 and described 4th N-type transistor N4, and the breadth length ratio of the breadth length ratio of described first N-type transistor N1 and described second N-type transistor N2 is equal, the breadth length ratio of described 3rd N-type transistor N3 is equal with the breadth length ratio of described 4th N-type transistor N4.Described N-type transistor output driving circuit is different and cause the N-type transistor of the driving force series connection of difference to some extent to form by two cover sizes, utilizes the described first N-type transistor N1 of large driving force and described second N-type transistor N2 to achieve the high-speed turnover of level.

Concrete, as shown in Figure 2, described first N-type transistor N1 and described second N-type transistor N2 series connection, concrete, the substrate of described first N-type transistor N1 and the substrate of described second N-type transistor N2 are connected to a first node A, the source electrode of described first N-type transistor N1 is connected with described first node A, the drain electrode of described first N-type transistor N1 is connected with the source electrode of described second N-type transistor N2, the grid of described first N-type transistor N1 and the grid of described 3rd N-type transistor N3 are connected to a Section Point B, described Section Point B is connected with the input 107 of described I/O interface by one second inverter G3, described first N-type transistor N1 and described 3rd N-type transistor N3 is made to have identical control signal, and the switch situation of described first N-type transistor N1 and described 3rd N-type transistor N3 keeps synchronous substantially with the input signal of described I/O interface.Further, described Section Point B is connected with the output of described second inverter G3, and the input of described second inverter G3 is connected with the input 107 of described I/O interface.

The drain electrode of described second N-type transistor N2 is connected with the output 108 of described I/O interface, the grid of described second N-type transistor N2 and the output of one first inverter G2, the input of described first inverter G2 is connected with the output of one first NOR gate G1 by one first time delay circuit 101, and the input 107 of described I/O interface is connected with two inputs of described first NOR gate G1 respectively with output.That is, the output signal of described I/O interface feeds back to the input of described first NOR gate G1, with the input signal of described I/O interface jointly after described first NOR gate G1, then as the control signal of described second N-type transistor N2 after described first time delay circuit 101.

The described grid of the 3rd N-type transistor N3 and the grid of the first N-type transistor N1 are connected to a Section Point B, described Section Point B is connected with the input 107 of described I/O interface by described second inverter G3, and the control signal of described 3rd N-type transistor N3 and described first N-type transistor N1 is synchronous.Described 3rd N-type transistor N3 and described 4th N-type transistor N4 series connection, concrete, the substrate of described 3rd N-type transistor N3 and the substrate of described 4th N-type transistor N4 are connected to one the 3rd node C, the source electrode of described 3rd N-type transistor N3 is connected with described 3rd node C, the drain electrode of described 3rd N-type transistor N3 is connected with the source electrode of described 4th N-type transistor N4, described 3rd node C and described first node A is connected to one the 4th node D, described 4th node D is by one first resistance R1 ground connection, the overshoot that the output voltage that described first resistance R1 reduces described I/O interface produces in switching process.

The drain electrode of described 4th N-type transistor N4 is connected with the output 108 of described I/O interface, the grid of described 4th N-type transistor N4 is connected with the output of one first NAND gate G4, and the output of described first NOR gate G1 is connected with two inputs of described first NAND gate G4 respectively with described 4th node D

That is, large-sized described first N-type transistor N1 and described second N-type transistor N2 is composed in series the first order output driving circuit of a N-type transistor, undersized described 3rd N-type transistor N3 and described 4th N-type transistor N4 is composed in series the second level output driving circuit of a N-type transistor, two cover sizes are different and cause the N-type transistor output driving circuit that the N-type transistor of the driving force series connection of difference is to some extent formed, the described first N-type transistor N1 of large driving force and described second N-type transistor N2 is utilized to achieve the high-speed turnover of level, and pass through the grid of the signal feedback of described I/O interface output to described second N-type transistor N2 and described 4th N-type transistor N4, as the control signal of described second N-type transistor N2 and described 4th N-type transistor N4, thus achieve the initial stage of output level in upset from high level to low level of described I/O interface, the fast conducting of described N-type transistor output driving circuit is with closed, and described output level is in the smoothing overturning signal in latter stage from high level to low level.

Further, described first inverter G2 and described second inverter G3 can improve the driving force of described N-type transistor output driving circuit, prevents the switch time delay of described first N-type transistor N1 and described second N-type transistor N2 long.

Described P-type crystal pipe output driving circuit comprises: the first P-type crystal pipe P1, the second P-type crystal pipe P2, the 3rd P-type crystal pipe P3 and the 4th P-type crystal pipe P4, the breadth length ratio of described first P-type crystal pipe P1 and described second P-type crystal pipe P2 is greater than the breadth length ratio of described 3rd P-type crystal pipe P3 and described 4th P-type crystal pipe P4, and the breadth length ratio of the breadth length ratio of described first P-type crystal pipe P1 and described second P-type crystal pipe P2 is equal, the breadth length ratio of described 3rd P-type crystal pipe P3 is equal with the breadth length ratio of described 4th P-type crystal pipe P4.Described P-type crystal pipe output driving circuit is different and cause the P-type crystal pipe of the driving force series connection of difference to some extent to form by two cover sizes, utilizes the described first P-type crystal pipe P1 of large driving force and described second P-type crystal pipe P2 to achieve the high-speed turnover of level.

Concrete, as shown in Figure 2, described first P-type crystal pipe P1 and described second P-type crystal pipe P2 connects, concrete, the substrate of described first P-type crystal pipe P1 and the substrate of described second P-type crystal pipe P2 are connected to one the 5th node L, the source electrode of described first P-type crystal pipe P1 is connected with described 5th node L, the drain electrode of described first P-type crystal pipe P1 is connected with the source electrode of described second P-type crystal pipe P2, the grid of described first P-type crystal pipe P1 and the grid of described 3rd P-type crystal pipe P3 are connected to one the 6th node M, described 6th node M is connected with the input 107 of described I/O interface by one the 4th inverter G7, described first P-type crystal pipe P1 and described 3rd P-type crystal pipe P3 is made to have identical control signal, and the switch situation of described first P-type crystal pipe P1 and described 3rd P-type crystal pipe P3 keeps synchronous substantially with the input signal of described I/O interface.Further, described 6th node M is connected with the output of described 4th inverter G7, and the input of described 4th inverter G7 is connected with the input 107 of described I/O interface.

The drain electrode of described second P-type crystal pipe P2 is connected with the output 108 of described I/O interface, the grid of described second P-type crystal pipe P2 and the output of one the 3rd inverter G6, the input of described 3rd inverter G6 is connected with the output of one second NAND gate G5 by one second time delay circuit 102, and the input 107 of described I/O interface is connected with two inputs of described second NAND gate G5 respectively with output.That is, the output signal of described I/O interface feeds back to the input of described second NAND gate G5, with the input signal of described I/O interface jointly after described second NAND gate G5, then as the control signal of described second N-type transistor N2 after described second time delay circuit 102.

The grid of described 3rd P-type crystal pipe P3 and the grid of the first P-type crystal pipe P1 are connected to one the 6th node M, described 6th node M is connected with the input 107 of described I/O interface by described 4th inverter G7, and the control signal of described 3rd P-type crystal pipe P3 and described first P-type crystal pipe P1 is synchronous.Described 3rd P-type crystal pipe P3 and described 4th P-type crystal pipe P4 connects, concrete, the substrate of described 3rd P-type crystal pipe P3 and the substrate of described 4th P-type crystal pipe P4 are connected to one the 7th node S, the source electrode of described 3rd P-type crystal pipe P3 is connected with described 7th node S, the drain electrode of described 3rd P-type crystal pipe P3 is connected with the source electrode of described 4th P-type crystal pipe P4, described 7th node S and described 5th node L is connected to one the 8th node U, described 8th node U is by one second resistance R2 ground connection, the overshoot that the output voltage that described second resistance R2 reduces described I/O interface produces in the switching process from low level to high level.

The drain electrode of described 4th P-type crystal pipe P4 is connected with the output 108 of described I/O interface, the grid of described 4th P-type crystal pipe P4 is connected with the output of one second NOR gate G8, and the output of described second NOR gate G8 is connected with two inputs of described second NOR gate G8 respectively with described 8th node U

That is, large-sized described first P-type crystal pipe P1 and described second P-type crystal pipe P2 is composed in series the first order output driving circuit of a P-type crystal pipe, undersized described 3rd P-type crystal pipe P3 and described 4th P-type crystal pipe P4 is composed in series the second level output driving circuit of a P-type crystal pipe, two cover sizes are different and cause the P-type crystal pipe output driving circuit that the P-type crystal pipe of the driving force series connection of difference is to some extent formed, the described first P-type crystal pipe P1 of large driving force and described second P-type crystal pipe P2 is utilized to achieve the high-speed turnover of level, and pass through the grid of the signal feedback of described I/O interface output to described second P-type crystal pipe P2 and described 4th P-type crystal pipe P4, as the control signal of described second P-type crystal pipe P2 and described 4th P-type crystal pipe P4, thus achieve the initial stage of output level in upset from low level to high level of described I/O interface, the fast conducting of described P-type crystal pipe output driving circuit is with closed, and described output level is in the smoothing overturning signal in latter stage from low level to high level.

Further, described 3rd inverter G6 and described 4th inverter G7 can improve the driving force of described P-type crystal pipe output driving circuit, prevents the switch time delay of described first P-type crystal pipe P1 and described second P-type crystal pipe P2 long.

Concrete operation principle is as follows:

When the input signal of described I/O interface is all stabilized in high level with output signal, the operating state of its output depends on the running of described N-type transistor output driving circuit.Now, described second N-type transistor N2 and described 4th N-type transistor N4 is in conducting state all the time.When the input signal of described I/O interface is converted to low level by high level, described first N-type transistor N1 and described 3rd N-type transistor N3 opens, and all hold conducting with ground, make the fast conducting of N-type transistor output driving circuit described in the output level upset initial stage of described I/O interface, power on, thus make described I/O interface output level can at a high speed to low transition.

Because the output signal of described I/O interface to have the delay of any relative to its input signal, within the input signal of described I/O interface to be converted to low level initial stage one end period by high level, the output signal of described I/O interface still remains high level, namely two input signals of described first NOR gate G1 are made to be respectively a high level and a low level, the output signal of described first NOR gate G1 is caused still to be low level, the induction shake that can hold with eliminating, makes described 4th N-type transistor N4 keep stable.

Meanwhile, along with the decline of the output level of described I/O interface, the output signal of described first NOR gate G1 will lower than the threshold voltage of described second N-type transistor N2 after described first inverter G2 is anti-phase, but due to the setting of described first time delay circuit 101, described second N-type transistor N2 will keep the conducting state of a period of time, thus continues to drive the output level of described I/O interface to change to low level.After the output voltage of described I/O interface continues the decline regular hour, the output voltage of described first inverter G2 is by the threshold voltage lower than described second N-type transistor N2, therefore described second N-type transistor N2 closes, the series connection of described first N-type transistor N1 and described second N-type transistor N2 stops the impact on the output signal of described I/O interface, the driving force of described N-type transistor output driving circuit declines, the continuation change of the output level of described I/O interface will only be subject to the impact of the series connection of described 3rd N-type transistor N3 and described 4th N-type transistor N4.Breadth length ratio due to described 3rd N-type transistor N3 and described 4th N-type transistor N4 is less than the breadth length ratio of described first N-type transistor N1 and described second N-type transistor N2, the driving force of series connection to the output level of described I/O interface of described 3rd N-type transistor N3 and described 4th N-type transistor N4 is less than the series connection of described first N-type transistor N1 and described second N-type transistor N2, the conversion speed of the output level of described I/O interface is slowed down, thus achieve the automatic control being realized noise by the feedback of the output signal of described I/O interface, avoid the phenomenon of the output voltage change overshoot of described I/O interface, and make the output signal of described I/O interface overturn the waveform smoothing of latter stage from high level to low level, as shown in Figure 3, 105 is input waveform, 106 is output waveform.

When the input signal of described I/O interface is all stabilized in low level with output signal, the operating state of the output 108 of described I/O interface depends on the running of described P-type crystal pipe output driving circuit.Now, described second P-type crystal pipe P2 and described 4th P-type crystal pipe P4 is in conducting state all the time.When the input signal of described I/O interface is high level by low transition, described first P-type crystal pipe P1 and described 3rd P-type crystal pipe P3 opens immediately, and with power end conducting, make the fast conducting of P-type crystal pipe output driving circuit described in the upset initial stage of the output level at described I/O interface from low level to high level, power on, thus the output level of described I/O interface can be changed to high level at a high speed.

Because the output signal of described I/O interface to have the delay of any relative to its input signal, within one end period that the input signal of described I/O interface by low transition is the high level initial stage, the output signal of described I/O interface is still low level, namely, two input signals of described second NAND gate G5 are made to be respectively a high level and a low level, the output signal of described second NAND gate G5 is caused still to be high level, thus can eliminate the induction shake of power end, and it is stable that described 4th P-type crystal pipe P4 is ensured.

Meanwhile, along with the rising of the output voltage of described I/O interface, the output signal of described second NAND gate G5 will higher than the threshold voltage of described second P-type crystal pipe P2 after described 3rd inverter G6 is anti-phase, but due to the setting of described second time delay circuit 102, described second P-type crystal pipe P2 will maintain the conductive state of a period of time, thus continues to drive the output level of described I/O interface to change to high level.After the output voltage of described I/O interface continues the rising regular hour, the output voltage of described 3rd inverter G6 is by the threshold voltage higher than described second P-type crystal pipe P2, therefore, described second P-type crystal pipe P2 closes, the series connection of described first P-type crystal pipe P1 and described second P-type crystal pipe P2 stops the impact on the output signal of described I/O interface, and the driving force of described P-type crystal pipe output driving circuit declines.The continuation change of the output level of described I/O interface will only be subject to the impact of the series connection of described 3rd P-type crystal pipe P3 and described 4th P-type crystal pipe P4.Breadth length ratio due to described 3rd P-type crystal pipe P3 and described 4th P-type crystal pipe P4 is less than the breadth length ratio of described first P-type crystal pipe P1 and described second P-type crystal pipe P2, the driving force of series connection to the output level of described I/O interface of described 3rd P-type crystal pipe P3 and described 4th P-type crystal pipe P4 is less than the series connection of described first P-type crystal pipe P1 and described second P-type crystal pipe P2, the conversion speed of the output level of described I/O interface is slowed down, thus achieve the automatic control being realized noise by the feedback of the output signal of described I/O interface, avoid the phenomenon of the output voltage change overshoot of described I/O interface, and make waveform smoothing in the upset latter stage from low level to high level of the output signal of described I/O interface, as shown in Figure 3, 105 is input waveform, 106 is output waveform.

To sum up, in the I/O interface driving circuit of the automatic control noises provided in the embodiment of the present invention, the control to N-type transistor output driving circuit and P-type crystal tube drive circuit will be realized after the output signal of described I/O interface and input signal combination, simultaneously, utilize the level shake that combinations thereof signal elimination power end and ground end induce when the output signal upset of described I/O interface, and utilize described first time delay circuit to adjust the driving force of described N-type transistor output driving circuit, utilize described second time delay circuit to adjust the driving force of described P-type crystal tube drive circuit, to prevent the output signal voltage overshoot of described I/O interface, the output signal realizing described I/O interface overturns the smoothing in latter stage, improve the noise inhibiting ability of described I/O interface circuit.

Above are only the preferred embodiments of the present invention, any restriction is not played to the present invention.Any person of ordinary skill in the field; in the scope not departing from technical scheme of the present invention; the technical scheme disclose the present invention and technology contents make the variations such as any type of equivalent replacement or amendment; all belong to the content not departing from technical scheme of the present invention, still belong within protection scope of the present invention.

Claims (11)

1. an I/O interface driving circuit for automatic control noises, is characterized in that, comprising:
N-type transistor output driving circuit and P-type crystal tube drive circuit, described N-type transistor output driving circuit is all connected with the output of I/O interface with described P-type crystal tube drive circuit;
Described N-type transistor output driving circuit comprises: the first N-type transistor, the second N-type transistor, the 3rd N-type transistor and the 4th N-type transistor;
The grid of described first N-type transistor is connected with the input of I/O interface, and the substrate of described first N-type transistor and the substrate of described second N-type transistor are connected to a first node, and the source electrode of described first N-type transistor is connected with described first node;
The source electrode of described second N-type transistor is connected with the drain electrode of described first N-type transistor, the drain electrode of described second N-type transistor is connected with the output of described I/O interface, the grid of described second N-type transistor is connected with the output of one first NOR gate by one first time delay circuit, and the input of described I/O interface is connected with two inputs of described first NOR gate respectively with output;
The described grid of the 3rd N-type transistor and the grid of the first N-type transistor are connected to a Section Point, described Section Point is connected with the input of described I/O interface, the substrate of described 3rd N-type transistor and the substrate of described 4th N-type transistor are connected to one the 3rd node, the source electrode of described 3rd N-type transistor is connected with described 3rd node, described 3rd node and described first node are connected to one the 4th node, described 4th node ground connection;
The source electrode of described 4th N-type transistor is connected with the drain electrode of described 3rd N-type transistor, the drain electrode of described 4th N-type transistor is connected with the output of described I/O interface, the grid of described 4th N-type transistor is connected with the output of one first NAND gate, and the output of described first NOR gate is connected with two inputs of described first NAND gate respectively with described 4th node;
Described P-type crystal tube drive circuit comprises: the first P-type crystal pipe, the second P-type crystal pipe, the 3rd P-type crystal pipe and the 4th P-type crystal pipe;
The grid of described first P-type crystal pipe is connected with the input of described I/O interface, and the substrate of described first P-type crystal pipe and the substrate of described second P-type crystal pipe are connected to one the 5th node, and the source electrode of described first P-type crystal pipe is connected with described 5th node;
The source electrode of described second P-type crystal pipe is connected with the drain electrode of described first P-type crystal pipe, the drain electrode of described second P-type crystal pipe is connected with the drain electrode of described second N-type transistor, and be connected with the output of described I/O interface, the grid of described second P-type crystal pipe is connected with the output of one second NAND gate by one second time delay circuit, and the input of described I/O interface is connected with two inputs of described second NAND gate respectively with output;
Grid and the described first P-type crystal pipe of described 3rd P-type crystal pipe are connected to one the 6th node, described 6th node is connected with the input of described I/O interface, the substrate of described 3rd P-type crystal pipe and the substrate of described 4th P-type crystal pipe are connected to one the 7th node, the source electrode of described 3rd P-type crystal pipe is connected with described 7th node, described 7th node and described 5th node are connected to one the 8th node, described 8th node ground connection;
The source electrode of described 4th P-type crystal pipe is connected with the drain electrode of described 3rd P-type crystal pipe, the drain electrode of described 4th P-type crystal pipe is connected with the drain electrode of described 4th N-type transistor, and be connected with the output of described I/O interface, the grid of described 4th P-type crystal pipe is connected with the output of one second NOR gate, and the output of described second NAND gate is connected with two inputs of described second NOR gate respectively with described 8th node.
2. the I/O interface driving circuit of control noises automatically as claimed in claim 1, it is characterized in that, the I/O interface driving circuit of described automatic control noises also comprises one first inverter, the output of described first NOR gate is connected with the input of described first inverter after described first time delay circuit, and the output of described first inverter is connected with the grid of described second N-type transistor.
3. the I/O interface driving circuit of control noises automatically as claimed in claim 2, it is characterized in that, the I/O interface driving circuit of described automatic control noises also comprises one second inverter, the input of described I/O interface is connected with the input of described second inverter, and the output of described second inverter is connected with described Section Point.
4. the I/O interface driving circuit of control noises automatically as claimed in claim 3, it is characterized in that, the I/O interface driving circuit of described automatic control noises also comprises one the 3rd inverter, the output of described second NAND gate is connected with the input of described 3rd inverter after described second time delay circuit, and the output of described 3rd inverter is connected with the grid of described second P-type crystal pipe.
5. the I/O interface driving circuit of control noises automatically as claimed in claim 4, it is characterized in that, the I/O interface driving circuit of described automatic control noises also comprises one the 4th inverter, the input of described I/O interface is connected with the input of described 4th inverter, and the output of described 4th inverter is connected with described 6th node.
6. the I/O interface driving circuit of control noises automatically as claimed in claim 1, it is characterized in that, the breadth length ratio of described first N-type transistor and described second N-type transistor is greater than the breadth length ratio of described 3rd N-type transistor and described 4th N-type transistor.
7. the I/O interface driving circuit of control noises automatically as claimed in claim 6, it is characterized in that, the breadth length ratio of described first N-type transistor is equal with the breadth length ratio of described second N-type transistor, and the breadth length ratio of described 3rd N-type transistor is equal with the breadth length ratio of described 4th N-type transistor.
8. the I/O interface driving circuit of control noises automatically as claimed in claim 1, it is characterized in that, the breadth length ratio of described first P-type crystal pipe and described second P-type crystal pipe is greater than the breadth length ratio of described 3rd P-type crystal pipe and described 4th P-type crystal pipe.
9. the I/O interface driving circuit of control noises automatically as claimed in claim 8, it is characterized in that, the breadth length ratio of described first P-type crystal pipe is equal with the breadth length ratio of described second P-type crystal pipe, and the breadth length ratio of described 3rd P-type crystal pipe is equal with the breadth length ratio of described 4th P-type crystal pipe.
10. the I/O interface driving circuit of control noises automatically as claimed in claim 1, it is characterized in that, the I/O interface driving circuit of described automatic control noises also comprises one first resistance, and described 4th node is by described first grounding through resistance.
The I/O interface driving circuit of 11. control noises automatically as claimed in claim 1, it is characterized in that, the I/O interface driving circuit of described automatic control noises also comprises one second resistance, and described 8th node is by described second grounding through resistance.
CN201510290280.9A 2015-05-31 2015-05-31 I/O interface driving circuit capable of automatically controlling noise CN105024682A (en)

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CN106505988A (en) * 2016-11-10 2017-03-15 中国电子科技集团公司第四十七研究所 Configurable I based on FPGA/O voltage holding circuits
CN110677021A (en) * 2019-09-23 2020-01-10 北京时代民芯科技有限公司 Output drive circuit of anti ground bounce noise

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CN102739214A (en) * 2012-06-19 2012-10-17 中国兵器工业集团第二一四研究所苏州研发中心 Self-adaptive noise suppression driver circuit
CN202978714U (en) * 2012-12-06 2013-06-05 雅达电子国际有限公司 MOS FET grid drive circuit and switch power supply
CN103226981A (en) * 2013-04-10 2013-07-31 京东方科技集团股份有限公司 Shift register unit and gate driving circuit

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US6127861A (en) * 1997-04-30 2000-10-03 Samsung Electronics, Co., Ltd. Duty cycle adaptive data output buffer
CN1741383A (en) * 2005-09-01 2006-03-01 上海交通大学 Adaptive noise suppressed I/O unit drive circuit
CN102739214A (en) * 2012-06-19 2012-10-17 中国兵器工业集团第二一四研究所苏州研发中心 Self-adaptive noise suppression driver circuit
CN202978714U (en) * 2012-12-06 2013-06-05 雅达电子国际有限公司 MOS FET grid drive circuit and switch power supply
CN103226981A (en) * 2013-04-10 2013-07-31 京东方科技集团股份有限公司 Shift register unit and gate driving circuit

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Publication number Priority date Publication date Assignee Title
CN106505988A (en) * 2016-11-10 2017-03-15 中国电子科技集团公司第四十七研究所 Configurable I based on FPGA/O voltage holding circuits
CN106505988B (en) * 2016-11-10 2019-06-04 中国电子科技集团公司第四十七研究所 Configurable I based on FPGA/O voltage holding circuit
CN110677021A (en) * 2019-09-23 2020-01-10 北京时代民芯科技有限公司 Output drive circuit of anti ground bounce noise

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