CN113495816B

CN113495816B - Burn-in testing and adjusting circuit, chip and method

Info

Publication number: CN113495816B
Application number: CN202010192965.0A
Authority: CN
Inventors: 刘剑锋; 许如柏
Original assignee: Huimang Microelectronics Shenzhen Co ltd
Current assignee: Huimang Microelectronics Shenzhen Co ltd
Priority date: 2020-03-18
Filing date: 2020-03-18
Publication date: 2023-07-25
Anticipated expiration: 2040-03-18
Also published as: CN113495816A

Abstract

The invention discloses a burning test and adjustment circuit, which comprises a counter, a burning adjustment pulse generation circuit, a burning adjustment data latch circuit, a burning adjustment data coding circuit, a selection circuit and at least one group of burning adjustment circuits, wherein the burning test and adjustment mode used by the invention does not need a special process, and the counting scanning mode of the invention realizes a self-detection function and improves the parameter detection precision by burning adjustment of a packaging sheet on the basis of parameter offset caused by wire bonding and plastic packaging because the packaging sheet already counts the parameter offset; furthermore, the burning detection and power-on locking circuit can realize extremely low power consumption, and the special processing burning circuit can ensure that the chip has higher reliability.

Description

Burn-in testing and adjusting circuit, chip and method

Technical Field

The present invention relates to the field of chip burn-in, and in particular, to a burn-in testing circuit, a chip and a method.

Background

The conventional parameter tuning modes are basically divided into a middle test tuning (wafer level) and a final test tuning (chip level).

The middle burning adjustment is divided into the following two methods:

1) Burning and adjusting pure PAD: the method is simple, does not need a burning data detection circuit, but needs to increase the number of burning PADs;

2) PAD burns and transfers and burns and transfer data detection circuitry: although the number of PADs is reduced, the method requires an additional detection circuit, and the detection circuit can bring about certain power consumption.

The conventional middle test burn-out adjustment can cause the difference between a parameter measured value and an actual value due to the needle insertion force of a test needle card and the parameter test environment of a tester, and if the burn-out adjustment is performed according to an abnormal measured value, irreversible deviation of the parameter can be caused, and finally the chip precision is poor. Meanwhile, the wafer is formed into the packaging sheet through wire bonding and plastic packaging, so that parameters are scattered, and finally the precision of the chip is poor.

The firing test adjustment is divided into the following two methods:

1) OTP burning adjustment: the method is realized through a disposable non-erasable circuit, and the method needs a special process, and has higher requirements on the design capability of a chip design company, and higher cost is required for self design or purchasing IP;

2) Memory burning: the method is realized by writing an erasable memory circuit, and the method also needs special process, and has higher requirements on the design capability of a chip design company, and higher cost is required for self-design or purchasing IP.

Disclosure of Invention

The invention aims to solve the technical problem of providing a burn-in testing circuit, a burn-in testing chip and a burn-in testing method aiming at the defects in the prior art.

The technical scheme adopted for solving the technical problems is as follows: the programming test programming circuit comprises a counter, a programming pulse generating circuit, a programming data latch circuit, a programming data coding circuit, a selection circuit and at least one group of programming circuits, wherein:

each chip parameter corresponds to one group of burning circuits, each group of burning circuits comprises a plurality of burning circuits, and each burning circuit corresponds to one burning position of the parameter;

the counter and the programming pulse generating circuit are used for outputting a group of counting signals which are scanned sequentially to the parameter detecting circuit and the programming data latching circuit when receiving an effective group of programming enabling signals, and outputting a group of programming pulse signals to the selecting circuit, wherein: the parameter detection circuit can compare and detect the current parameter to be detected by utilizing the counting signals which are scanned sequentially and output detection signals when the corresponding parameter value is detected;

The programming data latch circuit is used for latching a current group of counting signals when receiving the detection signals and sending the latched counting signals to the programming data coding circuit;

the burning data coding circuit is used for outputting burning coding signals after coding the latched counting signals based on the coding table, wherein: the counting signals with each length correspond to one code table, and the burning bits of the burning code signals corresponding to the counting signals which are closer to the center point in the same code table are smaller;

and the selection circuit is used for selecting a specific burning circuit in the group of burning circuits corresponding to the current parameters to be detected to execute burning according to the received effective group of burning enabling signals, the burning encoding signals and the group of burning pulse signals.

Preferably, the burn-in test adjustment circuit further comprises:

and each burning detection and power-on locking circuit corresponds to one burning detection and power-on locking circuit, and the burning detection and power-on locking circuits are used for starting a burning detection function to detect whether corresponding burning bits are burned or not when power-on reset signals are received, latching the burning detection signals after detection is completed, and closing the burning detection function after latching is completed.

Preferably, the burn-in test adjustment circuit further comprises:

and the burning data decoding circuit is connected with the counter, the burning pulse generating circuit, the burning detection and power-on locking circuit and the parameter detection circuit and is used for directly sending the counting signal to the parameter detection circuit to carry out parameter detection when each parameter starts burning, and reversely decoding the latched burning detection signal according to the coding table after each parameter finishes burning and outputting the signal to the parameter detection circuit.

Preferably, the burning circuit is a MOS switch burning circuit, which comprises a fuse, a burning switch, a protection device and an electrostatic discharge circuit;

the burning switch, the protection device and the fuse are connected in series together to form a burning branch connected between the voltage node and the ground, the static electricity discharge circuit is connected in parallel with the burning branch, and the protection device is a component capable of increasing the conduction voltage drop of the burning branch and ensuring that the conduction voltage drop of the burning branch is larger than that of the static electricity discharge circuit.

Preferably, the burning detection and power-on locking circuit comprises a bias current branch, a first current branch, a second current branch, a latch and two delay circuits;

The bias current branch comprises a detection control switch and a main switch tube which are connected in series between a bias current source and the ground, the first current branch comprises a first upper switch tube and a first lower switch tube which are connected in series between the voltage node and the ground, the second current branch comprises a second upper switch tube and a second lower switch tube which are connected in series between one end, far away from the voltage node, of the fuse, and the first lower switch tube and the second lower switch tube respectively form a current mirror with the main switch tube, and the second upper switch tube and the first upper switch tube form a current mirror;

the data input end of the latch is connected between the second upper switching tube and the second lower switching tube to acquire the burning detection signal, the input of one delay circuit is connected with the power-on reset signal, the output of the delay circuit is connected with the enabling end of the latch and the input of the other delay circuit, and the output of the other delay circuit is connected to the control end of the detection control switch.

In another aspect, the invention also constructs a burn-in testing chip, which comprises the circuit as described in any one of the preceding claims, and the chip comprises the following ports:

the clock signal input end is used for accessing a reference clock signal so that the counter and the burning pulse generating circuit generate the group of counting signals and the group of burning pulse signals;

The burning enabling end is used for accessing the group of burning enabling signals;

the self-detection latch signal input end is used for accessing the detection signal;

the power-on reset signal input end is used for accessing a power-on reset signal;

and the output end is used for outputting the counting signal or the burning detection signal.

The invention also constructs a burning test and adjustment method, which comprises the following steps:

when receiving a valid set of burning enabling signals, the counter and burning pulse generating circuit outputs a set of counting signals and a set of burning pulse signals which are scanned sequentially;

the parameter detection circuit compares and detects the current parameter to be detected by utilizing the counting signals which are scanned in sequence and outputs a detection signal when the corresponding parameter value is detected;

the burning data latch circuit latches a current group of counting signals when receiving the detection signals;

the burning data coding circuit codes the latched counting signal based on the coding table and then outputs a burning coding signal, wherein: the counting signals with each length correspond to one code table, and the burning bits of the burning code signals corresponding to the counting signals which are closer to the center point in the same code table are smaller;

The selection circuit selects a specific burning circuit in a group of burning circuits corresponding to the current parameters to be detected to execute burning according to the received effective group of burning enabling signals, the burning encoding signals and the group of burning pulse signals.

Preferably, the method further comprises:

the burn-in detection and power-on locking circuit starts a burn-in detection function when receiving a power-on reset signal to detect whether corresponding burn-in bits are burned or not, latches the burn-in detection signal after detection is finished, and closes the burn-in detection function after latching is finished;

and the burning data decoding circuit directly transmits the counting signal to the parameter detecting circuit to detect the parameters when each parameter starts burning, and reversely decodes the latched burning detecting signal according to the encoding table after each parameter finishes burning and outputs the signal to the parameter detecting circuit.

The burn-in testing and adjusting circuit, the chip and the method have the following beneficial effects: the burning and adjusting method for the packaging sheet does not need a special process, the burning and adjusting method for the packaging sheet is used during the forming, because the packaging sheet already counts parameter deviation caused by wire bonding and plastic packaging, the parameter burning and adjusting can be realized with higher and more accurate precision on the basis, the burning and adjusting circuit is realized in a cheaper way, the burning and adjusting circuit is simple to realize, for example, the burning and adjusting function can be realized only by a common MOS switch tube, and the counting and scanning method of the invention realizes the self-detection function and improves the parameter detection precision; furthermore, the burning detection and power-on locking circuit can realize extremely low power consumption, and the special processing burning circuit can ensure that the chip has higher reliability.

Drawings

For a clearer description of an embodiment of the invention or of a technical solution in the prior art, the drawings that are needed in the description of the embodiment or of the prior art will be briefly described, it being obvious that the drawings in the description below are only embodiments of the invention, and that other drawings can be obtained, without inventive effort, by a person skilled in the art from the drawings provided:

FIG. 1 is a schematic diagram of a burn-in circuit according to a preferred embodiment of the present invention;

FIG. 2 is a waveform diagram of a count signal;

FIG. 3 is a waveform diagram of a burning pulse signal;

FIG. 4 is a schematic diagram of coding and decoding;

FIG. 5 is a schematic diagram of a MOS switching regulator circuit;

FIG. 6 is a schematic diagram of a variation of the burn-in circuit;

FIG. 7 is a schematic diagram of another variation of the burn-in circuit;

FIG. 8 is a schematic diagram of a further variation of the burn-in circuit;

FIG. 9 is a schematic diagram of a burn-in detection and power-on latch circuit;

FIG. 10 is a flow chart of a method for burn-in testing according to a preferred embodiment of the present invention.

Detailed Description

In order that the invention may be readily understood, a more complete description of the invention will be rendered by reference to the appended drawings. Exemplary embodiments of the present invention are illustrated in the accompanying drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete. It should be understood that the embodiments of the present invention and the specific features in the embodiments are detailed descriptions of the technical solutions of the present application, and not limited to the technical solutions of the present application, and the embodiments of the present invention and the technical features in the embodiments may be combined with each other without conflict.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. It should be noted that "connected" or "connected" as used herein includes not only directly connecting two entities but also indirectly connecting through other entities having beneficial improvements.

The terms including ordinal numbers such as "first", "second", and the like used in the present specification may be used to describe various constituent elements, but these constituent elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, a first component may be termed a second component, and, similarly, a second component may be termed a first component, without departing from the scope of the present invention.

Referring to fig. 1, in a preferred embodiment of the present invention, the test programming circuit includes a counter and programming pulse generating circuit 1, a programming data latch circuit 2, a programming data encoding circuit 3, a selecting circuit 4, at least one set of programming circuits 5, at least one set of programming detection and power-on latch circuit 6, and a programming data decoding circuit 7.

Before describing the functions of the above circuits, the input and output of the whole burn-in circuit will be described first.

Four inputs of the whole burn-in testing and adjusting circuit are provided:

1) A set of burning enable signals TM ₀ ～TM _x The value of the signal subscript x corresponds to the parameter items that the chip actually needs to be burned, for example, x=0, 1 parameter item representing that the chip needs to be burned, x=4, 5 parameter items representing that the chip needs to be burned, and so on.

Since the chip usually has multiple parameters to be trimmed, and each parameter cannot be designed separately for cost saving, but requires a common circuit, which requires distinguishing signals, TM ₀ Corresponding parameter 0, TM _x Corresponding to parameter X. The circuit of the present invention can only allow TM when in operation ₀ ～TM _x One of the signals being high (logic 1) and the other signals being low (logic 0), e.g. TM ₀ At 1, TM ₁ ～TM _x It must be 0, the circuit only trims to parameter 0, which is only the enable signal for parameter 0.

2) Detection signal LA ₀ ～LA _x The signal is from an external parameter detection circuit.

3) The reference clock signal Fosc, which is provided by the clock generated by the OSC module of the chip via the frequency dividing circuit, mainly generates timing for the count signal and the burst signal.

4) The power-on reset signal FUSE_Latch.

The whole burn-in circuit outputs only the multiplexed output signal M in FIG. 1 ₀ ～M _x Each output signal M is actually a signal group, which is a self-detection scanning signal (i.e., a count signal to be mentioned later) during burning, and which is a burning detection signal after burning. M is M ₀ ～M _x And TM ₀ ～TM _x Is one-to-one corresponding to when TM ₀ At a high level, M is output ₀ ，M ₀ Specifically a _y …a ₀ Y represents the number of bits burned for the first parameter, e.g. M if the first parameter is 4 bits burned ₀ The output signal group is a ₃ a ₂ a ₁ a ₀ . When TM ₄ At a high level, M is output ₄ And so on.

The function and implementation of each circuit is described in detail below.

1) A counter and a burning pulse generating circuit 1;

the counter and programming pulse generating circuit 1 is configured to generate a programming enable signal TM after receiving a valid set of programming enable signals ₀ ～TM _x Outputting a set of counting signals D for sequential scanning _y ～D ₀ To the parameter detection circuit and the programming data latch circuit 2, and outputs a set of programming pulse signals FP _y ～FP ₀ To the selection circuit 4.

When any TM is active, it can be used as an enabling signal to start a counter, the counter scans sequentially, D _y ～D ₀ I.e. the count signal from all 0 to all 1 generated by the counter. Identical FP _y ～FP ₀ As a burning pulse signal, any TM is active.

The number of counted bits is related to the maximum number of bits burned for the parameter to be trimmed, for example, there are 4 parameters to be trimmed, i.e., x takes 4, 3 bits burned for the 1 st parameter, 2 bits burned for the 2 nd parameter, 4 bits burned for the 3 rd parameter, 6 bits burned for the 4 th parameter, and the number of counted bits is 6 in total. However, the maximum count signal actually output by each parameter is determined according to the burning bits of the parameter, that is, the value of y is determined by the number of burning bits of the parameter, and the value of y is the number of burning bits of the parameter minus one. D of sequential scanning _y ～D ₀ Reference can be made to fig. 2, which shows in particular a count signal D of the 1 st parameter, starting from all 0 and progressing to all 1 _y ～D ₀ Count signal D of the 2 nd parameter from 000 to 111 _y ～D ₀ Count signal D of the 3 rd parameter from 00 to 11 _y ～D ₀ Count signal D of parameter 4 from 0000 to 1111 _y ～D ₀ From 000000 ～ 111111.

Wherein the count signal D _y ～D ₀ The parameters are directly sent to the parameter detection circuit for parameter detection by the burning data decoding circuit 7, for example, assuming that the chip parameters are 4, namely, x is taken to be 4, if the current parameters to be detected are 1 st parameter, TM ₀ ～TM _x In particular 1000, i.e. TM ₀ Enabling, the programming data decoding circuit 7 outputs M ₀ I.e. a _y …a ₀ ，a _y …a ₀ The value of (1) is actually D which is output by the counter and the burning pulse generating circuit _y ～D ₀ Is a value of (2). For a specific principle of the burning data decoding circuit 7 reference is made to the following section.

Wherein the parameter detection circuit can utilize the count signal D of sequential scanning _y ～D ₀ Comparing and detecting the current parameter to be detected and outputting a detection signal LA when the corresponding parameter value is detected ₀ ～LA _x . Specifically, the parameter detection circuit receives the real-time signal D _y ～D ₀ Will then send real-time signal D _y ～D ₀ Comparing with the parameter value of the current parameter to be detected, if the comparison is consistent, the output signal of the detection circuit will turn over, and the turned-over output signal is the detection signal LA of the invention ₀ ～LA _x 。

Referring to fig. 3, the set of burst pulse signals includes a plurality of burst pulses, and a delay is disposed between two adjacent pulses. As shown in the figure, T1 represents the time width of each burst, and T2 represents the time width of the delay.

2) Burn-in data latch circuit 2:

the programming data latch circuit 2 is configured to receive a valid set of programming enable signals TM ₀ ～TM _x Receiving the detection signal LA ₀ ～LA _x When latching the current set of counting signals D _y ～D ₀ It is temporarily written as a latch signal e _y ...e ₀ And latch the signal e _y ...e ₀ To the burning data encoding circuit 3.

3) Burning data encoding circuit 3:

the burning data encoding circuit 3 is used for encoding the signal e based on the encoding table _y ...e ₀ After coding, outputting a burning code signal f _y ...f ₀ . Burn-in enable signal TM ₀ ～TM _x Can select a specific group of burning patternsCircuit 5, burning the coded signal f _y ...f ₀ The burning bit information for which burning is to be performed is reflected, according to which a specific burning circuit 5 can be selected from the selected set of burning circuits 5 to perform burning. For example, f ₀ A 1 means that the burn-in circuit 50 needs to perform burn-in, f _y A 1 means that the burning circuit 5y needs to perform burning, and so on. Each length of the count signal (the length of the count signal is equal to the value of y plus one) corresponds to one code table, in other words, different code tables corresponding to different numbers of burning bits. The signal e being closer to the center point in the same coding table _y ...e ₀ Corresponding burning code signal f _y ...f ₀ The fewer the burn-in bits.

Because the requirements of different parameters on the precision are different, theoretically, the higher the precision requirement is, the more the range of the burning adjustment is, the more the number of burning adjustment bits is required, and generally, the number of the total burning adjustment bits of the parameters is more than or equal to 2 bits. The total number of bits burned in the parameter is determined during circuit design, but the number of bits burned in the chip parameter (the number of bits burned in the parameter to be burned) is not constant, for example, if the test finds that the parameter is within the required precision range, the number of bits burned is 0, the number of bits burned depends on the actual tested parameter value and the difference required for meeting the precision, and the number of bits burned is less than or equal to the total number of bits burned in the parameter.

When the packaged chips are subjected to parameter test, the parameter values tested by a large number of chips are actually in normal distribution for the same parameter, so that the number of the chips which are closer to the central point should be reduced as much as possible in order to improve the burning yield. Taking 4 parameters of burning bits as an example, D _y ～D ₀ From 0000 to 1111, the central value is 0111, and the signals of + -1 counts of the central value are 0110 and 1000 respectively. Then the parameter detection circuit provides the detection signal LA when the counter is scanned to 0111 ₀ ～LA _x The programming data latch circuit 2 latches the count signal at this time, and the latched count signal e ₃ ...e ₀ Namely is0111, the parameter is at the central value, if the signal 0111 latched at this time is directly output to the burning circuit 5, the circuit design is judged to be burning by '1'; then if the parameter test is at the center value, the burn-in operation of three burn-in bits needs to be performed; however, the fuse is burned and adjusted to have the problem of yield; it is therefore preferable from a circuit design perspective to not burn the fuses when the parametric test is at a central value.

In order to solve the problem of the burn-in yield, the invention realizes that the number of chip burn-in is smaller when the chip is closer to the center point by encoding the latched counting signal. The 1 is used as a burning effective value, the central value 0111 is coded into 0000 through the processing of the coding circuit 3, so that the central value is not burned, the counting signals of the bits of the central value 0111 plus or minus 1 are 0110 and 1000, if the central value is not coded, 2 fuses need to be burned out by the 0110, and 1 fuse needs to be burned out by the 1000, so that the 1000 can meet the requirement, but the 0110 needs to be coded, and the 0110 is also burned out by only 1 fuse. The number of the chip burning adjustment which is closer to the center point is ensured to be smaller by a similar coding mode, so that the purpose of improving the burning adjustment yield is achieved. The different numbers of burned bits are converted in a similar manner.

Referring to fig. 4, one of the coding modes of 4 padding bits is presented, and it should be noted that the coding modes for implementing this function are not limited to the one presented in fig. 4, as long as the purpose is to ensure that the center value does not need padding, and the closer to the center value, the fewer the number of padding bits. In FIG. 4, the left-hand value is the latched count signal e _y ...e ₀ The right-hand value is the encoded modulated coded signal f _y ...f ₀ The burning data encoding circuit 3 can read the latched count signal e _y ...e ₀ Directly find the corresponding value on the left side in fig. 4, and then find the burning code signal f on the right side _y ...f ₀ Coding can be achieved.

4) A burning circuit 5, a selection circuit 4:

note that the circuit of the whole virtual frame part in fig. 1 is for one parameter, and the circuit of the other parameter is omitted in the figure. Each chip parameter corresponds to a set of trimming circuits 5, only one set of trimming circuits 5 being illustrated in fig. 1. Each set of the trimming circuits 5 includes a plurality of trimming circuits 5, and the MOS switch trimming circuits 0 to y shown in fig. 1 are a set of switch trimming circuits 5, and each MOS switch trimming circuit corresponds to one trimming bit of a parameter.

Since the encoding circuits 3 of all parameters can be multiplexed, the selection is made when the parameter tuning is performed. The selection circuit 4 is used for receiving a valid set of burning enable signals TM ₀ ～TM _x The burning code signal f _y ...f ₀ And a set of burning pulse signals FP _y ...FP ₀ And selecting a specific burning circuit 5 in a group of burning circuits 5 corresponding to the current parameters to be detected to execute burning.

For example, when testing parameter 0, TM ₀ Effectively, the programming coding signal and the programming pulse signal of the parameter 0 are subjected to AND operation, and after the operation is finished, the signals pass through TM ₀ The MOS switch burning circuit 0 is selected, and through one-to-one correspondence of the parameter, the TM signal and the MOS switch burning circuit, the false burning can be prevented, and the circuit function can be realized and meanwhile, the circuit can be better simplified.

Each parameter is provided with a plurality of groups of MOS switch burning circuits shown in fig. 5 according to actual requirements. Referring to fig. 5, specifically, the MOS switch trimming circuit includes a FUSE, a trimming switch (such as an NMOS tube MN1 configured with a parasitic diode in the figure), a protection device, and an ESD circuit shown in a dummy frame, where the trimming switch MN1, the protection device, and the FUSE are connected in series together to form a trimming branch connected between a voltage node VP and ground, the ESD circuit is connected in parallel with the trimming branch, and the protection device is a component capable of increasing a conduction voltage drop of the trimming branch and ensuring that the conduction voltage drop of the trimming branch is greater than that of the ESD circuit. As shown in fig. 5, the protection device in this embodiment is specifically an N-type NMOS transistor MN2 configured with a parasitic diode.

The burning in the present invention means that the FUSE in fig. 5 is burned out by applying a current flowing through the FUSE, and by integrating the resistance of the FUSE itself, the FUSE is burned out by heat accumulation. MN1 and MN2 in fig. 5 are used as switching tubes, and the signal FP is 1 and is turned on to realize burning; if the signal FP is 0, the signal is turned off and the burning is not performed. Because of the physical heat dissipation itself, if the heat accumulation is insufficient for a short time, the fusing cannot be realized, so that a sufficient current must be ensured, and therefore, the switching tube must have a sufficient current capability.

Taking the MOS switch burning circuit y as an example, the working principle of the MOS switch burning circuit and the specific principle of the reliability guarantee of burning are as follows: as shown in fig. 5, the pulse signal FP is modulated _y When coming, since MN1 and MN2 are NMOS transistors, MN1 and MN2 are turned on in the pulse active phase, such as the phase T1 indicated in fig. 3, VP has a large current flowing to ground through FUSE, MN1 and MN2, and this current FUSEs FUSE. Ideally the resistance across FUSE is infinite after fusing. Meanwhile, because the chips inevitably accumulate charges during the processes of manufacturing, production, assembly, testing, storage and handling, once a discharge passage exists, the discharge of the charges can generate extremely large current, and the current can damage the chips when flowing through the inside of the chips. To solve this problem, the VP pin in the actual chip will have an ESD as shown by the dashed box in FIG. 5. When VP-GND forward electrostatic discharge occurs, current can be reversely broken down and discharged through the parasitic diode D3 of MN3, and when VP-GND backward electrostatic discharge occurs, current can be positively conducted and discharged through the parasitic diode D3 of MN 3. Because the MOS switch burning circuit in the invention is added with MN2, when VP-GND forward electrostatic discharge occurs, the voltage required by VP discharge through the branch where FUSE is located (namely the burning branch) is the sum of the reverse breakdown voltage of the parasitic diode D1 of MN1 and the forward conduction voltage drop of the parasitic diode D2 of MN2 parasitic diode. Because MN3, MN1 and MN2 are the same devices, the reverse breakdown voltages of D1 and D3 are basically equal, so that a D2 forward conduction voltage drop differential exists between two discharge branches (the branch where FUSE is located and the branch where MN3 is located), and the electrostatic discharge basically only discharges through the D3 reverse breakdown branch and does not flow through the branch where FUSE is located, thereby not causing the electrostatic discharge to flow FUSE is fused by the electrostatic discharge current. When the reverse electrostatic discharge of the haircut VP-GND is carried out, the voltage required by GND through the forward conduction voltage drop of the parasitic diode D1 of the FUSE and the forward conduction voltage drop of the parasitic diode D2 of the MN1 are the sum, and the two discharge branches have the same difference of D2 forward conduction voltage drop, the electrostatic discharge basically only can be carried out through D3 forward conduction discharge, and the electrostatic discharge does not flow through the branch where the FUSE is located, so that the FUSE is not fused by the electrostatic discharge current. The circuit structure ensures that the FUSE of the chip is not fused by mistake in unavoidable electrostatic discharge, and greatly enhances the reliability of chip burning.

Of course, the above is only a specific example, and in practice, only one component can be added to the tuning branch (branch where the FUSE is located) to increase the conduction voltage drop of the tuning branch and ensure that the conduction voltage drop of the tuning branch is greater than the conduction voltage drop of the electrostatic discharge circuit, which is within the protection scope of the present invention, for example, fig. 6-8 are several simple modifications of the present embodiment, for example, compared with fig. 5, in fig. 6, the diode D2 is used instead of MN2, and fig. 7 and 8 are the positions of the FUSE are changed relative to fig. 5 and 6.

6) Burn and transfer detection and power on locking circuit 6:

The burning detection and power-on locking circuits 6 are in one-to-one correspondence with the burning circuits 5, each burning circuit 5 is correspondingly connected with one burning detection and power-on locking circuit 6, and the burning detection and power-on locking circuit 6 is used for starting a burning detection function to detect whether the corresponding burning position is burnt or not when receiving a power-on reset signal FUSE_latch, latching a burning detection signal DET after detection is completed, and closing the burning detection function after latching is completed.

Referring to fig. 9, the burn-in detection and power-on latch circuit 6 includes a bias current branch 60, a first current branch 61, a second current branch 62, a latch 65, and two delay circuits 63, 64.

The bias current branch 60 includes a detection control switch and a main switching tube MN3 connected in series between a bias current source Ibias and ground, the Ibias being provided by a bias module. The first current branch 61 includes a first upper switching tube MP1 and a first lower switching tube MN4 connected in series between the voltage node VP and the ground, the second current branch 62 includes a second upper switching tube MP2 and a second lower switching tube MN5 connected in series between one end of the FUSE far away from the voltage node VP and the ground, both MN4 and MN5 and MN3 form a current mirror, and MP1 and MP2 form a current mirror. MP1 and MP2 are PMOS tubes, MN3, MN4 and MN5 are NMOS tubes, and MN3: MN4: the ratio of MN5 is 1:1:1, mp1: the proportion of MP2 is 1: the larger the n, the greater the current capability. The data input end of the Latch 65 is connected between MP2 and MN5 to obtain the burn-in detection signal DET, the input of the delay circuit 63 is connected to the power-on reset signal fuse_latch, the output is connected to the enable end of the Latch 65 and the input of the delay circuit 64, and the output of the delay circuit 64 is connected to the control end of the detection control switch.

The purpose of the burning detection design is to judge whether the burning bits of each parameter are burned or not, taking 4 burning bits and the coded burning coding signal being 0111 as an example, the 0 th, 1 st and 2 nd bits are burned or not burned according to the burning coding signal; the burn-in detection function is designed for the purpose of determining the state at this time. Because each burning position needs to be detected, and meanwhile, the burning detection needs power consumption, and under the condition that a plurality of parameters are provided and each parameter has a plurality of burning positions, the power consumption of the burning detection cannot be ignored. The detection function must be turned off when necessary in order to achieve low power consumption. According to the invention, the Latch and turn-off functions are added, after the power-on reset signal FUSE_latch arrives, the DET signal at the moment is latched through a period of delay, and then the detection function is turned off through a period of delay, so that the power consumption required by detection is reduced.

Specifically, fuse_latch is a power-on reset signal, and when the power supply voltage rises to a specific voltage V1 during the power-on of the whole circuit, the whole circuit turns over from 0 to 1; the power supply voltage is turned off until a flip from 1 to 0 occurs at a specific voltage V2, and the specific voltage V1 is generally higher than the specific voltage V2. The FUSE_Latch signal is passed through delay circuit 63 to generate a Latch signal, then the Latch signal is turned over by a delay T later than FUSE_Latch, and at the same time the Latch signal is passed through delay circuit 64 to generate a shat signal, then the shat signal is turned over by a delay T later than Latch signal. Therefore, the FUSE_Latch signal firstly resets the Latch and the detection circuit, after a delay T, the Latch signal latches the detected DET signal, and after a delay T, the detection function of the detection circuit is closed by the Sut signal, so that the aim of low power consumption is fulfilled.

The principle of burning detection is as follows: in fig. 9, the FUSE has a small resistance before blowing, which is basically negligible, but the resistance after burning may be a larger resistance or infinite. Since MN3: MN4: the ratio of MN5 is 1:1:1, a step of; the current flowing through MN3 is Ibias; the value of the current flowing through MN4 and through MN5 is also Ibias; since MN4 and MP1 are in the same branch, the current flowing through MP1 is also Ibias; since the current of VP through FUSE, MP2, MN5 is limited to Ibias by MN5, the voltage Vfuse across FUSE (before) =rfuse (before) =ibias, rfuse (before) represents the resistance before FUSE blowing, and since Rfuse (before) is small, it can be approximately considered that the voltage at point b in fig. 9 is equal to VP, then when MP1: mp2=1: n, and n >1, the current capability of MP2 is n×ibias, and since MN5 has Ibias, MP1 has a current pull-up capability greater than MN5, DET has VP, and the logic signal is determined to be "1"; when FUSE is burned, the FUSE resistance increases, so the voltage across FUSE is Vfuse (post) =rfuse (post) =ibias, and Rfuse (post) indicates the resistance after FUSE is burned. At this point, the voltage at point b is VP-Vfuse (post), then the current pull-up capability of MP2 will be smaller than n×ibias, and when the circuit is designed reasonably, once the trimming is performed, the current pull-up capability of MP2 will be smaller than Ibias. Therefore, the pull-down capability of the MN5 is stronger than the pull-up capability of the MP2 after the programming, the DET voltage at this time is GND, and the logic is determined to be "0", so that it can be determined whether to continue the programming according to the above principle.

7) Burn-in data decoding circuit 7:

in order to improve the burn-in yield, the latched count signal is encoded by the encoding circuit 3 to obtain the burn-in encoded signal, and then the burn-in encoded signal is output to the MOS switch circuit through the selecting circuit 4 to perform burn-in, so that the burn-in detection and power-on latch circuit 6 detects that the latched DET signal is consistent with the burn-in encoded signal, but the encoded signal does not conform to the characteristic that the count signal increases gradually from all 0 to all 1, so that the burn-in encoded signal needs to be re-decoded and restored to the count signal when the latch circuit 2 latches, the decoding is the restoration of the encoded signal, and specifically, as shown in fig. four, the decoded signal is finally output to the module where the respective parameter is located.

The two inputs of the burning data decoding circuit 7 are respectively connected with the counter and burning pulse generating circuit 1 and the burning detecting and powering-on locking circuit 6, and the output of the burning data decoding circuit is connected with the parameter detecting circuit. The burning data decoding circuit 7 is configured to send the count signal directly to the parameter detecting circuit for parameter detection when each parameter starts burning, and after each parameter finishes burning, to reversely decode the latched burning detection signal according to the encoding table and output the decoded signal to the parameter detecting circuit, where the reverse decoding process is opposite to encoding, and specific reference can be made to the encoding part, and details are not repeated here. Whether the count signal is forwarded or the decoded signal is generated, the burning data decoding circuit 7 selects a specific output terminal to output according to the valid set of burning enable signals received by the burning data decoding circuit. For example, TM ₀ When 1 is reached, the programming data decoding circuit 7 selectively outputs M ₀ When TM ₄ At a high level, M is selected and outputted by the burning data decoding circuit 7 ₄ And so on.

When a certain parameter is burned, a signal TM corresponding to the parameter is high level, and the burned data decoding circuit 7 plays a role of counting signal forwarding at the moment. After the burn-in is completed, the power is needed to be turned on again to read the burn-in data of the parameter corresponding to the signal TM (i.e. the so-called burn-in detection signal above), and when TM is at a low level, the read burn-in data can be sent to the corresponding circuit: specifically, after the execution of the programming of a parameter is completed, the power-on reset signal fuse_latch is generated by re-powering on, at this time, the signal TM corresponding to the parameter is low level, a group of programming detection and power-on Latch circuits 6 corresponding to the parameter start the programming detection function, after the delay T, the Latch 65 is triggered by the Latch signal to Latch the detected programming data, and after the delay T, the shutdown detection function is triggered by the shutdown signal to reduce the power consumption, because the signal TM at this time is low level, the programming data decoding circuit 7 acts as a decoding function at this time, the programming data decoding circuit 7 performs reverse decoding on the latched programming data according to the coding table as shown in fig. four, and outputs the decoded programming data to the corresponding parameter detection circuit.

The entire operation of the present embodiment is briefly illustrated in the following description in conjunction with the above detailed description: in TM ₀ At high level, bus signal M ₀ Is 4 bits (i.e. a _y ＝a ₃ ) As an example. When TM ₀ When the voltage is high, the counter and the burning pulse generating circuit 1 start to operate to generate D _y ～D ₀ A signal. D (D) _y ～D ₀ The signal is output to the burning data decoding circuit 7 by using TM ₀ The selection signal is directly output to a parameter detection circuit corresponding to the parameter 0. Since this parameter 0 corresponds to only 4 bits of the burn-in bits, only signal D is selected ₃ ～D ₀ . Count signal D ₃ ～D ₀ The counting starts stepwise from 0000 to 1111, and the signal waveform is as shown in fig. 2. When one of the data sets is counted, for example, 0100, if the parameter detection circuit corresponding to the parameter 0 generates a flip signal (i.e., the detection signal LA) from 0 to 1 ₀ ) This signal is input to the programming data latch circuit 2 to trigger its latching of D at this time ₃ ～D ₀ Data, i.e. latch D ₃ ～D ₀ =0100, that is to say the output signal e latched by the trimming data latch circuit 2 ₃ ～e ₀ =0100. Signal e ₃ ～e ₀ As an input signal to the burning data encoding circuit 3, which finds the number e based on the encoding table of fig. 4 ₃ ～e ₀ After being coded, 0100 becomes signal f ₃ ～f ₀ 0011, i.e. modulation code signal f ₃ ～f ₀ 0011, the selection circuit 4 outputs the signal f ₃ ～f ₀ Respectively corresponding to FP ₃ ～FP ₀ Performing AND calculations one by one, i.e. f ₃ Corresponding FP ₃ ，f ₀ Corresponding FP ₀ Analog correspondence. FP (Fabry-Perot) ₃ ～FP ₀ Is a signal of (2)The waveform is shown in FIG. 3 (FP ₃ ～FP ₀ The timing of the design will be later than D ₃ ～D ₀ The time required to count to 1111). Signal f ₃ ～f ₀ Sum signal FP ₃ ～FP ₀ After AND calculation, by using TM ₀ For selecting the signal to be directly output to the group of switching circuits 5 corresponding to the parameter 0, let us assume that the circuit shown in the dashed box part in fig. 1 corresponds to the parameter 0, then y=3, then f ₃ ～f ₀ Sum signal FP ₃ ～FP ₀ The signals after AND calculation are output to MOS switch burning circuits 0-3 in the virtual frame, because f ₃ ～f ₂ =00, when FP ₃ ～FP ₂ The pulse of (2) will not burn up by two bits when coming, i.e. neither of the MOS switch burn-in circuits 2, 3 will perform burn-in. And f ₁ ～f ₀ =11, when FP ₁ ～FP ₀ When the pulse arrives, the lower two bits are burned, i.e. the MOS switch burning circuits 0 and 1 perform burning. According to the schematic diagram shown in FIG. 3, the burning will first follow FP ₀ Starting to burn and regulate step by step, T ₁ To burn and adjust the time of single burning and adjusting position, T ₂ Is the delay between two pulses (avoiding simultaneous firing). After the burn-in is completed, the TM can be read by powering up again ₀ Corresponding to the burning data of parameter 0, and TM ₀ At a low level, the read burn-in data can be sent to the corresponding circuit. Specifically, after the power-on reset signal FUSE_Latch is generated by the power-on again, TM ₀ The burn-in detection and power-on locking circuits 60-y in the virtual frame detect burn-in data first, latch the detected burn-in data through the Latch signal trigger Latch 65 after time delay T, and then the shutdown detection function is triggered by the shutdown signal after time delay T, so that power consumption is reduced. The latched programming data is decoded reversely by the programming data decoding circuit 7 according to the coding table shown in figure four, and is output to the corresponding circuit after the decoding is completed, and the bus M is used at the moment ₀ The data obtained by decoding is a ₃ ～a ₀ ＝0100。

Based on the same inventive concept, the invention also discloses a burn-in testing and adjusting chip, which comprises the circuit as described above, wherein the chip comprises the following ports:

the clock signal input end is used for accessing a reference clock signal so that the counter and burning pulse generating circuit 1 generates the group of counting signals and the group of burning pulse signals;

For more details, reference is made to the embodiment of the above circuit, and details are not repeated here.

Referring to fig. 10, based on the same inventive concept, the invention also discloses a burn-in testing and adjusting method, which can be realized based on the burn-in testing and adjusting circuit or chip of the invention, and comprises the following steps:

s1: when receiving a valid set of programming enabling signals, the counter and programming pulse generating circuit 1 outputs a set of counting signals and a set of programming pulse signals which are scanned sequentially;

s2: the burning data decoding circuit 7 directly sends the counting signal to the parameter detection circuit for parameter detection;

s3: the parameter detection circuit compares and detects the current parameter to be detected by utilizing the counting signals which are scanned in sequence and outputs a detection signal when the corresponding parameter value is detected;

s4: the burning data latch circuit 2 latches a current group of counting signals when receiving the detection signals;

s5: the burning data encoding circuit 3 encodes the latched count signal based on the encoding table and outputs a burning encoded signal, wherein: the counting signals with each length correspond to one code table, and the burning bits of the burning code signals corresponding to the counting signals which are closer to the center point in the same code table are smaller;

s6: the selection circuit 4 selects a specific burning circuit 5 in a group of burning circuits 5 corresponding to the current parameters to be detected to execute burning according to the received effective group of burning enabling signals, the burning encoding signals and the group of burning pulse signals;

S7: the burn-in detection and power-on lock circuit 6 starts the burn-in detection function to detect whether the corresponding burn-in bit is burned or not when receiving the power-on reset signal, latches the burn-in detection signal after the detection is completed, and closes the burn-in detection function after the latching is completed.

S8: and the burning data decoding circuit 7 carries out reverse decoding on the latched burning detection signals according to the coding table after each parameter is burnt and outputs the signals to the parameter detection circuit.

For more details, reference may be made to the above-mentioned circuits and embodiments of the chip, which are not described herein.

In summary, the burn-in testing and adjusting circuit, the chip and the method have the following beneficial effects: the burning and adjusting method for the packaging sheet does not need a special process, the burning and adjusting method for the packaging sheet is used during the forming, because the packaging sheet already counts parameter deviation caused by wire bonding and plastic packaging, the parameter burning and adjusting can be realized with higher and more accurate precision on the basis, the burning and adjusting circuit is realized in a cheaper way, the burning and adjusting circuit is simple to realize, for example, the burning and adjusting function can be realized only by a common MOS switch tube, and the counting and scanning method of the invention realizes the self-detection function and improves the parameter detection precision; furthermore, the burning detection and power-on locking circuit can realize extremely low power consumption, and the special processing burning circuit can ensure that the chip has higher reliability.

The embodiments of the present invention have been described above with reference to the accompanying drawings, but the present invention is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many forms may be made by those having ordinary skill in the art without departing from the spirit of the present invention and the scope of the claims, which are to be protected by the present invention.

Claims

1. The burning test and adjustment circuit is characterized by comprising a counter, a burning adjustment pulse generating circuit, a burning adjustment data latch circuit, a burning adjustment data coding circuit, a selection circuit and at least one group of burning adjustment circuits, wherein:

2. The burn-in circuit of claim 1, further comprising:

3. The burn-in circuit of claim 1, further comprising:

4. The burn-in circuit of claim 2, wherein the burn-in circuit is a MOS switch burn-in circuit comprising a fuse, a burn-in switch, a protection device, and an electrostatic discharge circuit;

5. The burn-in circuit of claim 4, wherein the burn-in switch is a MOS transistor configured with a parasitic diode and the protection device is a diode or a MOS transistor configured with a parasitic diode.

6. The burn-in circuit of claim 4 wherein the burn-in detection and power-on latch circuit comprises a bias current leg, a first current leg, a second current leg, a latch, two delay circuits;

7. A burn-in chip comprising the circuit of any one of claims 1-6.

8. The burn-in chip of claim 7, wherein the chip comprises the following ports:

9. A burn-in testing method, the method comprising:

10. The method according to claim 9, wherein the method further comprises: