CN104280721B - A kind of step delay pulse implementation method based on slide gauge method - Google Patents

Abstract

The present invention provides a kind of step delay pulse implementation method based on slide gauge method, it is compared to speed oblique wave hardware circuit and builds method, hardware circuit is without overhead: speed oblique wave hardware circuit builds method needs extra hardware spending, and slide gauge method utilization FPGA is internally integrated PLL and realizes step delay, it is not necessary to additional hardware circuit overhead；It is compared to speed oblique wave hardware circuit and builds method, and length of delay is adjustable: speed oblique wave hardware circuit builds method, and once circuit is fixed, then length of delay is fixed, and can not adjust length of delay according to demand, and adaptability is poor；The slide gauge method of the present invention, can change length of delay with adjustment technology index.Reliability of the present invention is high: slide gauge method realizes based on FPGA, and in the case of high-grade fpga chip, this processing method reliability is high, can be applicable to space industry.

Description

A kind of step delay pulse implementation method based on slide gauge method

Technical field

The invention belongs to echo wave signal acquisition field, particularly relate to a kind of step delay pulse based on slide gauge method real Existing method.

Background technology

GPR passes through transmitting and the echo wave signal acquisition of impulse wave, it is achieved the detection to shallow underground target.With it Speed is fast, be easily achieved and the advantage such as high-resolution, is widely used.Pulse wave radar mostly is nanosecond or picosecond width, very Difficulty realizes real-time sampling on circuit, therefore uses equivalent sampling method more.In equivalent sampling, radar transmitter need to be realized and trigger arteries and veins Punching and receiver trigger fine delay value between pulse, and then complete echo wave signal acquisition.

In existing realization delay scheme, use delay chips and speed oblique wave hardware circuit the implementation method such as to build more.Its In, delay chip mostly is inferior grade chip, and in the space industry requiring high reliability, this scheme cannot use.Speed oblique wave Hardware circuit building plan, postpones reliability and postpones precision height.But hardware circuit is complex, harsh at circuit weight demands In the case of, it is difficult to use；And circuit once fixes, postponing precision and fix therewith, project compatibility is poor.Delay chip scheme exists Space industry cannot use, mainly explanation speed oblique wave hardware circuit building plan.

Speed oblique wave hardware circuit is built method and is mainly relatively realized delay scheme by speed harmonic ratio, it is achieved principle such as Fig. 1 Shown in.After transmitter triggers pulse Tr_pulse output, drive circuit exports fast harmonic wave.Slow oblique wave inputs number by adjusting DAC Word value realizes, and inputs the adjustable numerical value of DAC, and DAC output level changes.When slow ramp level value is more than fast ramp level value, defeated Go out one fixed width receiver and trigger pulse Rx_pulse.When slow oblique wave changes △ V, receiver triggers pulse Rx_pulse and changes △ T, thus realize the delay step value between Tr_pulse and Rx_pulse.Wherein, precision is postponed by fast ramp slopes and the most oblique Ripple DAC output voltage change precision together decides on.

Though such scheme can realize step delay, and it is high to postpone reliability, but shortcoming is as follows:

1) hardware circuit expense is big.

Owing to speed oblique wave is both needed to be realized by hardware circuit, increasing hardware circuit complexity and expense, complete machine weight is also Increased.

Fast harmonic wave is realized by integrating circuit, increases electric capacity and resistance unit；Slow oblique wave is realized by DAC-circuit, increases DAC chip.At the space industry that weight demands is harsh, it is difficult to be widely used.

2) length of delay is non-adjustable

In speed oblique wave delay scheme, once circuit is fixed, then postpone precision and fix, can not adjust delay according to demand Value, scheme adaptability is poor.

Summary of the invention

For solving above-mentioned technical problem, the present invention provides a kind of step delay pulse realization side based on slide gauge method Method, it is based on slide gauge method, high by using the PLL of FPGA to realize stepping, reliability and precision, and hardware circuit is without lattice Overhead.

The step delay pulse implementation method based on slide gauge method of the present invention, it processes chip and vernier based on FPGA Slide calliper rule method generates launches/receives trigger delay pulse, specifically includes following steps:

Step 1, generates coarse delay counter value a and the computing formula of thin delay counter value b, table based on slide gauge method It is shown as:

With

Wherein, n is the thin number postponed in total delay, and k is the width of enumerator used in this method；

Step 2, arranges transmitting on FPGA process chip and triggers pulse generation module and receive triggering pulse generation module, And process chip input base frequency clock frequency F to FPGA_base, its base frequency clock cycle is T_base, and launch triggering pulse generation mould It is A that the transmitting of block triggers pulse Clock Multiplier Factor, receives the reception triggering pulse Clock Multiplier Factor B triggering pulse generation module；

Step 3, substitutes into step 1 obtain the described triggering pulse Clock Multiplier Factor A and reception triggering pulse Clock Multiplier Factor B that launches Formula, calculate coarse delay counter value a and thin delay counter value b；

Step 4, launches thin delay counter value b as input Counter Value input and triggers pulse generation module, will be thick Delay counter value a and thin delay counter value b and value be input to receive as input Counter Value and trigger pulse generation mould Block, launches and triggers pulse generation module and receiving and trigger pulse generation module and all add 1 triggering Counter Value at rising edge clock, When launching the local Counter Value triggering pulse generation module and reception triggering pulse generation module equal to input Counter Value, Triggering pulse is launched in output and reception triggers pulse.

The beneficial effects of the present invention is:

The present invention is compared to speed oblique wave hardware circuit and builds method, and hardware circuit is without overhead: speed oblique wave hardware Circuit builds method needs extra hardware spending, and slide gauge method utilization FPGA is internally integrated PLL and realizes step delay, it is not necessary to Additional hardware circuit overhead.

The present invention is compared to speed oblique wave hardware circuit and builds method, and length of delay is adjustable: speed oblique wave hardware circuit is built Method, once circuit is fixed, then length of delay is fixed, and can not adjust length of delay according to demand, and adaptability is poor；The vernier calliper of the present invention Chi method, can change length of delay with adjustment technology index.

The reliability of the present invention is high: slide gauge method realizes based on FPGA, in the case of high-grade fpga chip, and this process Method reliability is high, can be applicable to space industry.

Accompanying drawing explanation

Fig. 1 is that speed oblique wave of the prior art postpones implementation method schematic diagram；

Fig. 2 is the step delay pulse implementation method flow chart based on slide gauge method of the present invention；

Fig. 3 is the slide gauge method base frequency clock of the present invention, launches and trigger clock and receive triggering timing relationship figure；

Fig. 4 is embodiment one schematic diagram of the step delay pulse implementation method based on slide gauge method of the present invention.

Detailed description of the invention

The present invention seeks to produce and specify the delay width required, according to slide gauge method, this delay width is by coarse delay Width and the thin width that postpones collectively constitute.Wherein, coarse delay width is several coarse delay precision composition, if carefully postponing width is Dry the thin precision that postpones forms.The present invention specifies coarse delay precision to be receiver trigger clock cycle, and the thin precision that postpones is for receiving Machine trigger clock cycle and the difference of transmitter trigger clock cycle.According to specifying the delay width required, calculated by formula To the coarse delay precision number needed and the thin precision number that postpones, then by controlling logic realization length of delay.

Present invention step delay based on slide gauge method pulse implementation method processes chip and slide gauge based on FPGA Method, generates to launch/receive and triggers pulse daley pulse, and pulse daley precision 79.4ps.

1) generate length of delay according to slide gauge method, length of delay is divided into coarse delay value and thin length of delay.If:

Total retardation value: Tdelay

Coarse delay value Tc_delay

Thin length of delay: Tf_delay

Coarse delay precision: △ T

Carefully postpone precision: △ t

Coarse delay counter value: a

Thin delay counter value: b

Then have:

T_delay=T_{c_delay}+T_{f_delay} (1)

Wherein

T_delay=n × Δ t (2)

N: in total retardation value Tdelay, the thin number postponing △ t.

It is respectively as follows: according to slide gauge method, coarse delay value and thin length of delay

$T_{f\_delay}=mod\left(\frac{T_{delay}}{\mathrm{\Δ}T}\right)---\left(4\right)$

Coarse delay counter value a (coarse delay number in total retardation value) is:

Thin delay counter value b is:

$b=\frac{T_{f\_delay}}{\mathrm{\Δ}t}=\frac{\mathrm{mod}\left(\frac{T_{delay}}{\mathrm{\Δ}T}\right)}{\mathrm{\Δ}t}---\left(6\right)$

Then formula (1) and (2) become:

T_delay=n × Δ t=a × Δ T+b × Δ t (7)

Slide gauge method protocol procedures figure, sequential chart and figure illustrate as shown in Figure 2.The slide gauge method fundamental frequency of the present invention Clock, transmitting trigger clock and receive triggering timing relationship as shown in Figure 3.

If:

Base frequency clock frequency: Fbase

Base frequency clock cycle: Tbase

Launch and trigger pulse Clock Multiplier Factor: A

Receive and trigger pulse Clock Multiplier Factor: B

Launch trigger clock cycle: Ttr

Receive trigger clock cycle: Trx

Coarse delay precision △ T:Trx

Thin delay precision △ t:Trx-Ttr

Have:

$F_{base}=\frac{1}{T_{base}}---\left(8\right)$

Launching trigger clock cycle Ttr is:

$T_{tr}=\frac{T_{base}}{A}---\left(9\right)$

Receiving trigger clock cycle Trx is:

$T_{rx}=\frac{T_{base}}{B}---\left(10\right)$

Wherein, coarse delay precision △ T is for receiving trigger clock cycle Trx, and the thin precision △ t of delay triggers for launching/receiving Clock cycle difference, it may be assumed that

$\mathrm{\Δ}t=T_{rx}-T_{tr}=\frac{T_{base}\×(A-B)}{A\×B}---\left(11\right)$

According to formula T_delay=n × Δ t=a × Δ T+b × Δ t,

Length of delay n △ t is:

N × Δ t=a × T_rx+b×(T_rx-T_tr)=(a+b) × T_rx-b×T_tr (12)

According to slide gauge method andAnd formula, For obtaining the length of delay of n △ t, coarse delay counter value a is:

Thin delay counter b is:

$b=\frac{mod\left(\frac{n\×\mathrm{\Δ}t}{T_{rx}}\right)}{\mathrm{\Δ}t}=mod\left(\frac{n\×(A-B)}{A}\right)---\left(14\right)$

Consider that FPGA realizes convenient, give here

A=2^k

B=2^k-1 (15)

Thus formula 2.12 and 2.13 can be reduced to:

$b=mod\left(\frac{n\×(A-B)}{A}\right)=mod\left(\frac{n}{2^k}\right)---\left(17\right)$

I.e. n being quantified as after N is, low k position is b, and high (N-k) position is a.

Embodiment one

Indices is as follows:

FPGA input clock cycle: 320ns

Launch and trigger clock multiplier coefficient A:64

Receive and trigger clock multiplier coefficient B: 63

According to formulaDelay precision is 79.4ps.

If maximum delay value Tdelay is 3000* △ t, and transmitting triggering impulse scaler value width is log2 (64)=6, Receiving and triggering impulse scaler width is log2 (3000/64+64)=7.

As shown in Figure 4, input base frequency clock frequency is 3.125MHz (clock cycle is 320ns), and frequency multiplication 64 times obtains respectively Obtain again receiving triggering clock frequency 196.875MHz to launching triggering clock frequency 200MHz, frequency multiplication 63；

According to length of delay n* △ t and formulaAnd formula Obtain coarse delay counter value and thin delay counter value.Assume n=3000, then:

Coarse delay value a=46, thin length of delay b=56.

Input b=56 is to launching triggering pulse generation module respectively；Input a+b=102 generates mould to receiving triggering pulse Block

Launch/receive triggering pulse generation module and safeguard local Counter Value respectively, triggering at rising edge clock, counting Device value adds 1.When local Counter Value is equal to input Counter Value, exports to launch and trigger pulse and receive triggering pulse.

In the present embodiment, delay precision is 79.4ps, can change length of delay with adjustment technology index.

By revising the frequency multiplication value of PLL, adjust and postpone precision.Frequency multiplication value and delay accuracy relation are as shown in table 1.

Table 1

Amendment input clock cycle value, adjusts and postpones precision, input clock cycle value and delay accuracy relation such as table 2 institute Show.

Table 2

Certainly, the present invention also can have other various embodiments, without departing substantially from present invention spirit and in the case of referring to, ripe Know those skilled in the art to work as and can make various corresponding change and deformation according to the present invention, but these change accordingly and become Shape all should belong to the protection domain of appended claims of the invention.

Claims (1)

1. a step delay pulse implementation method based on slide gauge method, it is characterised in that based on FPGA process chip and Slide gauge method generates launches/receives trigger delay pulse, specifically includes following steps:

Step 1, generates coarse delay counter value a and the computing formula of thin delay counter value b based on slide gauge method, represents For:

With $b=\mathrm{mod}\left(\frac{n\×(A-B)}{A}\right)=\mathrm{mod}\left(\frac{n}{2^k}\right);$

Wherein, n is the thin number postponed in total delay, and k is the width of enumerator used in this method；

Step 2, arranges transmitting on FPGA process chip and triggers pulse generation module and receive triggering pulse generation module, and to FPGA processes chip input base frequency clock frequency F_base, its base frequency clock cycle is T_base, and launch triggering pulse generation module Launching triggering pulse Clock Multiplier Factor is A, and the reception triggering pulse Clock Multiplier Factor receiving triggering pulse generation module is B；

Step 3, substitutes into, by the described triggering pulse Clock Multiplier Factor A and reception triggering pulse Clock Multiplier Factor B that launches, the public affairs that step 1 obtains Formula, calculates coarse delay counter value a and thin delay counter value b；

Step 4, launches thin delay counter value b as input Counter Value input and triggers pulse generation module, by coarse delay Counter Value a and thin delay counter value b and value be input to receive as input Counter Value and trigger pulse generation module, Penetrate triggering pulse generation module and receiving to trigger pulse generation module and all add 1, when sending out triggering Counter Value at rising edge clock When penetrating the local Counter Value triggering pulse generation module and reception triggering pulse generation module equal to input Counter Value, output Launch and trigger pulse and receive triggering pulse.