CN114679179A - High-speed time domain reconfigurable hybrid analog-to-digital converter - Google Patents

High-speed time domain reconfigurable hybrid analog-to-digital converter Download PDF

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CN114679179A
CN114679179A CN202210271022.6A CN202210271022A CN114679179A CN 114679179 A CN114679179 A CN 114679179A CN 202210271022 A CN202210271022 A CN 202210271022A CN 114679179 A CN114679179 A CN 114679179A
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time
signal
voltage
digital converter
output
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朱樟明
赵鑫
李登全
沈易
刘术彬
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Xidian University
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Xidian University
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/004—Reconfigurable analogue/digital or digital/analogue converters
    • H03M1/005—Reconfigurable analogue/digital or digital/analogue converters among different converters types
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/50—Analogue/digital converters with intermediate conversion to time interval

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  • Analogue/Digital Conversion (AREA)

Abstract

The invention discloses a high-speed time domain reconfigurable hybrid analog-to-digital converter, which comprises: the successive approximation type analog-to-digital converter is used for carrying out coarse quantization on the input differential voltage signal to obtain a margin voltage signal and outputting a first digital signal; the margin amplifier is connected with the successive approximation type analog-to-digital converter and used for amplifying a margin voltage signal; the voltage-time converter is connected with the margin amplifier and used for converting the amplified margin voltage signal into a time signal; the time-to-digital converter is connected with the voltage-to-time converter and is used for converting the time signal into a second digital signal; and the output module is connected with the successive approximation type analog-to-digital converter and the time-to-digital converter and is used for combining the first digital signal and the second digital signal and outputting a digital code signal. The high-speed time domain reconfigurable hybrid analog-to-digital converter provided by the invention has the advantages that the design complexity, the power consumption and the area of the high-speed high-precision ADC in the voltage domain under the low power voltage are obviously reduced.

Description

High-speed time domain reconfigurable hybrid analog-to-digital converter
Technical Field
The invention belongs to the technical field of analog-to-digital conversion, and particularly relates to a high-speed time domain reconfigurable hybrid analog-to-digital converter.
Background
An Analog-to-Digital Converter (ADC) is a Converter that converts an Analog quantity, which is compared with a standard quantity (or a reference quantity), into a discrete signal represented by a binary number. With the rapid development of wireless communication, radar systems, instruments and meters, the demand for high-speed and high-precision RF a/D converters has increased dramatically. The pipeline architecture is the preferred implementation of high-speed high-precision ADC, which has better compromise performance in terms of speed and precision.
Currently, the existing pipeline ADC mainly adopts a pure voltage domain ADC. However, with the advance of deep submicron CMOS processes, the design difficulty of a high-performance voltage amplifier in a pure voltage domain pipeline ADC increases sharply, especially under low power supply voltage, the swing amplitude and the dc gain of the ADC cannot meet the design requirements of a high-speed high-precision ADC, and meanwhile, the structure of the whole pure voltage domain faces huge power consumption and linearity pressure.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides a hybrid analog-to-digital converter with high speed and reconfigurable time domain. The technical problem to be solved by the invention is realized by the following technical scheme:
a high-speed time domain reconfigurable hybrid analog-to-digital converter, comprising:
The successive approximation type analog-to-digital converter is used for carrying out coarse quantization on the input differential voltage signal to obtain a margin voltage signal and outputting a first digital signal;
the margin amplifier is connected with the successive approximation type analog-to-digital converter and used for amplifying the margin voltage signal;
the voltage-time converter is connected with the residue amplifier and is used for converting the amplified residue voltage signal into a time signal;
the time-to-digital converter is connected with the voltage-to-time converter and is used for converting the time signal into a second digital signal;
and the output module is connected with the successive approximation type analog-to-digital converter and the time-to-digital converter and is used for combining the first digital signal and the second digital signal and outputting a digital code signal.
In an embodiment of the present invention, the successive approximation type analog-to-digital converter is a one-step R-bit SAR ADC, which includes a first sampling switch, a second sampling switch, a first capacitor array, a second capacitor array, a comparator set, and a control logic unit; wherein the content of the first and second substances,
an analog input signal Vin serving as a first input signal of the voltage domain SAR ADC is connected to a first input end of the first capacitor array through the first sampling switch;
An analog reference signal Vref is used as a second input signal of the voltage domain SAR ADC and is connected to the first input end of the second capacitor array through the second sampling switch;
the output end of the first capacitor array and the output end of the second capacitor array are respectively connected with the first input end and the second input end of the comparator group, and meanwhile, the output end of the first capacitor array and the output end of the second capacitor array are used as the first output end of the successive approximation type analog-to-digital converter to be connected with the residue amplifier so as to output a residue voltage signal V to the residue amplifierRES；
A third input end of the comparator group is connected with a first clock signal CKC; the output end of the comparator group is connected with the input end of the control logic unit;
the first output end of the control logic unit is connected with the second input end of the first capacitor array, and the second output end of the control logic unit is connected with the second input end of the second capacitor array;
and a third output end of the control logic unit is used as a second output end of the successive approximation type analog-to-digital converter to output a Q-bit first digital signal.
In one embodiment of the invention, the residue amplifier comprises an open loop dynamic amplifier, a third switch, a fourth switch, a first capacitor and a second capacitor; wherein, the first and the second end of the pipe are connected with each other,
A first input end of the open-loop dynamic amplifier is used as an input end of a margin amplifier and is connected with a first output end of the successive approximation type analog-to-digital converter, and a second input end of the open-loop dynamic amplifier is connected with a second clock signal clk;
the first output end of the open-loop dynamic amplifier is connected with the first capacitor through the third switch; the second output end of the open-loop dynamic amplifier is connected with the second capacitor through the fourth switch;
the other ends of the first capacitor and the second capacitor are grounded;
the common end of the third switch and the first capacitor is used as the first output end of the margin amplifier and is connected with the first input end of the voltage-time converter so as to output an amplified margin voltage signal V to the third switchP；
The common end of the fourth switch and the second capacitor is used as the second output end of the margin amplifier and is connected with the second input end of the voltage-time converter so as to output an amplified margin voltage signal V to the second input end of the voltage-time converterN。
In one embodiment of the present invention, the voltage-to-time converter includes transistors M1-M6, a first buffer, a second buffer, and a current source; wherein, the first and the second end of the pipe are connected with each other,
the grids of the M1 and the M2 are respectively used as a first input end and a second input end of the voltage-time converter and are connected with a first output end and a second output end of the residue amplifier;
The sources of M1 and M2 and the drain of M7 are mutually connected and grounded through a current source;
the drain of M1 is connected to the source of M3, and the drain of M2 is connected to the source of M4;
the grid of the M3 is connected with the grid of the M4 and is commonly connected with a bias voltage VB terminal;
a drain of M3 and a drain of M5 are commonly connected to an input terminal of the first buffer, a drain of M4 and a drain of M6 are commonly connected to an input terminal of the second buffer;
the sources of M5, M6 and M7 are connected to a voltage VDD terminal; the gates of M5, M6, and M7 are commonly connected to a clock control signal CLKT;
the output end of the first buffer is used as the first output end of the voltage-time converter to be connected with the time-numberA first input terminal of the converter for inputting a time signal T theretoSTR；
The output end of the second buffer is used as the second output end of the voltage-time converter and is connected with the second input end of the time-digital converter so as to input the time signal T to the second input end of the voltage-time converterSTO。
In one embodiment of the invention, the time-to-digital converter comprises a delay chain, a bit selector, a D flip-flop array, a continuous-time comparator and a decoder; wherein, the first and the second end of the pipe are connected with each other,
the delay chain comprises N controllable delay units and N +1 gating switches; the N controllable delay units are connected with the N +1 gating switches in series at intervals, and the input end of the 1 st controllable delay unit is used as the first input end of the time-to-digital converter and is connected with the first output end of the voltage-to-time converter through the first gating switch;
Wherein N is 2M-1M is the highest total number of bits of the second digital signal;
the input end of the bit selector inputs the configuration precision, and the output end of the bit selector is correspondingly connected with N +1 gating switches for controlling the working state of the corresponding controllable delay unit;
the D flip-flop array comprises N D flip-flops; the D end of the ith D trigger is connected with the common ends of the (i + 1) th switch and the (i + 1) th controllable delay unit, and i is more than or equal to 1 and less than or equal to N-1; the D end of the Nth D trigger is connected with the output end of the Nth controllable delay unit through an (N + 1) th switch;
the clk ends of the N D flip-flops are used as second input ends of the time-to-digital converter and connected with a second output end of the voltage-to-time converter; q ends of the N D triggers are respectively connected with a plurality of first input ends of the decoder so as to output a plurality of low-order codes of the second digital code;
the positive input end and the negative input end of the continuous time comparator are respectively connected with the first output end and the second output end of the voltage-time conversion module; the output end of the continuous time comparator is connected with the second input end of the decoder to output the highest-order code of the second digital code;
and the output end of the decoder is used as the output end of the time-to-digital converter to output the 0-to-M bit second digital signal.
In one embodiment of the invention, each of the controllable delay cells includes transistors M8-M13; wherein, the first and the second end of the pipe are connected with each other,
the gate of M8 is connected to input signal BIA 2; the drain electrode of M8 is connected with the source electrodes of M9 and M10 respectively; the source of M8 is grounded;
the drain of M9, the gate of M10, the drain of M11 and the gate of M12 are connected with each other;
the gates of M9 and M11 are connected and serve as the input terminals of the current controllable delay unit; the drain of M10 and the drain of M12 are connected and used as the output end of the current controllable delay unit;
the gate of M13 is connected to input signal BIA1, the source is connected to voltage VDD terminal, and the drain is connected to the sources of M11 and M12, respectively.
The invention has the beneficial effects that:
1. the invention realizes the reconstruction of the speed and the precision of the integral mixed analog-digital converter through a first-stage Q-bit successive approximation type analog-digital converter and a second-stage time-digital converter, a middle-stage margin amplifier and a voltage-time converter amplify the margin voltage of the first stage and convert the margin voltage into a time interval to quantize the second stage, and the final N-bit digital code is output after the quantization results of the two stages are combined; the structure obviously reduces the design complexity, power consumption and area of the high-speed high-precision ADC in the voltage domain under the low power supply voltage, and has higher conversion efficiency and conversion precision;
2. The high-speed time domain reconfigurable hybrid analog-to-digital converter provided by the invention realizes the configurability of the precision and the speed of a single channel, thereby improving the performance and the energy efficiency of the whole analog-to-digital converter.
The present invention will be described in further detail with reference to the drawings and examples.
Drawings
Fig. 1 is a structural block diagram of a high-speed time domain reconfigurable hybrid analog-to-digital converter according to an embodiment of the present invention;
fig. 2 is a circuit structure diagram of a voltage domain SAR ADC according to an embodiment of the present invention;
fig. 3 is a schematic circuit diagram of a residue amplifier according to an embodiment of the present invention;
FIG. 4 is a diagram of a practical circuit structure of a voltage-to-time converter according to an embodiment of the present invention;
FIG. 5 is a schematic structural diagram of a configurable time-to-digital converter according to an embodiment of the present invention;
fig. 6 is a structure diagram of a practical application circuit of a controllable delay unit according to an embodiment of the present invention;
fig. 7 is a schematic diagram of a time-to-digital converter with a precision of 0-3 according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Example one
Referring to fig. 1, fig. 1 is a block diagram of a high-speed time domain reconfigurable hybrid analog-to-digital converter according to an embodiment of the present invention, which includes:
the successive approximation type analog-to-digital converter 1 is used for carrying out coarse quantization on an input differential voltage signal to obtain a margin voltage signal and outputting a first digital signal;
the residue amplifier 2 is connected with the successive approximation type analog-to-digital converter 1 and used for amplifying a residue voltage signal;
the voltage-time converter 3 is connected with the margin amplifier 2 and used for converting the amplified margin voltage signal into a time signal;
a time-to-digital converter 4 connected to the voltage-to-time converter 3 for converting the time signal into a second digital signal;
and the output module 5 is connected with the successive approximation type analog-to-digital converter 1 and the time-to-digital converter 4, and is used for combining the first digital signal and the second digital signal and outputting a digital code signal.
Specifically, the high-speed time-domain reconfigurable hybrid analog-to-digital converter provided by this embodiment is implemented by a two-stage structure, where the first stage is formed by a Q-bit successive approximation type analog-to-digital converter, the second stage configures a time-to-digital converter to 0 to M-bit precision, so as to implement speed and precision reconstruction of the overall hybrid analog-to-digital converter, the middle-stage residue amplifier and the voltage-to-time converter amplify the residue voltage of the first stage and convert the residue voltage into a time interval, and quantize the time interval to the second stage, and the two-stage quantization results are combined to implement an output code with overall Q to (Q + M) precision.
In the present embodiment, the Successive Approximation type Analog-to-Digital Converter 1 is a voltage domain one-step R (R ═ 1,2,3, …) bit SAR ADC (SAR ADC, Successive Approximation Register Analog to Digital Converter). The one-step R-bit successive approximation type analog-to-digital converter is an analog-to-digital converter which quantizes a continuous analog signal into an R-bit digital code in a single conversion period, can increase the conversion speed by R times compared with the traditional SAR ADC, and is generally applied to occasions with single channel, high speed, high precision and the like.
Specifically, referring to fig. 2, fig. 2 is a circuit structure diagram of a voltage domain SAR ADC according to an embodiment of the present invention, which includes a first sampling switch K1, a second sampling switch K2, a first capacitor array DAC1, a second capacitor array DAC2, a comparator group, and a control logic unit; wherein the content of the first and second substances,
the analog input signal Vin as a first input signal of the voltage domain SAR ADC is connected to a first input terminal of the first capacitor array DAC1 through a first sampling switch K1;
the analog reference signal Vref is connected as a second input signal of the voltage domain SAR ADC to the first input terminal of the second capacitor array DAC2 through the second sampling switch K2;
the output end of the first capacitor array DAC1 and the output end of the second capacitor array DAC2 are respectively connected with the first input end and the second input end of the comparator group, and simultaneously, the first output end of the successive approximation type analog-to-digital converter 1 is connected with the margin amplifier 2 to output a margin voltage signal V to the margin amplifier RES；
The third input end of the comparator group is connected with the first clock signal CKC; the output end of the comparator group is connected with the input end of the control logic unit;
a first output end of the control logic unit is connected with a second input end of the first capacitor array DAC1, and a second output end of the control logic unit is connected with a second input end of the second capacitor array DAC 2;
a third output end of the control logic unit is used as a second output end of the successive approximation type analog-to-digital converter 1 to output a Q-bit first digital signal.
In this embodiment, the working principle of the one-step R-bit SAR ADC is as follows: if R ═ 1, in each conversion cycle, output one-bit digital code, i.e. for the first stage of Q bits, Q conversion cycles are required, if R ═ 2, then in each quantization cycle output two-bit digital code, for the first stage of Q bits, Q/2 conversion cycles are required, with respect to R ═ 1, the required conversion cycle is halved, and the speed is doubled; and the like when R is 3,4 ….
It should be noted that, in this embodiment, the specific circuit structures of the first capacitor array DAC1 and the second capacitor array DAC2 may refer to the existing similar circuit. Generally, the upper and lower plates of the capacitor array can be respectively used as the first input end and the second input end of the array by a clock, and the output end is a common end of the upper plates of all the capacitors. In addition, as for the specific circuit structure of the comparator group and the control logic unit, reference may also be made to the related art, which is not limited in this embodiment.
Further, referring to fig. 3, fig. 3 is a schematic circuit structure diagram of a residue amplifier according to an embodiment of the present invention, which includes: the circuit comprises an open-loop dynamic amplifier Gm, a third switch K3, a fourth switch K4, a first capacitor C1 and a second capacitor C2; wherein the content of the first and second substances,
a first input end of the open-loop dynamic amplifier Gm is used as an input end of the residue amplifier 2 and is connected with a first output end of the successive approximation type analog-to-digital converter 1, and a second input end of the open-loop dynamic amplifier Gm is connected with a second clock signal clk;
the first output end of the open-loop dynamic amplifier Gm is connected with a first capacitor C1 through a third switch K3; the second output end of the open-loop dynamic amplifier Gm is connected with a second capacitor C2 through a fourth switch K4;
the other ends of the first capacitor C1 and the second capacitor C2 are both grounded;
the common terminal of the third switch K3 and the first capacitor C1 is used as the second terminal of the residue amplifier 2An output terminal connected to the first input terminal of the voltage-time converter 3 for outputting the amplified residual voltage signal V theretoP；
The common terminal of the fourth switch K4 and the second capacitor C2 is connected to the second input terminal of the voltage-to-time converter 3 as the second output terminal of the residue amplifier 2, so as to output the amplified residue voltage signal V theretoN。
Further, referring to fig. 4, fig. 4 is a circuit structure diagram of an actual application of a voltage-to-time converter according to an embodiment of the present invention, which includes transistors M1-M6, a first buffer Buff1, a second buffer Buff2, and a current source I; wherein the content of the first and second substances,
The gates of the M1 and M2 are respectively used as a first input end and a second input end of the voltage-time converter 3 to be connected with a first output end and a second output end of the residue amplifier 2;
the sources of M1 and M2 and the drain of M7 are connected with each other and grounded through a current source I;
the drain of M1 is connected to the source of M3, and the drain of M2 is connected to the source of M4;
the grid of the M3 is connected with the grid of the M4 and is commonly connected with a bias voltage VB terminal;
the drain of M3 and the drain of M5 are commonly connected to the input terminal of a first buffer Buff1, and the drain of M4 and the drain of M6 are commonly connected to the input terminal of a second buffer Buff 2;
the sources of M5, M6 and M7 are connected to a voltage VDD terminal; the gates of M5, M6, and M7 are commonly connected to a clock control signal CLKT;
the output of the first buffer Buff1, which serves as the first output of the voltage-to-time converter 3, is connected to the first input of the time-to-digital converter 4 for inputting the time signal T theretoSTR；
The output of the second buffer buf 2, which serves as a second output of the voltage-to-time converter 3, is connected to a second input of the time-to-digital converter 4 for inputting thereto the time signal TSTO。
In this embodiment, the transistors M1, M2, M3, and M4 are all NMOS transistors, and the transistors M5, M6, and M7 are all PMOS transistors. Specifically, the operating principle of the voltage-time converter is as follows:
When the clock control signal CLKT of the voltage-to-time converter is at a low level, the first output terminal and the second output terminal are charged to a high level through the PMOS transistors M5 and M6 and are kept at the high level after passing through the buffer; when the clock control signal CLKT of the voltage-to-time converter is at a high level, the signal V amplified by the residue amplifierPAnd VNInput to the first and second input terminals of the voltage-to-time converter for amplification, VPAnd VNThe difference in the magnitude between the two transistors makes the conduction time of the NMOS transistors M1 and M2 different, which causes the output terminals of the voltage-time converter to start discharging differently, so that the time interval T occursRESThereby completing the conversion of the voltage difference to a time interval, and the signal is quantized by a reconfigurable time-to-digital converter of the later stage.
In this embodiment, the second level structure is mainly used for quantizing the residue voltage. Since the margin voltage is usually a small signal, it is suitable for processing with a super high-speed converter. A Time-to-Digital Converter (TDC) is a Converter that quantizes a Time interval into a Digital code, and has the characteristics of ultra high speed and low power consumption. Therefore, in the present embodiment, the second stage structure uses a super-high speed low power time domain time-to-digital converter to quantize the residue voltage.
Specifically, referring to fig. 5, fig. 5 is a schematic structural diagram of a configurable time-to-digital converter according to an embodiment of the present invention, which includes a delay chain 41, a bit selector 42, a D flip-flop array 43, a continuous time comparator 44, and a decoder 45; wherein, the first and the second end of the pipe are connected with each other,
the delay chain 41 comprises N controllable delay units Td1～TdNAnd N +1 gate switches S1～SN+1(ii) a N controllable delay units Td1～TdNAnd N +1 gating switches S1～SN+1Are connected in series at intervals, and the 1 st controllable delay unit Td1As a first input of the time-to-digital converter 4, by means of a first gating switchS1 is connected to the first output terminal of the voltage-to-time converter 3;
wherein N is 2M-1And M is the highest total number of bits of the second digital signal.
The input terminal of the bit selector 42 inputs the precision of the configuration, e.g. 3, 4, etc., and the output terminal thereof is connected with N +1 gate switches S1～SN+1For controlling the working state of the corresponding controllable delay unit.
The D flip-flop array 43 includes N D flip-flops; wherein, the D end of the ith D trigger is connected with the (i + 1) th switch Si+1And the (i + 1) th controllable delay unit Tdi+1I is more than or equal to 1 and less than or equal to N-1 at the public end; the D end of the Nth D trigger passes through the (N + 1) th switch SN+1And the Nth controllable delay unit TdNThe output ends of the two-way valve are connected;
the clk ends of the N D flip-flops are used as second input ends of the time-to-digital converter 4 and connected to a second output end of the voltage-to-time converter 3; the Q terminals of the N D flip-flops are respectively connected to a plurality of first input terminals of the decoder 45 to output a plurality of low-order codes of the second digital code;
A positive input end and a negative input end of the continuous time comparator 44 are respectively connected with a first output end and a second output end of the voltage-time conversion module 3; the output terminal of the continuous-time comparator 44 is connected to the second input terminal of the decoder 45 to output the highest-order code of the second digital code;
an output terminal of the decoder 45 outputs the 0 to M-bit second digital signal as an output terminal of the time-to-digital converter 4.
Further, referring to fig. 6, fig. 6 is a circuit structure diagram of an actual application of the controllable delay unit according to the embodiment of the present invention, wherein each controllable delay unit includes transistors M8 to M13; wherein the content of the first and second substances,
the gate of M8 is connected to input signal BIA 2; the drain electrode of M8 is connected with the source electrodes of M9 and M10 respectively; the source of M8 is grounded;
the drain of M9, the gate of M10, the drain of M11 and the gate of M12 are connected with each other;
the gates of M9 and M11 are connected and serve as the input terminals of the current controllable delay unit; the drain of M10 and the drain of M12 are connected and used as the output end of the current controllable delay unit;
the gate of M13 is connected to input signal BIA1, the source is connected to voltage VDD terminal, and the drain is connected to the sources of M11 and M12, respectively.
The structure and the operation principle of the time-to-digital converter circuit provided in the present embodiment will be described in detail below by taking a time-to-digital converter configurable to 0 to 3 bits as an example.
Referring to fig. 7, fig. 7 is a schematic structural diagram of a time-to-digital converter with a precision of 0-3 according to an embodiment of the present invention. Wherein N is 2M-1The delay chain includes 4 controllable delay units and 5 gating switches, and correspondingly, the D flip-flop array includes 4D flip-flops, and the specific connection relationship is shown in fig. 7.
The operation principle of the configurable 0-to-3-bit time-to-digital converter provided by the embodiment is as follows:
when the time-to-digital converter is configured to be 0 bit, all the gating switches are in an off state, and at the moment, the delay chain, the D trigger array, the bit selector and the decoder do not work.
When the time-to-digital converter is configured to be 1 bit, the delay chain, the D flip-flop array, the bit selector and the decoder are not operated, and the continuous time comparator compares the time signal TSTRAnd TSTOA 1-bit precision is obtained, i.e. the TDC configuration is 1-bit precision.
When the time-to-digital converter is configured to 2 bits, the continuous-time comparator compares the time signal TSTRAnd TSTOObtaining the MSB of the most significant digit code; the first output end, the second output end and the third output end of the bit selector are connected with the gating switch S1～S3And closing it, i.e. only the front 2M-1(current M2) 2 delay units and first 2M-1(M2) 2D flip-flops, T STOSignal timing interval information TRESLatching in the first two D flip-flops and outputting D1、D2A signal. The second input end of the decoder is connected with the output end of the continuous time comparator, and a plurality of first input ends are respectively connected with D1、D2(ii) a The decoder calculates two-bit thermometer code D1D2After decoding into a one-bit digital code, the 2-bit digital code is combined with the comparison result MSB of the continuous time comparator to output.
When the time-to-digital converter is configured to 3 bits, the continuous-time comparator compares the signal TSTRAnd TSTOThe most significant digit code MSB is obtained, and the first output end, the second output end, the third output end, the fourth output end and the fifth output end of the bit selector are respectively connected with a gating switch S1～S5And closing it, i.e. only the front 2M-1(current M-3) 4 delay units and first 2M-1(M-3) -4D flip-flops, TSTOSignal timing interval information TRESLatching in the first four D flip-flops and outputting D1，D2，D3，D4A signal. The second input terminal of the decoder is connected with the output terminal of the continuous time comparator, and a plurality of first input terminals are connected with D1、D2、D3、D4(ii) a The decoder calculates four-bit thermometer code D1D2D3D4After decoding into two-bit digital code, the two-bit digital code is combined with the comparison result MSB of the continuous time comparator to output 3-bit digital code.
Thus, a second digital code of 0-3 bits is implemented.
Finally, the output module 5 combines the Q-bit first digital signal generated by the first-stage successive approximation type analog-to-digital converter and the 0-M-bit second digital signal generated by the second-stage time-to-digital converter, so as to output Q to (Q + M) -bit output codes.
The invention realizes the reconstruction of the speed and the precision of the integral mixed analog-digital converter through a first-stage Q-bit successive approximation type analog-digital converter and a second-stage time-digital converter, a middle-stage margin amplifier and a voltage-time converter amplify the margin voltage of the first stage and convert the margin voltage into time intervals to quantize the second stage, and the final N-bit digital code is output after the two-stage quantization results are combined; the structure obviously reduces the design complexity, power consumption and area of the high-speed and high-precision ADC in the voltage domain under the low power supply voltage, and has higher conversion efficiency and conversion precision. In addition, the high-speed time domain reconfigurable hybrid analog-to-digital converter provided by the invention realizes the single-channel configurability of precision and speed, thereby improving the performance and energy efficiency of the whole analog-to-digital converter.
The foregoing is a further detailed description of the invention in connection with specific preferred embodiments and it is not intended to limit the invention to the specific embodiments described. For those skilled in the art to which the invention pertains, numerous simple deductions or substitutions may be made without departing from the spirit of the invention, which shall be deemed to belong to the scope of the invention.

Claims (6)

1. A high-speed time domain reconfigurable hybrid analog-to-digital converter, comprising:
the successive approximation type analog-to-digital converter (1) is used for carrying out coarse quantization on an input differential voltage signal to obtain a margin voltage signal and outputting a first digital signal;
the residue amplifier (2) is connected with the successive approximation type analog-to-digital converter (1) and is used for amplifying the residue voltage signal;
the voltage-time converter (3) is connected with the residue amplifier (2) and is used for converting the amplified residue voltage signal into a time signal;
a time-to-digital converter (4) connected to the voltage-to-time converter (3) for converting the time signal into a second digital signal;
and the output module (5) is connected with the successive approximation type analog-to-digital converter (1) and the time-to-digital converter (4) and is used for combining the first digital signal and the second digital signal and outputting a digital code signal.
2. The high-speed time-domain reconfigurable hybrid analog-to-digital converter according to claim 1, characterized in that the successive approximation analog-to-digital converter (1) is a one-step R-bit SAR ADC comprising a first sampling switch (K1), a second sampling switch (K2), a first capacitor array (DAC1), a second capacitor array (DAC2), a comparator bank and a control logic unit; wherein, the first and the second end of the pipe are connected with each other,
An analog input signal Vin as a first input signal of a voltage domain SAR ADC is connected through the first sampling switch (K1) to a first input terminal of the first capacitor array (DAC 1);
an analog reference signal Vref as a second input signal of the voltage domain SAR ADC is connected through the second sampling switch (K2) to a first input of the second capacitive array (DAC 2);
the output end of the first capacitor array (DAC1) and the output end of the second capacitor array (DAC2) are respectively connected with the first input end and the second input end of the comparator group, and are simultaneously used as the first output end of a successive approximation type analog-to-digital converter (1) to be connected with the residue amplifier (2) so as to output a residue voltage signal V to the residue amplifierRES；
A third input end of the comparator group is connected with a first clock signal CKC; the output end of the comparator group is connected with the input end of the control logic unit;
a first output terminal of the control logic unit is connected to a second input terminal of the first capacitor array (DAC1), and a second output terminal of the control logic unit is connected to a second input terminal of the second capacitor array (DAC 2);
and a third output end of the control logic unit is used as a second output end of the successive approximation type analog-to-digital converter (1) to output a Q-bit first digital signal.
3. The high-speed time-domain reconfigurable hybrid analog-to-digital converter according to claim 1, characterized in that the residue amplifier (2) comprises an open-loop dynamic amplifier (Gm), a third switch (K3) and a fourth switch (K4), a first capacitor (C1) and a second capacitor (C2); wherein, the first and the second end of the pipe are connected with each other,
a first input end of the open-loop dynamic amplifier (Gm) is used as an input end of a margin amplifier (2) and is connected with a first output end of the successive approximation type analog-to-digital converter (1), and a second input end of the open-loop dynamic amplifier (Gm) is connected with a second clock signal clk;
a first output terminal of the open-loop dynamic amplifier (Gm) is connected to the first capacitor (C1) through the third switch (K3); a second output terminal of the open-loop dynamic amplifier (Gm) is connected to the second capacitor (C2) through the fourth switch (K4);
the other ends of the first capacitor (C1) and the second capacitor (C2) are both grounded;
the common end of the third switch (K3) and the first capacitor (C1) is used as the first output end of a margin amplifier (2) to be connected with the first input end of the voltage-time converter (3) so as to output an amplified margin voltage signal V to the first input end of the voltage-time converterP；
The common end of the fourth switch (K4) and the second capacitor (C2) is used as the second output end of the residue amplifier (2) to be connected with the second input end of the voltage-time converter (3) so as to output an amplified residue voltage signal V to the second input end of the voltage-time converter N。
4. The high-speed time-domain reconfigurable hybrid analog-to-digital converter according to claim 1, characterized in that the voltage-time converter (3) comprises transistors M1-M6, a first buffer (Buff1), a second buffer (Buff2) and a current source (I); wherein, the first and the second end of the pipe are connected with each other,
the grids of the M1 and the M2 are respectively used as a first input end and a second input end of the voltage-time converter (3) and are connected with a first output end and a second output end of the residue amplifier (2);
the sources of M1 and M2 and the drain of M7 are connected to each other and to ground through a current source (I);
the drain of M1 is connected with the source of M3, and the drain of M2 is connected with the source of M4;
the grid of the M3 and the grid of the M4 are connected and are connected with a bias voltage VB terminal in common;
the drain of M3 and the drain of M5 are commonly connected to the input terminal of the first buffer (Buff1), and the drain of M4 and the drain of M6 are commonly connected to the input terminal of the second buffer (Buff 2);
the sources of M5, M6 and M7 are connected with a voltage VDD end; the gates of M5, M6, and M7 are commonly connected to a clock control signal CLKT;
the output of the first buffer (Buff1) is connected as a first output of a voltage-to-time converter (3) to a first input of the time-to-digital converter (4) for inputting thereto a time signal T STR；
The secondThe output of the buffer (Buff2) is connected as a second output of the voltage-to-time converter (3) to a second input of the time-to-digital converter (4) for inputting thereto the time signal TSTO。
5. The high-speed time-domain reconfigurable hybrid analog-to-digital converter according to claim 1, characterized in that the time-to-digital converter (4) comprises a delay chain (41), a bit selector (42), a D flip-flop array (43), a continuous-time comparator (44) and a decoder (45); wherein the content of the first and second substances,
the delay chain (41) comprises N controllable delay units (T)d1～TdN) And N +1 gate switches (S)1～SN+1) (ii) a N controllable delay units (Td 1-TdN) and N +1 gating switches (S)1～SN+1) Spaced and connected in series, and the 1 st controllable delay unit (T)d1) As a first input of a time-to-digital converter (4), connected to a first output of said voltage-to-time converter (3) through a first gating switch (S1);
wherein N is 2M-1M is the highest total digit of the second digital signal;
the input end of the bit selector (42) inputs the configuration precision, and the output end thereof is correspondingly connected with N +1 gating switches (S)1～SN+1) For controlling the working state of the corresponding controllable delay unit;
the D flip-flop array (43) comprises N D flip-flops; wherein, the D end of the ith D trigger is connected with the (i + 1) th switch (S) i+1) And the (i + 1) th controllable delay unit (T)di+1) I is more than or equal to 1 and less than or equal to N-1 at the public end; the D end of the Nth D trigger passes through the (N + 1) th switch (S)N+1) And the Nth controllable delay unit (T)dN) The output ends of the two-way valve are connected;
the clk ends of the N D triggers are used as second input ends of a time-to-digital converter (4) and are connected with a second output end of the voltage-to-time converter (3); q ends of the N D flip-flops are respectively connected with a plurality of first input ends of the decoder (45) to output a plurality of low-order codes of the second digital code;
the positive input end and the negative input end of the continuous time comparator (44) are respectively connected with the first output end and the second output end of the voltage-time conversion module (3); the output end of the continuous time comparator (44) is connected with the second input end of the decoder (45) to output the highest bit code of the second digital code;
the output end of the decoder (45) is used as the output end of the time-to-digital converter (4) to output the second digital signal of 0 to M bits.
6. The high-speed time-domain reconfigurable hybrid analog-to-digital converter according to claim 1, wherein each of the controllable delay cells comprises transistors M8-M13; wherein, the first and the second end of the pipe are connected with each other,
the gate of M8 is connected to input signal BIA 2; the drain electrode of M8 is connected with the source electrodes of M9 and M10 respectively; the source of M8 is grounded;
The drain electrode of M9, the gate electrode of M10, the drain electrode of M11 and the gate electrode of M12 are mutually connected;
the gates of M9 and M11 are connected and used as the input end of the current controllable delay unit; the drain of M10 and the drain of M12 are connected and used as the output end of the current controllable delay unit;
m13 has a gate connected to input signal BIA1, a source connected to voltage VDD terminal, and a drain connected to the sources of M11 and M12, respectively.
CN202210271022.6A 2022-03-18 2022-03-18 High-speed time domain reconfigurable hybrid analog-to-digital converter Pending CN114679179A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117555212A (en) * 2024-01-11 2024-02-13 深圳市山海半导体科技有限公司 Time delay module, time-to-digital converter, system and method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117555212A (en) * 2024-01-11 2024-02-13 深圳市山海半导体科技有限公司 Time delay module, time-to-digital converter, system and method
CN117555212B (en) * 2024-01-11 2024-04-09 深圳市山海半导体科技有限公司 Time delay module, time-to-digital converter, system and method

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