JP7298366B2 - Capacitance detector - Google Patents

Description

The present invention relates to a capacitance detection device.

2. Description of the Related Art Conventionally, as a capacitance detection device, for example, one described in Patent Document 1 is known. This capacitance detection device is arranged between a reference capacitance, a detection capacitance (capacity to be measured) connected to the reference capacitance, a first switch for initializing the reference capacitance, and the reference capacitance and the detection capacitance. A second switch, a third switch for initializing the detection capacitance, and a control circuit are provided. After initializing the reference capacity by operating the first switch, the control circuit performs a plurality of switch operations including the operation of the second switch and the operation of the third switch. An intermediate potential is obtained, and the number of detections corresponding to the number of switch operations when the intermediate potential is lower than the reference potential is derived. This number of times of detection is hereinafter referred to as a count value. This count value is correlated to the capacitance of the detection capacitor, and the derivation of the count value detects the capacitance of the detection capacitor.

Japanese Patent No. 4356003

By the way, in Patent Document 1, the capacity of the detection capacitor is detected by deriving the count value. Therefore, since the capacitance for one count is the detection resolution, it is necessary to increase the number of switch operations in order to improve the detection accuracy. For example, the number of switch operations is on the order of tens of thousands. This increases the time required for capacitance sensing.

On the other hand, when the time required for capacitance detection increases, the effects of low-frequency noise superimposed on the power supply (first and second potential sources) related to capacitance detection and the increase in the fluctuation width of the power supply itself become noticeable. As a result, the detection accuracy may decrease. In other words, increasing the number of switch operations to improve detection accuracy may adversely lead to a decrease in detection accuracy.

SUMMARY OF THE INVENTION An object of the present invention is to provide a capacitance detection device capable of shortening the time required for detection without lowering the detection accuracy.

Means for solving the above problems and their effects will be described below.
1. A variable capacitance capacitor, an electrode constituting a target for capacitance detection, and a control circuit, wherein the control circuit operates when a voltage of a voltage application device is applied to the electrode via the variable capacitance capacitor. , an operation process for manipulating the capacitance of the variable capacitor so as to control the intermediate potential, which is the potential at the connection point between the variable capacitor and the electrode, to the reference potential; and a detection process of detecting the capacitance of the detection target based on the capacitance of the variable capacitor.

In the above configuration, by controlling the intermediate potential to the reference potential, the ratio between the capacitance to be detected and the capacitance of the variable capacitor can be controlled to a ratio corresponding to the reference potential. Therefore, the capacitance to be detected or a value approximating it can be grasped from the capacitance of the variable capacitor as the manipulated variable when controlling to the reference potential and the above ratio. Therefore, according to the detection process, the capacitance to be detected can be detected. Moreover, in general, the manipulation process of controlling the intermediate potential to the reference potential by manipulating the capacitance of the variable capacitor can be performed without making the number of switching operations on the order of tens of thousands. Therefore, in the above configuration, the time required to detect the capacitance to be detected can be shortened compared to the case where the capacitance is detected by deriving the count value described above.

2. A differential amplifier circuit is provided which receives the intermediate potential and the reference potential and outputs a voltage signal corresponding to the difference between them. 2. The electrostatic capacitance detection device according to 1 above, wherein in addition to the capacitance, the process detects the electrostatic capacitance of the detection target based on the output value of the differential amplifier circuit when controlled to the reference potential.

When the intermediate potential is controlled to be the reference potential, a deviation may occur between the intermediate potential and the reference potential depending on the minimum changeable unit of the capacitance of the variable capacitor. Therefore, when detecting the capacitance to be detected based only on the ratio of the capacitance of the variable capacitor and the capacitance of the detection target determined from the reference potential and the capacitance of the variable capacitor, The resolution of the capacitance to be detected depends on the minimum changeable unit of the capacitance of the variable capacitor. Therefore, in the above configuration, by detecting the capacitance to be detected in consideration of the output value of the differential amplifier circuit, the capacitance to be detected can be varied according to the amount of deviation between the reference potential and the intermediate potential. It is possible to specify even a minute level that cannot be grasped from only the capacitance of the capacitor and the above ratio.

3. The detection process includes two values of the capacitance of the variable capacitor when the intermediate potential is a pair of values sandwiching the reference potential and the difference between the intermediate potential and the reference potential is minimized. 3. The capacitance detection device according to the above 1 or 2, which is a process of detecting the capacitance of the detection target based on.

In the above configuration, the actual capacitance of the detection target is obtained from the two values of the capacitance of the variable capacitor and the ratio of the capacitance of the variable capacitor and the capacitance of the detection target, which are grasped from the reference potential. are determined. In other words, the capacitance to be detected is greater than or equal to the smaller one of the two capacitance values and less than or equal to the larger one. Therefore, according to the above configuration, the capacitance to be detected can be narrowed down.

4. In the detection process, an upper capacitance value, which is the capacitance to be detected which is grasped according to the capacitance of the variable capacitor and the reference potential when controlled to the reference potential, is amplified by the differential amplification. A process of detecting the capacitance of the detection target by correcting based on the output value of the circuit, and even if the output value of the differential amplifier circuit is the same, the above when the reference potential is controlled. 3. The capacitance detection device according to 2 above, wherein when the capacitance of the variable capacitor is large, the magnitude of the correction amount based on the output value is made larger than when the capacitance is small.

The magnitude of the difference between the intermediate potential and the reference potential at the stage where the difference between the intermediate potential and the reference potential is controlled to be as small as possible can be considered to be inversely proportional to the capacitance of the variable capacitor at that time. Therefore, even if the difference between the intermediate potential and the reference potential is the same, the difference between the capacitance of the detection target and the actual capacitance of the detection target that can be grasped only from the capacitance of the variable capacitor and the reference potential The magnitude varies depending on the capacitance of the variable capacitor. That is, even if the magnitude of the difference between the intermediate potential and the reference potential is the same, when the capacitance of the variable capacitor is large, the difference between the capacitance of the variable capacitor and the reference potential is greater than when the capacitance of the variable capacitor is small. The difference between the capacitance of the object to be detected that can be grasped only from the angle and the actual capacitance of the object to be detected becomes large. Therefore, in the above configuration, when the capacitance of the variable capacitor is large, the magnitude of the correction amount is made larger than when the capacitance is small. detection error can be suppressed.

5. 4. The above 2 to 4, wherein the control circuit repeatedly executes the detection process, and when the capacitance of the detection target detected by the detection process changes, outputs a signal indicating the change. Any one of the capacitance detection devices.

With the above configuration, when the capacitance to be detected changes, the effect can be notified to the outside.
6. a first discharge path for discharging the variable capacitor; a first discharge switch for opening and closing the first discharge path; a second discharge path for discharging the electrode; and a second discharge path for opening and closing the second discharge path. a discharge switch, wherein the control circuit executes a discharge process of discharging the variable capacitor and the electrode by closing the first discharge switch and the second discharge switch, and In the operation process, the first discharge switch and the second discharge switch are opened after the discharge process, and a voltage is applied to the electrode via the variable capacitor by the voltage application device. 6. The electrostatic capacitance detection device according to 5 above, wherein the detection process is repeatedly performed while the capacitance of the variable capacitor is fixed after once controlling the intermediate potential to the reference potential.

Each time the capacitance of the variable capacitor is manipulated by the manipulation process, the parasitic capacitance of each wire or the like may change. Therefore, when the operation process is executed prior to each execution of the detection process, even though the capacitance of the object to be detected does not actually change, the change in the parasitic capacitance causes the detection process to The detected capacitance may change. Therefore, in the above configuration, after controlling the intermediate potential to the reference potential, the detection process is repeatedly executed with the capacitance of the variable capacitor fixed, thereby reducing the parasitic capacitance caused by the manipulation of the capacitance of the variable capacitor. It is possible to prevent the change from being erroneously detected as the change in the capacitance to be detected.

7. A differential amplifier circuit is provided which receives the intermediate potential and the reference potential and outputs a voltage signal corresponding to the difference between the intermediate potential and the reference potential, and the output processing outputs a signal indicating that a predetermined object has approached the electrode. If the amount of change in the output value of the differential amplifier circuit in a sampling period shorter than the sampling period of the output value of the differential amplifier circuit for detecting is larger than a specified amount, the electrostatic capacitance detection device is abnormal. 7. The electrostatic capacitance detection device according to 6 above, including a process of outputting a signal to the effect that there is.

For example, if the electrode is in a conducting state with a certain resistance value to the ground, an abnormal leak current is generated, and the amount of change in the output value of the differential amplifier circuit in an extremely short sampling period becomes large. On the other hand, if there is no leakage current, the amount of change in the output value of the differential amplifier circuit in a very short sampling period is a very small amount, such as the influence of noise. Therefore, in the above configuration, when the amount of change in the output value of the differential amplifier circuit in a sampling period shorter than the sampling period of the output value of the differential amplifier circuit is larger than a specified amount, a signal indicating that there is an abnormality is output. By doing so, the abnormality can be notified to the outside.

8. The variable capacitor is a series connection of a plurality of capacitors and switches connected in parallel, and the capacitance is variable by on/off operation of the switch, and the plurality of series connections 8. The capacitance detection device according to any one of 1 to 7 above, wherein the capacitances of the corresponding capacitors are different from each other.

ADVANTAGE OF THE INVENTION This invention has the effect of being able to shorten the time required for detection further, without reducing detection accuracy.

1 is a circuit diagram showing the electrical configuration of a first embodiment of a capacitance detection device; FIG. The circuit diagram which shows the capacitor array about the electrostatic capacitance detection apparatus of the same embodiment. 5 is a graph for explaining how an estimated combined capacitance is calculated for the capacitance detection device of the embodiment; 4 is a flowchart showing how to derive a detected capacitance for the capacitance detection device of the same embodiment; The circuit diagram which shows the electrical structure about 2nd Embodiment. 4 is a flowchart showing the procedure of processing executed by the control circuit according to the embodiment; FIG. 4 is a diagram showing the relationship between upper capacity and lower capacity according to the embodiment; FIG. 4 is a diagram showing a detection capacitor according to the same embodiment and a ratio of a change in intermediate potential to a change in the detection capacitor; FIG. 11 is a flow chart showing the procedure of processing executed by a control circuit according to the third embodiment; FIG. 4 is a time chart showing an example of intermediate potential transition depending on the presence or absence of an abnormality;

<First Embodiment>
A first embodiment of the capacitance detection device will be described below.
As shown in FIG. 1, the electrostatic capacitance detection device includes a capacitor array 11, a detection capacitor 12 whose capacitance is to be detected, a first switch 13, a second switch 14, a third switch 15, and an amplifier. A differential amplifier circuit 16 as an AD converter, an AD converter circuit 17 as an AD converter, and a control circuit 18 .

The capacitor array 11 has a variable combined capacitance Cs. That is, as shown in FIG. 2, the capacitor array 11 is configured by connecting in parallel a plurality (for example, eight) of capacitors 21 each having a series-connected capacitor 22 and a switch 23 . The capacities of these multiple capacitors 22 are set to be different from each other. Specifically, when the capacitance of the capacitor 22 with the smallest capacitance is represented by C0, the capacitances C0, C1, C2, C3, C4, C5, C6, and C7 of all the capacitors 22 satisfy the following equation (1). is set to

Cn=C0×2̂n, n=0 to 7 (1)
In addition, the switch 23 connected to the capacitor 22 having the capacity Cn is turned on and off (when the potential difference between the electrodes is state that does not function as a capacitor) is switched. That is, the switch 23 is turned on when the control value bn is "1", and turned off when the control value bn is "0".

Therefore, the combined capacitance Cs of the capacitor array 11 is expressed by the following formula (2) according to the control value bn (n=0 to 7).
Cs=b0.C0+b1.C1+...+b7.C7...(2)
In other words, the combined capacitance Cs changes according to the control value bn (“1” or “0”) with the capacitance C0 as the minimum unit (LSB).

The capacitor array 11 is arranged so that the capacitances C0 to C7 of the capacitors 22 do not fluctuate, for example, even if the surrounding environment changes.
As shown in FIG. 1, the detection capacitor 12 has a capacitance including its own capacitance and a stray capacitance determined by the surrounding environment (hereinafter, the capacitance of the detection capacitor 12 may be indicated as "detection capacitance Cx"). have

The capacitor array 11 and the detection capacitor 12 are connected in series to a power supply (V1). That is, one end of the capacitor array 11 is electrically connected to the high-side potential V1 as a power supply, and the other end is electrically connected to one end of the detection capacitor 12 via the second switch 14 . The other end of the detection capacitor 12 is electrically connected to a low-side potential V2 (<V1) as a power supply. The low-side potential V2 is set, for example, to the same potential as the ground (=0).

The first switch 13 initializes the capacitor array 11 (discharges the charges accumulated in the capacitors). Specifically, the first switch 13 is connected between both terminals of the capacitor array 11 (the plurality of capacitors 21), that is, connected in parallel. Both terminals are connected and disconnected, respectively. More strictly, for example, when all the switches 23 of the plurality of capacitive sections 21 are in the ON state, the first switch 13 switches between both terminals of all the capacitors 22 of the plurality of capacitive sections 21 as it is switched to the ON state. Connect and initialize between them (discharge the charge accumulated in the capacitor). The second switch 14 is electrically connected between the capacitor array 11 and the detection capacitor 12, and connects and disconnects the capacitor array 11 and the detection capacitor 12 with switching to the ON state and the OFF state, respectively. The third switch 15 initializes the detection capacitor 12 (discharges the charge accumulated in the capacitor). Specifically, the third switch 15 is connected between both terminals of the detection capacitor 12, that is, connected in parallel, and is connected and connected between both terminals of the detection capacitor 12 with switching to the ON state and the OFF state, respectively. Cut off.

A connection point N1 between the capacitor array 11 and the detection capacitor 12 is connected to the positive input terminal + of the differential amplifier circuit 16 . A negative input terminal − of the differential amplifier circuit 16 is connected via an amplifier circuit 19 to a connection point N 2 of a pair of resistors R connected in series to a power source. The differential amplifier circuit 16 inputs the intermediate potential Vout, which is the potential at the connection point N1, and the reference potential Vref (=V1/2) obtained by dividing the power supply by a pair of resistors R, and generates a differential voltage ΔV (= Vout-Vref) is amplified and output.

It should be noted that the intermediate potential Vout is a potential obtained by dividing the capacitance of the power supply by the combined capacitance Cs of the capacitor array 11 and the detection capacitance Cx of the detection capacitor 12, and is expressed by the following equation (3).
Vout=V1/(1+Cx/Cs) (3)
That is, the intermediate potential Vout is inversely proportional to the ratio of the detected capacitance Cx to the combined capacitance Cs (=Cx/Cs).

The differential voltage ΔV is represented by the following formula (4).
ΔV=Vout−Vref=V1/(1+Cx/Cs)−V1/2 (4)
Therefore, when the combined capacitance Cs matches the detection capacitance Cx (Cx/Cs=1), the intermediate potential Vout matches the reference potential Vref and the differential voltage ΔV becomes zero.

The polarity of the differential voltage ΔV is negative when the detection capacitance Cx is larger than the combined capacitance Cs, and positive when the detection capacitance Cx is smaller than the combined capacitance Cs. Therefore, when changing the combined capacitance Cs of the capacitor array 11 according to the control value bn (n=0 to 7), the differential amplifier circuit 16 functions as a comparator for determining the magnitude relationship between the combined capacitance Cs and the detection capacitance Cx. may be viewed.

The AD conversion circuit 17 AD-converts the differential voltage ΔV, for example, which has a 10-bit sign and is amplified by the differential amplifier circuit 16 , and outputs the converted voltage to the control circuit 18 . As is clear from equation (4), when the deviation between the combined capacitance Cs and the detected capacitance Cx is small (Cx/Cs≈1), the difference voltage ΔV approximates zero, but the combined capacitance Cs and the detected capacitance Cx When the deviation is large, the differential voltage ΔV becomes a positive or negative number with a large absolute value.

Therefore, if the AD conversion minimum unit (LSB) of the AD conversion circuit 17 is constant, the differential amplifier circuit 16 is preferably configured so that the amplification factor can be changed according to the absolute value of the difference voltage ΔV. . In this case, when the absolute value of the differential voltage .DELTA.V exceeds a predetermined value, for example, when the combined capacitance Cs of the capacitor array 11 is changed according to the control value bn (n=0 to 7), the differential amplifier circuit 16 , the differential voltage ΔV is amplified with a relatively small amplification factor. On the other hand, differential amplifier circuit 16 amplifies differential voltage ΔV with a relatively large amplification factor when the absolute value of differential voltage ΔV is less than a predetermined value. As a result, the AD conversion circuit 17 can perform AD conversion in the minimum unit substantially changed according to the absolute value of the difference voltage ΔV.

Alternatively, when the absolute value of the differential voltage ΔV exceeds a predetermined value, such as when changing the combined capacitance Cs of the capacitor array 11 according to the control value bn (n=0 to 7), the AD conversion circuit 17 A constant digital value representing that fact may be output, and when the absolute value of the differential voltage ΔV is less than a predetermined value, a digital value representing the differential voltage ΔV may be output.

Alternatively, the AD conversion circuit 17 may be configured with multiple units or multiple channels so that the minimum unit (LSB) of AD conversion can be changed according to the absolute value of the differential voltage ΔV. In this case, when the absolute value of the differential voltage ΔV exceeds a predetermined value, for example, when the combined capacitance Cs of the capacitor array 11 is changed according to the control value bn (n=0 to 7), the AD conversion circuit 17 outputs a digital value AD-converted in a relatively large minimum unit. On the other hand, when the absolute value of the difference voltage ΔV is less than a predetermined value, the AD conversion circuit 17 outputs a digital value AD-converted in a relatively small minimum unit.

In any case, when the absolute value of the differential voltage ΔV is below a predetermined value, that is, when the intermediate potential Vout is close to the reference potential Vref, the AD conversion circuit 17 detects the intermediate potential Vout due to the change corresponding to the resolution of the combined capacitance Cs. A/D conversion can be performed in a minimum unit smaller than the voltage fluctuation of .

The control circuit 18 is mainly composed of, for example, an MCU (microcomputer), and controls the first switch 13, the second It drives and controls the switch 14 and the third switch 15 . Specifically, the control circuit 18 performs the following process A.

1. Both the first switch 13 and the third switch 15 are turned on, the second switch 14 is turned off, and the capacitor array 11 and the detection capacitor 12 are discharged by a short circuit between their terminals. That is, each of the capacitor array 11 and the detection capacitor 12 is initialized.

2. Both the first switch 13 and the third switch 15 are turned off, the second switch 14 is turned on, and the capacitor array 11 and the detection capacitor 12 are connected in series. Then, the intermediate potential Vout is generated at the connection point N1.

3. A differential voltage ΔV (=Vout−V1/2) amplified by the differential amplifier circuit 16 and AD-converted by the AD converter circuit 17 is inputted to detect the differential voltage ΔV.
That is, the control circuit 18 as the detection section 18a detects the differential voltage ΔV correlated with the intermediate potential Vout.

Further, the control circuit 18 as the switching control unit 18b sets a control value bn (n=0 to 7), and the plurality of capacitors 22 of the capacitor array 11 according to the control value bn (n=0 to 7). to selectively turn on and off the switches 23. At this time, as described above, the combined capacitance Cs of the capacitor array 11 changes according to the control value bn (n=0 to 7). Then, when the control circuit 18 changes the combined capacitance Cs of the capacitor array 11 according to the control value bn (n=0 to 7), the polarity of the differential voltage ΔV AD-converted by the AD conversion circuit 17 is determined. The obtained control value bn is stored in the internal memory.

That is, the control circuit 18 uses a so-called binary search technique to acquire the combined capacitance Cs that approximates the detection capacitance Cx of the detection capacitor 12 . Specifically, the control circuit 18 performs the following processing B.

1. The control value b7, which is the most significant bit of the control value bn of the capacitor array 11, is set to "1", and the control values b6 to b0, which are all other lower bits, are set to "0". That is, the set value is set to "1000_0000".

2. The difference voltage ΔV (=Vout−V1/2) is input according to the process A described above.
3. The control value b7 is determined to be "1" or "0" according to the polarity of the differential voltage .DELTA.V. Then, the determined value a of the control value b7 is stored in the built-in memory. That is, when the polarity of the differential voltage ΔV is negative, the combined capacitance Cs (=C7) is smaller than the detected capacitance Cx, so the determined value a of the control value b7 is set to "1". On the other hand, when the polarity of the differential voltage ΔV is positive, the combined capacitance Cs (=C7) is larger than the detected capacitance Cx, so the determined value a of the control value b7 is set to "0".

4. Similarly, the control value b6, which is the next bit, is set to "1", and the control values b5 to b0, which are all other lower bits, are set to "0". That is, the set value is set to "a100_0000".
5. The difference voltage ΔV (=Vout−V1/2) is input according to the process A described above.

6. The control value b6 is determined to be "1" or "0" depending on the polarity of the differential voltage .DELTA.V. Then, the determined value b of the control value b6 is stored in the built-in memory.
7. Repeat the processes of 4 to 6 in the same manner to determine the control values b5 to b0, which are the next bits, to be "1" or "0", and store the determined values c to h in the internal memory. do.

As described above, the control circuit 18 acquires the combined capacitance Cs (hereinafter, also referred to as “first combined capacitance Cs1”) represented by the set value “abcd_efgh”.
Cs1=a*C7+b*C6+...+h*C0...(5)
This first combined capacitance Cs1 is a combined capacitance Cs that is smaller than the detection capacitance Cx that is closest to the detection capacitance Cx. At the same time, the control circuit 18 adds the minimum capacitance C0 to the first combined capacitance Cs1 to obtain a combined capacitance Cs that is closest to the detected capacitance Cx and larger than the detected capacitance Cx (hereinafter referred to as “second combined capacitance Cs2”). ) is obtained.

Cs2=Cs1+C0 (6)
That is, the control circuit 18 as the acquisition unit 18c selects two adjacent combined capacitors Cs whose magnitude relationship between the intermediate potential Vout and the preset reference potential Vref (=V1/2) is reversed as the first combined capacitor Cs1 and the first combined capacitor Cs1. Obtained as the second combined capacitance Cs2.

Further, the control circuit 18 as the detection unit 18a matches the control values b7 to b0 with the set value "abcd_efgh" to match the combined capacitance Cs of the capacitor array 11 with the first combined capacitance Cs1, following the process A described above. A differential voltage ΔV (hereinafter also referred to as “first differential voltage ΔV1”) correlated with the intermediate potential Vout (hereinafter also referred to as “first intermediate potential Vout1”) at this time is detected. Similarly, the control circuit 18 as the detection unit 18a matches the control values b7 to b0 with the set value "abcd_efgh+0000_0001" to match the combined capacitance Cs of the capacitor array 11 with the second combined capacitance Cs2. Accordingly, a differential voltage ΔV (hereinafter also referred to as “second differential voltage ΔV2”) correlated with intermediate potential Vout (hereinafter also referred to as “second intermediate potential Vout2”) at this time is detected.

Then, the control circuit 18 as the calculation unit 18d calculates the estimated combined capacitance Cse of the capacitor array 11 when the intermediate potential Vout matches the reference potential Vref based on the first differential voltage ΔV1 and the second differential voltage ΔV2. .

That is, as shown in FIG. 3, approximating that the intermediate potential Vout is proportional to the combined capacitance Cs between the first combined capacitance Cs1 and the second combined capacitance Cs2, the first combined capacitance Cs1 and the estimated combined capacitance The following equation (7) holds when the slope between Cse and the slope between the estimated combined capacitance Cse and the second combined capacitance Cs2 match.

ΔV1/(Cse−Cs1)=ΔV2/(Cs2−Cse)
Cse=(.DELTA.V1.Cs2+.DELTA.V2.Cs1)/(.DELTA.V1+.DELTA.V2) (7)
The estimated combined capacitance Cse of the capacitor array 11 whose intermediate potential Vout matches the reference potential Vref matches the capacitance of the detection capacitor 12 as described above. The control circuit 18 as the derivation unit 18 e derives the estimated combined capacitance Cse at this time as the detection capacitance Cx of the detection capacitor 12 .

As is clear from equation (7), the estimated combined capacitance Cse is calculated using the differential voltage ΔV, so that the calculation is not hindered even if the intermediate potential Vout itself is not detected. Also, the differential voltage ΔV is treated as a dimensionless number by being present in both the numerator and the denominator. Therefore, even if the differential voltage ΔV is amplified with an arbitrary amplification factor by the differential amplifier circuit 16 or is AD-converted by the AD converter circuit 17, the calculation result of the estimated combined capacitance Cse is basically unchanged. . As described above, when the intermediate potential Vout is close to the reference potential Vref, the digital value of the differential voltage ΔV is represented by a minimum unit smaller than the voltage fluctuation of the intermediate potential Vout due to the change corresponding to the resolution of the combined capacitance Cs. Therefore, the detected capacitance Cx can be derived with higher accuracy than the resolution of the combined capacitance Cs.

Next, the manner in which the control circuit 18 derives the detection capacitance Cx will be generally described. This processing is repeatedly executed by, for example, a scheduled interrupt.
As shown in FIG. 4, when the process shifts to this routine, in step S1, the control circuit 18 changes the combined capacitance Cs of the capacitor array 11 by the above-described processes A and B, and changes the intermediate capacitance Cs accordingly. The potential Vout, more precisely, the differential voltage ΔV is detected.

Subsequently, in step S2, the control circuit 18 acquires one of the combined capacitances Cs around which the magnitude relationship between the intermediate potential Vout and the reference potential Vref is inverted as the first combined capacitance Cs1 and the second combined capacitance Cs2. .

Next, in step S3, the control circuit 18 controls the first intermediate potential Vout1 and the second intermediate potential Vout2, which are the intermediate potentials Vout when the combined capacitance Cs is the first combined capacitance Cs1 and the second combined capacitance Cs2, respectively. , the estimated combined capacitance Cse of the capacitor array 11 when the intermediate potential Vout matches the reference potential Vref is calculated based on the first differential voltage ΔV1 and the second differential voltage ΔV2.

Then, in step S4, the control circuit 18 derives the capacitance of the detection capacitor 12 as the detection capacitance Cx based on the estimated combined capacitance Cse, and terminates the process. That is, the control circuit 18 matches the detected capacitance Cx with the estimated combined capacitance Cse.

The action and effect of this embodiment will be described.
(1) In the present embodiment, the acquisition unit 18c acquires the first combined capacitance Cs1 and the second combined capacitance Cs2 that are closest to the capacitance of the capacitor array 11 when the intermediate potential Vout matches the reference potential Vref. Then, the calculation unit 18d calculates the estimated combined capacitance Cse based on the first intermediate potential Vout1 and the second intermediate potential Vout2. Then, the derivation unit 18e derives the detection capacitance Cx based on the fact that the intermediate potential Vout, which is the potential of the power supply capacitance divided by the estimated combined capacitance Cse and the capacitance of the detection capacitor 12, matches the reference potential Vref.

The combined capacitance Cs is changed to the first combined capacitance Cs1 or the second combined capacitance Cs2 by selectively switching the plurality of capacitors 22 to the ON state and the OFF state by the switching control unit 18b, that is, by changing the capacitance and comparing the potentials by binary search. can be rapidly converged to For example, the number of times the eight capacitors 22 are selectively switched on and off is on the order of a dozen times. Therefore, the time required to detect the capacitance of the detection capacitor 12 can be shortened. In addition, the detection capacitance Cx is derived so that the intermediate potential Vout, which is the potential of the capacitive voltage division of the power supply with the estimated combined capacitance Cse, matches the reference potential Vref. The capacitance of the detection capacitor 12 can be detected with higher precision than the capacitance C0.

(2) In the present embodiment, the detection unit 18a only needs to detect the voltage difference ΔV between the intermediate potential Vout and the reference potential Vref. , the high-resolution ADC, which is expensive and has a large circuit scale, is not required, so the cost can be reduced. Further, since the estimated combined capacitance Cse can be calculated based on the differential voltage ΔV between the intermediate potential Vout and the reference potential Vref, the calculation load can be further reduced.

(3) In the present embodiment, the difference voltage ΔV between the intermediate potential Vout and the reference potential Vref is amplified by the differential amplifier circuit 16, so that even if the difference voltage ΔV is minute, it is made more conspicuous. , and the SN ratio can be further improved. In particular, common-mode noise can be cut if the differential amplifier circuit 16 has fully differential characteristics. Further, if the amplification factor of the differential amplifier circuit 16 is changed according to the absolute value of the differential voltage ΔV, even if the AD conversion circuit 17 has a constant minimum unit of AD conversion (LSB), the minimum unit can be substantially reduced to can be changed. Therefore, the AD conversion circuit 17 having a simple configuration can be adopted, and the cost can be reduced.

(4) In the present embodiment, the difference voltage ΔV between the intermediate potential Vout and the reference potential Vref is AD-converted by the AD conversion circuit 17, so that the difference voltage ΔV can be handled as a digital value, and smoother operation can be performed. Arithmetic processing can be realized.

(5) In the present embodiment, the time required to detect the capacitance of the detection capacitor 12 can be shortened, so that the circuit stop time can be lengthened accordingly, and the power consumption of the entire device can be reduced. Alternatively, since the time required to detect the capacitance of the detection capacitor 12 can be further shortened, it is possible to reduce the influence of low-frequency noise superimposed on the power supply (high-side potential V1, etc.) and an increase in the fluctuation range of the power supply itself. Accuracy can be further improved.

(6) In this embodiment, the time required to detect the capacitance of the detection capacitor 12 can be further shortened, so that the number of detections within a certain period of time can be increased. Therefore, by performing filtering processing such as averaging the capacitance of the detection capacitor 12 detected within a certain period of time, the capacitance of the detection capacitor 12 can be detected with higher accuracy.

(7) In the present embodiment, since the capacitances Cn (n=0 to 7) of the plurality of capacitors 22 are in a power-of-two relationship, the binary search can find the first combined capacitance Cs1 and the second combined capacitance at the shortest time. Cs2 can be obtained.

<Second embodiment>
The second embodiment will be described below with reference to the drawings, focusing on differences from the first embodiment.

FIG. 5 shows a capacitance detection device 30 according to this embodiment. 5, members corresponding to members shown in FIG. 1 are denoted by the same reference numerals for convenience.
The capacitance detection device 30 according to the present embodiment is a proximity detection sensor that is mounted on a vehicle and detects that a person has approached a predetermined location of the vehicle. Specifically, for example, it is a sensor that detects when a person's foot touches the rear part of the vehicle, or when a person's hand traces the vicinity of the vehicle's slide door. When the proximity detection sensor detects that a predetermined part of a person, which is a target object, approaches, the opening/closing part is automatically opened by an electronic control unit (ECU) that controls the opening/closing of the opening/closing part of the vehicle. .

As shown in FIG. 5, a battery 40 is connected to the capacitance detection device 30, and the voltage of the battery 40 is stepped down by the regulator 31 to the high-side potential V1. Further, as shown in FIG. 5, an electrode 34 is connected via a filter circuit 32 to the connection point N1. The electrode 34 constitutes the detection capacitor 12, which is a virtual capacitor whose capacitance is to be detected, together with an external member of the capacitance detection device 30. FIG.

Further, as shown in FIG. 5, the differential amplifier circuit 16 includes an operational amplifier 16a, and the negative input terminal - of the operational amplifier 16a is connected to the connection point N1 via the resistor 16b and the amplifier circuit 19a. It is connected to the output terminal through the resistor 16c. Here, the amplifier circuit 19 a has the same specifications as the amplifier circuit 19 . A positive input terminal + of the operational amplifier 16a is grounded through a resistor 16d and connected to the amplifier circuit 19 through a resistor 16e.

In this embodiment, the resistors 16b and 16e have the same resistance value R1, and the resistors 16c and 16d have the same resistance value R2. In that case, the output of the differential amplifier circuit 16 is given by the following equation (8).

(R2/R1) (Vref-Vout) (8)
In this embodiment, the resistance values R1 and R2 are set such that (R2/R1) is "Vadin/(8*C0*Rref)". Here, the input voltage range Vadin of the AD conversion circuit 17 and the reference sensitivity ratio Rref are used. The reference sensitivity ratio Rref indicates the ratio of the amount of change in the intermediate potential Vout to the same amount of change when the detection capacitance Cx slightly changes when the combined capacitance Cs is the standard capacitance value CStyp. That is, when the above equation (3) is differentiated by the detection capacitance Cx, the following equation (9) is obtained.

[−V1/{1+(Cx/Cs)^2}]・(1/Cs) (9)
Here, a reference sensitivity ratio Rref is obtained by substituting the standard capacitance value CStyp for each of the combined capacitance Cs and the detection capacitance Cx. In this case, when the combined capacitance Cs determined by the binary search described above is equal to the standard capacitance value CStyp, if the output value of the differential amplifier circuit 16 changes by the input voltage range Vadin of the AD conversion circuit 17, the amount of change in the detected capacitance Cx is becomes "8·C0".

Note that the control circuit 18 according to the present embodiment is configured by a dedicated hardware circuit such as an ASIC (application specific integrated circuit). Incidentally, in this embodiment, it is assumed that the voltage of the battery 40 is stepped down by the regulator 31 and output to the control circuit 18 or the like by activating the above-described ECU. Also, the control circuit 18 is connected to the ECU described above via a communication line 50 .

FIG. 6 shows the procedure of processing executed by the control circuit 18 . The processing shown in FIG. 6 is repeatedly executed by the control circuit 18 at a predetermined cycle. Note that, hereinafter, the step number of each process is represented by a number prefixed with "S".

In the series of processes shown in FIG. 6, the control circuit 18 first determines whether or not the determination flag F is "1" (S10). The determination flag F is "1" when the control values b0 to b7 are determined by the binary search and the reference capacity control value CScnt corresponding to the control values b0 to b7 is determined, and "0" otherwise. becomes. The determination flag F is "0" at the time when the electrostatic capacitance detection device 30 is activated as the ECU is activated. That is, at that time, the reference capacity control value CScnt has been initialized.

When the determination flag F is "0" (S10: NO), the control circuit 18 executes a binary search process (S12), and determines the determined values a to h of the control values b0 to b7. A reference capacity control value CScnt is determined (S14). In other words, the intermediate potential Vout is feedback-controlled to the reference potential Vref, and the reference capacitance control value CScnt is determined based on the control values b0 to b7 when the intermediate potential Vout approaches the reference potential Vref as much as possible. The reference capacity control value CScnt has the most significant bit a and the least significant bit h.

The binary search process in this embodiment is basically the same as the processes 1 to 7 described above. Execute. That is, first, the control circuit 18 turns on both the first switch 13 and the third switch 15 and turns off the second switch 14 to discharge the capacitor array 11 and the electrode 34. With the switch 13 and the third switch 15 both turned off and the second switch 14 turned on, the capacitor array 11 and the electrode 34 are connected in series. Then, the control circuit 18 performs feedback control of the intermediate potential Vout to the reference potential Vref using the control value b7 of the most significant bit as a manipulated variable. Next, after executing the discharging process again, the control circuit 18 performs feedback control of the intermediate potential Vout to the reference potential Vref using the control value b6 as the manipulated variable while the capacitor array 11 and the electrode 34 are connected in series. Thereafter, the discharge process and the process of connecting the capacitor array 11 and the electrode 34 in series are repeated each time the manipulated variable is changed until the intermediate potential Vout is feedback-controlled to the reference potential Vref with the control value b0 as the manipulated variable.

Next, the control circuit 18 multiplies the reference capacitance control value CScnt by the capacitance weighting coefficient CScef to set the minimum capacitance C0 of the capacitor array 11 to 27 times the minimum unit of the detection capacitance Cx in this embodiment. Convert to a value (S16). This is because, in the present embodiment, the output of the AD conversion circuit 17 is 10 bits, and the gain setting of the differential amplifier circuit 16 expresses "8·C0" in 10 bits. That is, in the present embodiment, as shown in FIG. 7, 1/2 to the 7th power of "C0", which is the minimum unit of the AD conversion circuit 17, is set to b0, and twice that is set to b1. The least significant bit of the control value CScnt corresponds to b7. Therefore, the least significant bit of the reference capacitance control value CScnt is multiplied by the capacitance weighting factor CScef in order to set the value to 2 7 times the minimum unit of the AD conversion circuit 17 .

Returning to FIG. 6, the control circuit 18 calculates the sensitivity ratio CSratio by dividing the reference capacitance control value CScnt by the standard capacitance value CStyp (S18). Then, the control circuit 18 substitutes "1" for the determination flag F (S20).

On the other hand, when the control circuit 18 determines that the confirmation flag F is "1" (S10: YES), the first switch 13 and the third switch 15 are both turned on, and the second switch 14 is turned off. Then, the capacitor array 11 and the electrode 34 are discharged (S22). Next, the control circuit 18 turns off both the first switch 13 and the third switch 15 and turns on the second switch 14 to connect the capacitor array 11 and the electrode 34 in series (S24). Then, the control circuit 18 acquires the differential voltage ΔV, which is the output voltage of the differential amplifier circuit 16 (S26). Next, the control circuit 18 substitutes a value obtained by multiplying the sensitivity ratio CSratio by the difference voltage ΔV into the lower capacitance value Cxf (S28). This is a process of converting the differential voltage ΔV into a value when the combined capacitance Cs is the standard capacitance value CStyp. That is, as can be seen from the above equation (9), the amount of change in the intermediate potential Vout with respect to the change in the detection capacitance Cx changes depending on the magnitude of the detection capacitance Cx.

FIG. 8 shows the relationship between the sensitivity, which is the change in the intermediate potential Vout with respect to the change in the detection capacitance Cx, and the magnitude of the detection capacitance Cx based on the above equation (9). The relationship shown in FIG. 8 is based on the assumption that the combined capacitance Cs is equal to the detected capacitance Cx in the above equation (9). This reflects the state at the time when the process of S12 is completed. That is, when the process of S12 is completed, the combined capacitance Cs is as close as possible to the detected capacitance Cx, so they are considered to be equal to each other. As shown in FIG. 8, the amount of change in the intermediate potential Vout when the detection capacitance Cx changes after the processing of S12 is completed depends on the detection capacitance Cx when the processing of S12 is completed. This is because the amount of change in the intermediate potential Vout when the detection capacitance Cx changes after the processing of S12 is completed depends on the combined capacitance Cs when the processing of S12 is completed. Therefore, after the processing of S12 is completed, the change in the differential voltage ΔV due to the change of the detection capacitance Cx by a predetermined amount can be regarded as dependent on the combined capacitance Cs at the time when the processing of S12 is completed.

Therefore, in the present embodiment, the difference voltage ΔV is multiplied by the sensitivity ratio CSratio in order to convert the difference voltage ΔV into a value when the combined capacitance Cs is the standard capacitance value CStyp at the time when the processing of S12 is completed.

Then, the control circuit 18 substitutes the sum of the upper capacitance value Cxc and the lower capacitance value Cxf for the detected capacitance Cx(n) (S30). Here, the variable "n" indicates the current sampling value when the process of FIG. 6 is repeatedly executed.

Next, the control circuit 18 determines whether or not the value obtained by subtracting the detected capacitance Cx(n−1) calculated last time from the detected capacitance Cx(n) calculated this time is equal to or greater than a predetermined amount ΔCth (S32). . This process is a process of determining whether or not a specific part of a person has come close to the electrode 34 . In view of the fact that the detection capacitance Cx increases when the specific site approaches the electrode 34, the control circuit 18 determines that the specific site approaches when the detection capacitance Cx increases by a predetermined amount ΔCth or more (S32: YES), and sets the contact sensing flag to "1". ” is substituted (S34). On the other hand, when the amount of increase in the detection capacitance Cx is less than the predetermined amount ΔCth (S32: NO), the control circuit 18 substitutes "0" for the contact sensing flag (S36). Then, the control circuit 18 outputs the value of the contact sensing flag to the ECU via the communication line 50 (S38).

When the process of S38 is completed, the control circuit 18 updates the variable n (S40).
When the processes of S20 and S40 are completed, the control circuit 18 once terminates the series of processes shown in FIG.

As described above, according to the present embodiment, by correcting the differential voltage ΔV by the sensitivity ratio CSratio, even if the difference between the detected capacitance Cx and the combined capacitance Cs is the same, the combined capacitance at the time when the process of S16 is completed is It is possible to compensate for the difference in the differential voltage ΔV depending on Cs. That is, according to the above equation (9), when the combined capacitance Cs at the time when the processing of S12 is completed is large, the amount of change in the intermediate potential Vout when the detection capacitance Cx changes is greater than when it is small. , that is, the absolute value becomes smaller. On the other hand, the sensitivity ratio CSratio is a parameter that becomes larger when the combined capacitance Cs is large than when it is small. Therefore, even if the magnitude of the difference voltage ΔV is the same, when the combined capacitance Cs is large, the lower capacitance value Cxf, that is, the absolute value, is made larger than when it is small. Therefore, it is possible to suppress the variation in the amount of change in the intermediate potential Vout when the detection capacitance Cx changes due to the magnitude of the combined capacitance Cs at the time when the processing of S12 is completed. It can be calculated with high precision.

According to this embodiment described above, the following operational effects are obtained.
(8) Each time the switch 23 of the capacitor array 11 is operated, the parasitic capacitance of each wiring may change. Therefore, if the processing of S12 is executed prior to each update of the detection capacitance Cx, the capacitance to be detected does not actually change, but the change in the parasitic capacitance causes the change in S30 to occur. There is a possibility that the detected capacitance Cx calculated by the processing of . On the other hand, in the present embodiment, when the process of S12 is completed, the change in the parasitic capacitance is detected by monitoring the change in the detection capacitance Cx while the reference capacitance control value CScnt is fixed. False detection of changes can be suppressed.

(9) In the binary search process, each of the control values b0 to b7 is set as one manipulated variable, and each time the discharge process is executed again, the process of connecting the capacitor array 11 and the electrode 34 in series is executed. . As a result, even if a leak current occurs in the detection capacitor 12, the difference between the upper capacitance value Cxc and the actual capacitance of the detection capacitor 12 can be minimized.

<Third Embodiment>
The third embodiment will be described below with reference to the drawings, focusing on differences from the first embodiment.

FIG. 9 shows the procedure of processing executed by the control circuit 18 . The processing shown in FIG. 9 is repeatedly executed by the control circuit 18 at a predetermined cycle. In addition, in FIG. 9, the same step numbers are assigned to the processes corresponding to the processes shown in FIG. 6 for the sake of convenience.

In the series of processes shown in FIG. 9, when the process of S28 is completed, the control circuit 18 substitutes the differential voltage .DELTA.V obtained by the process of S26 into the differential voltage .DELTA.Va (S50). Then, the control circuit 18 waits until the predetermined time T1 elapses (S52: NO). Here, the predetermined time T1 is set to a time interval shorter than the repetition cycle of the processing in FIG. Then, when the predetermined time T1 has passed (S52: YES), the control circuit 18 acquires the differential voltage ΔV again (S54), substitutes it for the differential voltage ΔVb (S56), and proceeds to the process of S30.

Further, after completing the processes of S34 and S36, the control circuit 18 determines whether or not the absolute value of the difference between the differential voltage ΔVa and the differential voltage ΔVb is larger than the specified amount ΔVth (S58). Here, the prescribed amount ΔVth is defined as, for example, when the electrode 34 is electrically connected to the ground by a member such as a conductor having a low resistance value, an abnormal leak current is generated, and the function of the proximity detection sensor is fulfilled. is set according to the rate of change of the detection capacitance Cx in a situation in which it is impossible to If the control circuit 18 determines that the value is greater than the specified amount ΔVth (S58: YES), it substitutes "1" for the abnormality notification flag (S60). "0" is substituted for the flag (S62). Then, when the processes of S60 and S62 are completed, the control circuit 18 outputs the respective values of the contact detection flag and the abnormality notification flag to the ECU via the communication line 50 (S38a). Here, when the abnormality notification flag is "1", the ECU invalidates the value of the contact sensing flag, and executes a notification process or the like for notifying the outside that there is an abnormality.

The control circuit 18 executes the process of S40 when the process of S38a is completed. When the processes of S20 and S40 are completed, the control circuit 18 once terminates the series of processes shown in FIG.

FIG. 10 shows transition of the intermediate potential Vout after completion of the binary search process. Specifically, the solid line indicates an example of transition of the intermediate potential Vout in a normal state, and the dashed-dotted line indicates an example of transition of the intermediate potential Vout in an abnormal state. As shown in FIG. 10, the amount of decrease in the intermediate potential Vout after the elapse of the predetermined time T1 increases in the abnormal state. Therefore, the control circuit 18 detects a drop in the intermediate potential Vout in the abnormal state based on the magnitude (absolute value) of change speed of the difference voltage ΔV by the process of S58. By notifying the ECU of the occurrence of an abnormality in this case, it is possible to notify the occurrence of the abnormality via the ECU. In view of the fact that the change in the intermediate potential Vout in the event of an abnormality may be a decrease or an increase, the process of S58 monitors the rate of change of the differential voltage ΔV.

Incidentally, FIG. 10 shows the time t1 when the process of S24 is completed, the time t2 when the process of S26 is executed, and the time t3 when the process of S54 is executed. The two-dot chain line indicates the maximum velocity. In the present embodiment, the amount of decrease in the intermediate potential Vout of which the rate of decrease in the intermediate potential Vout is the largest among the determinations of normality from the completion of the process of S24 to the execution of the process of S54 is set by a specified amount ΔVth and Therefore, the time difference T0 between the time t2 when the process of S26 is executed and the time t1 when the process of S24 is completed is set as small as possible. However, if there is a limit to reducing the time difference T0, the specified amount ΔVth may be set with a margin corresponding to the time difference T0. However, when there is an abnormality due to leakage current, the closer to the completion of the process of S24, the faster the intermediate potential Vout decreases, so it is desirable that the time difference T0 be as short as possible.

<Correspondence relationship>
Correspondence relationships between the items in the above embodiment and the items described in the "Means for Solving the Problems" column are as follows. Below, the corresponding relationship is shown for each number of the solution described in the column of "means for solving the problem".

The [1,2,8] variable capacitors correspond to the capacitor array 11 . A voltage applying device corresponds to the regulator 31 . The operation process corresponds to the process of S1 in FIG. 4 and the process of S12 in FIGS. The detection processing corresponds to the processing of S2 to S4 in FIG. 4 and the processing of S26 to S30 in FIGS. [3] Corresponds to the processing in FIG. [4] Corresponds to the processing in FIGS. [5] The output process corresponds to the process of S38 in FIG. 6 and the process of S38a in FIG. [6] The first discharge path corresponds to the path connected in parallel to the capacitor array 11 and provided with the first switch 13 , and the first discharge switch corresponds to the first switch 13 . The second discharge path corresponds to the path with the third switch 15 and the second discharge switch corresponds to the third switch 15 . [7] ``Sampling cycle of the output value of the differential amplifier circuit for outputting a signal indicating that a predetermined object has approached the electrode'' corresponds to the cycle of the processing in FIG. "Sampling period shorter than the sampling period of the output value of the differential amplifier circuit for outputting a signal indicating that an object has approached the electrode" corresponds to the predetermined time T1.

This embodiment can be implemented with the following modifications. This embodiment and the following modified examples can be implemented in combination with each other within a technically consistent range.
- In the above-described embodiment, the capacitances Cn (n=0 to 7) of the plurality of capacitors 22 of the capacitor array 11 do not have to be in a power-of-two relationship as shown in equation (1). For example, the capacitances Cn (n=0 to 7) may have a relationship of powers of 3 or more natural numbers.

The number of capacitors 22 in the capacitor array 11 is arbitrary as long as the capacitors 22 have different capacities. Also, the capacities of the plurality of capacitors 22 may have a relationship of powers of two or more natural numbers, or may have a relationship of gradually increasing with a constant deviation.

- In the first embodiment, the AD conversion circuit 17 may be omitted and the capacitance of the detection capacitor 12 may be detected by analog processing.
- In the first embodiment, the differential amplifier circuit 16 may be omitted and the differential voltage ΔV may be AD-converted by the AD converter circuit 17 as it is.

- In the first embodiment, instead of the differential amplifier circuit 16, an amplifier that amplifies the intermediate potential Vout may be employed. Alternatively, the differential amplifier circuit 16 may be omitted and the intermediate potential Vout may be AD-converted by the AD conversion circuit 17 as it is. That is, the control circuit 18 as the detection section 18a may detect the intermediate potential Vout as it is.

- In the first embodiment, the first combined capacitor Cs1 and the second combined capacitor Cs2 may be any of the combined capacitors Cs in the vicinity where the magnitude relationship between the intermediate potential Vout and the reference potential Vref is inverted. .

- In the above embodiment, the low-side potential V2 does not have to be the same potential (=0) as the ground. In this case, for example, V1 in equation (4) should be changed to "V1-V2".
In the above-described embodiment, the reference potential Vref, which is the adjustment target value of the potential of the capacitive voltage division of the power supply, is not limited to "V1/2". good. Even if the reference potential Vref is arbitrarily changed, by calculating the potential of the capacitance division of the power supply by the combined capacitance Cs and the capacitance of the detection capacitor 12, that is, the estimated combined capacitance Cse in which the intermediate potential Vout matches the reference potential Vref, A detection capacitance Cx can be derived.

- In the above-described embodiment, the reference potential Vref may be set by DAC capacity voltage division or the like instead of resistance voltage division.
- In the first embodiment, there may be a plurality of detection capacitors 12 whose capacities are to be detected. When the detection capacitances Cx of the plurality of detection capacitors 12 are individually derived, a switch may be provided to selectively connect the capacitor array 11 or the like, which is a circuit configuration other than those, by time division or the like. Such individual derivation of the detection capacitances Cx of the plurality of detection capacitors 12 can be realized by shortening the time required to derive the detection capacitances Cx of the respective detection capacitors 12 .

- In the binary search process (S12) in FIGS. 6 and 9, it is not essential to execute the discharge process each time before determining the determined values of the control values b7 to b0. In other words, they may be equivalent to 1 to 7 in the first embodiment.

6 and 9, the sensitivity ratio CSratio is a value obtained by dividing the reference capacity control value CScnt by the standard capacity value CStyp, but it is not limited to this. For example, it may be a value obtained by dividing the upper capacitance value Cxc by the standard capacitance value CStyp.

The conversion process for converting the differential voltage ΔV into a value when the combined capacitance Cs is a predetermined value such as the standard capacitance value CStyp is not limited to the process of S28. For example, a process of multiplying the difference voltage ΔV by the reference capacitance control value CScnt may be performed. In addition, in order to make the magnitude of the detection capacitance Cx equivalent to that of the second embodiment and the third embodiment while performing such processing, the gain "R2/R1" of the differential amplifier circuit 16 is set to the second The value "1/CStyp" exemplified in the embodiment may be used.

- In the configuration illustrated in FIG. 5, the detected capacitance Cx may be calculated by the process illustrated in the first embodiment. At that time, a process of judging whether or not there is an abnormality based on the amount of change in the differential voltage ΔV when the predetermined time T1 has elapsed may be added.

- In the configuration illustrated in FIG. 5, the control circuit 18 may include a CPU and a ROM, and the CPU may execute a program stored in the ROM, thereby realizing the processes illustrated in FIGS. .

- In the configuration illustrated in FIG. 5, the filter circuit may be deleted.
- It is not essential to provide the regulator 31 in the configuration of FIG.
In the processing of S32, instead of determining whether or not the value obtained by subtracting the previous detected capacitance Cx(n-1) from the current detected capacitance Cx(n) is equal to or greater than a predetermined amount ΔCth, the current detected capacitance Cx It may be determined whether or not the absolute value of the value obtained by subtracting the previous detected capacitance Cx(n-1) from (n) is equal to or greater than a predetermined amount ΔCth.

In the process of FIG. 9, after the process of S56, the detected capacitance Cx is recalculated based on the differential voltage ΔVb, and in the process of S58, the value obtained by subtracting the detected capacitance Cx(n) from the recalculated detected capacitance Cx. may be determined whether or not the absolute value of is greater than or equal to a specified amount ΔCth1. This also determines whether or not there is an abnormality based on the amount of change in the difference voltage ΔV being larger than the specified amount.

- In the above embodiment, a comparator may be provided between the connection point N1 and the control circuit 18 to input the intermediate potential Vout and the reference potential Vref and determine the magnitude relationship between them. In the above-described binary search, a comparator may be used instead of the differential amplifier circuit 16 to determine the magnitude relationship between the intermediate potential Vout and the reference potential Vref, that is, the magnitude relationship between the combined capacitance Cs and the detection capacitance Cx. Even in this case, the control circuit 18 can determine the set value "abcd_efgh" of the capacitor array 11 based on the determination result of the comparator.

- Instead of the differential amplifier circuit 16, a comparator for comparing the intermediate potential Vout and the reference potential Vref may be provided. Even in this case, since the set value "abcd_efgh" of the capacitor array 11 can be determined, the detection capacitance Cx can be detected by assuming that the combined capacitance Cs of the capacitor array 11 is equal to the detection capacitance Cx.

As the processing for detecting the detection capacitance Cx based on the combined capacitance Cs when the intermediate potential Vout has two values sandwiching the reference potential Vref and the difference between the intermediate potential Vout and the reference potential Vref is the minimum, the first is not limited to the calculation of the detected capacitance Cx by linear interpolation based on the differential voltages ΔV1 and ΔV2 as exemplified in the embodiment. For example, the median of the two values may be regarded as the detected capacitance Cx. Note that this process can also be realized by providing a comparator for comparing the intermediate potential Vout and the reference potential Vref in place of the differential amplifier circuit 16 .

Technical ideas that can be grasped from the above embodiment and modifications will be described.
The electrostatic capacitance detection device includes a capacitor array having a plurality of parallel-connected capacitors with different capacities, wherein the combined capacitance is changed by selectively switching the on state and off state of the plurality of capacitors; A detection capacitor connected in series with an array, a switching control unit for selectively switching the plurality of capacitors to an on state and an off state, and an intermediate potential that is a potential of capacitive voltage division of a power supply by the combined capacitance and the capacitance of the detection capacitor. a detection unit that detects a potential; and an acquisition unit that acquires, as a first combined capacitance and a second combined capacitance, one of the combined capacitances near the point where the magnitude relationship between the intermediate potential and a preset reference potential is inverted. and the intermediate potential matches the reference potential based on the first intermediate potential and the second intermediate potential, which are the intermediate potentials when the combined capacitance is the first combined capacitance and the second combined capacitance, respectively. and a derivation unit for deriving the capacitance of the detection capacitor as a detection capacitance based on the estimated synthesis capacitance.

According to this configuration, the acquisition unit acquires the first combined capacitance and the second combined capacitance near the capacitance of the capacitor array when the intermediate potential matches the reference potential. The calculation unit calculates the estimated combined capacitance based on the first intermediate potential and the second intermediate potential. Then, the deriving unit derives the detection capacitance based on the fact that the intermediate potential, which is the potential of the capacitance voltage division of the power supply by the estimated combined capacitance and the capacitance of the detection capacitor, matches the reference potential.

The combined capacitance can be quickly converged to the first combined capacitance or the second combined capacitance by selectively switching the plurality of capacitors to the ON state and the OFF state by the switching control unit. Therefore, the time required to detect the capacitance of the detection capacitor can be shortened. In addition, the detection capacitance is derived so that the intermediate potential, which is the potential of the capacitive voltage division of the power supply with the estimated combined capacitance, matches the reference potential. The capacitance of the detection capacitor can be detected with high accuracy.

In the capacitance detection device, it is preferable that the detection section detects a differential voltage between the intermediate potential and the reference potential.
According to this configuration, since the detection section only needs to detect the differential voltage between the intermediate potential and the reference potential, the range required for detection can be reduced compared to the entire range of the intermediate potential, for example.

It is preferable that the capacitance detection device includes an amplifier that amplifies the differential voltage between the intermediate potential and the reference potential.
According to this configuration, the differential voltage between the intermediate potential and the reference potential is amplified by the amplifying section, so that even if the differential voltage is very small, it can be made more conspicuous.

It is preferable that the capacitance detection device includes an AD converter that AD-converts the differential voltage between the intermediate potential and the reference potential.
According to this configuration, the differential voltage between the intermediate potential and the reference potential can be handled as a digital value, and smoother arithmetic processing can be realized.

(B) In the above capacitance detection device,
The capacitance detection device, wherein the capacitances of the plurality of capacitors are in a power-of-two relationship.
According to this configuration, the first combined capacity and the second combined capacity can be acquired in the shortest time by binary search.

ΔV... Differential voltage, C0 to C7... Capacity, Cs... Combined capacity, Cx... Detection capacity, Cs1... First combined capacity, Cs2... Second combined capacity, Cse... Estimated combined capacity, Vref... Reference potential, Vout... Intermediate potential , Vout1... First intermediate potential, Vout2... Second intermediate potential, 11... Capacitor array, 12... Detection capacitor, 13... First switch, 14... Second switch, 15... Third switch, 16... Differential amplifier circuit ( Amplifier section), 17 AD conversion circuit (AD conversion section) 18 Control circuit 18a Detection section 18b Switching control section 18c Acquisition section 18d Calculation section 18e Derivation section 21 Capacitance section , 22...capacitor, 23...switch.

Claims (9)

a variable capacitor;
an electrode constituting a capacitance detection target;
a control circuit;
The control circuit is
When the voltage of the voltage application device is applied to the electrode via the variable capacitor, the variable capacitor is controlled to control an intermediate potential, which is a potential at a connection point between the variable capacitor and the electrode, to a reference potential. an operation process for manipulating the capacitance of the capacitor;
a detection process for detecting the capacitance of the detection target based on the capacitance of the variable capacitor when controlled to the reference potential,
a differential amplifier circuit that receives the intermediate potential and the reference potential and outputs a voltage signal corresponding to the difference between the intermediate potential and the reference potential;
In the detection process, the capacitance to be detected is based on the output value of the differential amplifier circuit when controlled to the reference potential, in addition to the capacitance of the variable capacitor when controlled to the reference potential. A process for detecting
In the detection process, an upper capacitance value, which is the capacitance to be detected which is grasped according to the capacitance of the variable capacitor and the reference potential when controlled to the reference potential, is amplified by the differential amplification. A process of detecting the capacitance of the detection target by correcting based on the output value of the circuit, and even if the output value of the differential amplifier circuit is the same, the above when the reference potential is controlled. A capacitance detection device that performs processing for increasing the magnitude of the correction amount based on the output value when the capacitance of the variable capacitor is large compared to when the capacitance is small. a variable capacitor;
an electrode constituting a capacitance detection target;
a control circuit;
The control circuit is
When the voltage of the voltage application device is applied to the electrode via the variable capacitor, the variable capacitor is controlled to control an intermediate potential, which is a potential at a connection point between the variable capacitor and the electrode, to a reference potential. an operation process for manipulating the capacitance of the capacitor;
a detection process for detecting the capacitance of the detection target based on the capacitance of the variable capacitor when controlled to the reference potential,
a differential amplifier circuit that receives the intermediate potential and the reference potential and outputs a voltage signal corresponding to the difference between the intermediate potential and the reference potential;
In the detection process, the capacitance to be detected is based on the output value of the differential amplifier circuit when controlled to the reference potential, in addition to the capacitance of the variable capacitor when controlled to the reference potential. is a process for detecting
The control circuit is
Repeating the detection process,
A capacitance detection device that executes an output process of outputting a signal indicating the change when the capacitance of the detection target detected by the detection process changes. In the detection process, an upper capacitance value, which is the capacitance to be detected which is grasped according to the capacitance of the variable capacitor and the reference potential when controlled to the reference potential, is amplified by the differential amplification. A process of detecting the capacitance of the detection target by correcting based on the output value of the circuit, and even if the output value of the differential amplifier circuit is the same, the above when the reference potential is controlled. 3. The electrostatic capacitance detection device according to claim 2, wherein the correction amount based on the output value is made larger when the capacitance of the variable capacitor is large than when it is small. a variable capacitor;
an electrode constituting a capacitance detection target;
a control circuit;
The control circuit is
When the voltage of the voltage application device is applied to the electrode via the variable capacitor, the variable capacitor is controlled to control an intermediate potential, which is a potential at a connection point between the variable capacitor and the electrode, to a reference potential. an operation process for manipulating the capacitance of the capacitor;
a detection process for detecting the capacitance of the detection target based on the capacitance of the variable capacitor when controlled to the reference potential,
The detection process includes two values of the capacitance of the variable capacitor when the intermediate potential is a pair of values sandwiching the reference potential and the difference between the intermediate potential and the reference potential is minimized. A process for detecting the capacitance of the detection target based on,
The control circuit is
Repeating the detection process,
A capacitance detection device that executes an output process of outputting a signal indicating the change when the capacitance of the detection target detected by the detection process changes. a first discharge path for discharging the variable capacitor;
a first discharge switch that opens and closes the first discharge path;
a second discharge path for discharging the electrode;
a second discharge switch that opens and closes the second discharge path,
The control circuit is
performing a discharge process of discharging the variable capacitor and the electrode by closing the first discharge switch and the second discharge switch;
In the detection process, the first discharge switch and the second discharge switch are opened after the discharge process, and a voltage is applied to the electrode via the variable capacitor by the voltage application device. run when
5. The electrostatic capacitance detection according to any one of claims 2 to 4, wherein the detection process is repeatedly executed with the capacitance of the variable capacitor fixed after the intermediate potential is once controlled to the reference potential. Device. a differential amplifier circuit that receives the intermediate potential and the reference potential and outputs a voltage signal corresponding to the difference between the intermediate potential and the reference potential;
The output processing changes the output value of the differential amplifier circuit in a sampling period shorter than the sampling period of the output value of the differential amplifier circuit for outputting a signal indicating that a predetermined object has approached the electrode. 6. The capacitance detection device according to claim 5 , further comprising a process of outputting a signal indicating that the capacitance detection device is abnormal when the magnitude of the amount is larger than a specified amount. The variable capacitor is formed by connecting a plurality of series-connected bodies of a capacitor and a switch in parallel, and the capacitance is made variable by turning on and off the switch,
The capacitance detection device according to any one of claims 1 to 6 , wherein the capacitances of corresponding capacitors of the plurality of series-connected bodies are different from each other. a capacitor array having a plurality of parallel-connected capacitors with different capacities, wherein the combined capacitance is changed by selectively switching the on-state and off-state of the plurality of capacitors;
a sensing capacitor connected in series with the capacitor array;
a switching control unit that selectively switches the plurality of capacitors between an on state and an off state;
a detection unit that detects an intermediate potential that is a potential of a power supply capacitive voltage divided by the combined capacitance and the capacitance of the detection capacitor;
an obtaining unit that obtains, as a first combined capacitance and a second combined capacitance, one of the combined capacitances near the point where the magnitude relationship between the intermediate potential and a preset reference potential is inverted;
When the intermediate potential matches the reference potential, based on the first intermediate potential and the second intermediate potential, which are the intermediate potentials when the combined capacitance is the first combined capacitor and the second combined capacitor, respectively. a computing unit that computes the estimated combined capacitance of the capacitor array;
and a derivation unit that derives the capacitance of the detection capacitor as a detection capacitance based on the estimated combined capacitance. The detection unit detects a first differential voltage between the first intermediate potential and the reference potential, and detects a second differential voltage between the second intermediate potential and the reference potential,
9. The capacitance according to claim 8, wherein the calculation unit calculates the estimated combined capacitance of the capacitor array when the intermediate potential matches the reference potential, based on the first differential voltage and the second differential voltage. detection device.

Images