JP2017118179A - A/d converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an A/D converter that is able to hinder A/D conversion error without lengthening an A/D conversion processing time.SOLUTION: A multiplexer 5 switches an analog input signal of each of a plurality of channels. A hold part 6 holds a voltage by inputting an analog input signal of a switched channel into a capacitor CHOLD for only a sampling time. An A/D conversion part 7 performs an A/D conversion process for a voltage of the hold part 6 standby-input for only a sampling time Ts, following the input of the analog input signal. A comparison reference setting part 9 sets a comparison reference Vrcomp for a range of reference voltage VREF and reference ground VGND. A sampling time setting part 11a calculates and sets a sampling time Ts for an A/D conversion process of the subsequent another channel according to the difference between the comparison reference Vrcomp and the A/D conversion output ADOUT of the present channel subjected to the A/D conversion process by the A/D conversion part 7.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an A / D conversion apparatus that performs A / D conversion processing on analog input signals of a plurality of channels.

  Conventionally, A / D converters have been developed for various purposes. Among them, a technique for continuously performing A / D conversion processing while switching input of analog input signals of a plurality of channels is provided (for example, see Patent Document 1). When this type of technique is used, the charging voltage of the sampling capacitor varies in accordance with the input voltage of each channel. For this reason, when the input voltages of the channels differ greatly, the charging / discharging voltage of the sampling capacitor changes greatly, and a long time is required for sampling (hereinafter referred to as sampling time). Further, when a sufficient sampling time cannot be secured, sampling is performed before the charging voltage of the sampling capacitor reaches an appropriate voltage, resulting in an increase in offset error.

  According to the technique described in Patent Document 1, a circuit for connecting the high potential side terminal of the sampling capacitor to GND is provided, and when the A / D conversion processing is completed, the hold voltage of the sample hold circuit is discharged, and the next analog input The signal is input to the sample hold circuit. As a result, it is possible to prevent the influence of the capacitance component remaining in the sample-and-hold circuit during AD conversion of the signal input from the immediately preceding channel. According to the technique described in Patent Document 2, the digital signal of the current channel is corrected based on the difference value from the digital signal of the immediately preceding channel.

JP 2009-188736 A JP 2013-201598 A

  For example, when the technique described in Patent Document 1 is used, a discharge circuit for discharging the sampling capacitor must be provided, so that the circuit configuration becomes complicated and the discharge circuit must be provided close to the sampling capacitor. Therefore, the leakage current may flow through the discharge circuit, and the leakage current may increase to a level that cannot be ignored, and it is difficult to employ this configuration.

  Assuming the worst case, a sampling time for changing the charging voltage of the sampling capacitor by the reference voltage must be set, and the sampling capacitor must be discharged every time A / D conversion processing is performed. , Processing time will be long. Further, for example, even if the technique described in Patent Document 2 is used, the processing time may be long.

  An object of the present invention is to provide an A / D conversion error suppressing device without lengthening the A / D conversion processing time in an apparatus for performing A / D conversion processing by switching analog input signals of a plurality of channels. It is to provide a D conversion device.

  According to the first aspect of the present invention, the switching unit switches analog input signals of a plurality of channels, and the holding unit receives an analog input signal of one channel among the plurality of channels switched by the switching unit, The sampling capacitor is charged by an analog input signal during the sampling time, and holds the voltage after the sampling time has elapsed. The A / D conversion unit is configured to be able to quantize a voltage within a range of a predetermined reference voltage, receives an analog input signal, and performs A / D conversion processing on the voltage of the holding unit that is standby input for the sampling time. The comparison reference setting unit sets a comparison reference in a range between the reference voltage and the reference ground. The sampling time setting unit determines the sampling time for the A / D conversion process for the next channel according to the difference between the A / D conversion output of the current channel that has been A / D converted by the A / D conversion unit and the comparison reference. Is calculated and set.

  According to the first aspect of the present invention, the sampling time setting unit determines the next time according to the difference between the A / D conversion output of the current channel subjected to A / D conversion processing by the A / D conversion unit and the comparison reference. Since the sampling time of the A / D conversion processing of other channels is calculated and set, it is not necessary to set the sampling time to a predetermined maximum time, and the A / D conversion processing can be performed in a short time.

1 is an electrical configuration diagram schematically illustrating an A / D conversion device according to a first embodiment. A diagram schematically showing an example of the contents of an analog input signal The figure which shows the relationship of the sampling time of the next channel according to the A / D conversion output of this channel Timing chart schematically showing the operation The figure which shows the relationship of the sampling time of the next channel according to the A / D conversion output of this channel in 2nd Embodiment. Electrical configuration diagram schematically showing an A / D converter in the third embodiment Timing chart schematically showing the operation Timing chart schematically showing operation in the fourth embodiment Timing chart schematically showing operation in the fifth embodiment Electrical configuration diagram schematically showing an A / D converter in the sixth embodiment Timing chart schematically showing the operation Timing chart schematically showing operation in the seventh embodiment

  Hereinafter, some embodiments of the A / D conversion device will be described with reference to the drawings. In each embodiment described below, configurations that perform the same or similar operations are denoted by the same or similar reference numerals, and description thereof is omitted as necessary.

(First embodiment)
1 to 4 are explanatory views of the first embodiment. The A / D conversion device 3 includes a plurality of channels CH. A, CH. B, CH. The C analog input signals VINA, VINB and VINC are input via an RC filter circuit 4 installed outside the A / D converter, and are subjected to A / D conversion processing. Hereinafter, a description will be given of a three-channel input form of “channel CH.A”, “channel CH.B”, and “channel CH.C”. Yes, that is, it is applicable if it has at least two or more channel inputs.

  The A / D conversion device 3 includes a multiplexer 5, a holding unit 6, an A / D conversion unit 7, an A / D conversion output storage unit 8, a comparison reference setting unit 9, a comparison unit 10, and an A / D control unit 11. Is provided. The A / D control unit 11 includes a memory serving as a non-transitional tangible recording medium such as a RAM, a ROM, and an EEPROM, and a method corresponding to the program by executing the program stored in the memory. Execute. The A / D control unit 11 may be configured by a logic circuit that operates logically. In this case, various controls can be performed using this hardware configuration.

  The RC filter circuit 4 is configured by connecting resistors RA, RB, RC and capacitors CA, CB, CC between the input terminal and the ground, respectively, and removes high frequency noise and is used for A / D conversion processing. The voltage is charged in the capacitors CA, CB and CC and held. The RC filter circuit 4 outputs the charging voltages of these capacitors CA, CB, and CC to the input terminal of the multiplexer 5 as A / D conversion input voltages VADA, VADB, and VADC. Of these, examples of values such as resistors RA, RB, RC and capacitors CA, CB, CC, CHOLD are given. The resistors RA, RB, RC are composed of, for example, about several hundred Ω to several tens of kΩ, and the capacitors CA, CB, CC have capacitance values of, for example, 0. It is configured to be about several μF. The capacitor CHOLD has a capacitance value of about several pF, for example.

  The multiplexer 5 can output the voltage Vn by switching the A / D conversion input voltages VADA, VADB, VADC under the control of the A / D control unit 11. The output voltage Vn of the multiplexer 5 is input to the holding unit 6. The holding unit 6 includes a control switch 12 and a sampling capacitor (hereinafter abbreviated as a capacitor) CHOLD. The control switch 12 is configured to be capable of on / off switching control by the A / D control unit 11, and when the control switch 12 is turned on by the A / D control unit 11, the output voltage Vn of the multiplexer 5 is input to the capacitor CHOLD. When the common connection node between the control switch 12 and the capacitor CHOLD is Nn, the capacitor CHOLD of the holding unit 6 holds the voltage VHOLD of the node Nn. The A / D control unit 11 includes a sampling time setting unit 11a. The sampling time setting unit 11a can set the sampling time, and the control switch 12 is turned off after the set sampling time has elapsed. Thus, the capacitor CHOLD is disconnected, and the voltage VHOLD at that time is input to the A / D converter 7.

  The A / D converter 7 is configured by a type such as a successive approximation type or a ΔΣ type. The A / D conversion unit 7 is configured to be able to quantize a voltage in a range between a predetermined reference voltage VREF (for example, 5 V) and a reference ground VGND (for example, 0 V), and is set by the sampling time setting unit 11a. A / D conversion processing is performed on the voltage VHOLD sampled and held after the lapse of the sampling time. The A / D conversion unit 7 stores the A / D conversion output ADOUT in the A / D conversion output storage unit 8 and outputs it to the comparison unit 10.

  On the other hand, the comparison reference setting unit 9 shows a block for setting the comparison reference Vrcomp. The comparison reference Vrcomp indicates a reference value determined in advance within the range of the reference voltage VREF and the reference ground VGND of the A / D converter 7. For example, the reference voltage VREF is 5 [V] and the reference ground VGND is 0. In the case of [V], for example, it is set to 2.5 [V] which is ½ within the range. The comparison reference Vrcomp is a value used by the sampling time setting unit 11a to set the sampling time.

  The comparison unit 10 compares the A / D conversion output ADOUT subjected to A / D conversion processing by the A / D conversion unit 7 with the comparison reference Vrcomp set by the comparison reference setting unit 9, and calculates a difference. The difference is output to the sampling time setting unit 11 a of the A / D control unit 11.

  Then, the sampling time setting unit 11a of the A / D control unit 11 calculates and sets the sampling time Ts of the A / D conversion process of the next channel according to the difference calculated by the comparison unit 10.

  FIGS. 2A to 2D show examples of the contents of the analog input signals VINA, VINB, and VINC. As shown in FIGS. 2 (a) to 2 (d), each channel CH. A, CH. B, CH. The analog input signals VIN, VINB, and VINC of C include (a) a monotonically increasing characteristic T1, (b) a monotonic decreasing characteristic T2, (c) a variation function (for example, a trigonometric function) characteristic T3, and (d) a predetermined voltage range. A characteristic that varies regularly or irregularly for each of the channels A, B, and C according to the time t, such as a characteristic T4 of a constant voltage that falls within the range, for example.

  The operation of the above configuration will be described. The RC filter circuit 4 connects each channel CH. To each of the capacitors CA, CB, CC according to a time constant determined in advance according to the resistors RA, RB, RC and the capacitors CA, CB, CC. A, CH. B, CH. C analog input signals VINA, VINB and VINC are charged. The charging voltages of the capacitors CA, CB, and CC are input to the multiplexer 5 of the A / D converter 3 as A / D conversion input voltages VADA, VADB, and VADC, respectively.

  The A / D control unit 11 receives the channel CH. When the capacitor CHOLD is charged with the A / D conversion input voltage VADA of A, the channel CH. The multiplexer 5 is switched so as to connect between the A / D conversion input terminal and the output terminal of the A and the channel CH. B, CH. The multiplexer 5 is controlled to switch between the A / D conversion input terminal and the output terminal of C. That is, the multiplexer 5 is connected to the channel CH. When the input is switched to A and the A / D conversion input voltage VADA of the channel A is charged to the capacitor CHOLD, the RC filter circuit 4 is connected to the channel CH. B and CH. The C analog input signals VINB and VINC can be charged independently while being RC filtered by the resistors RB and RC and the capacitors CB and CC.

  Thereafter, the A / D control unit 11 performs channel CH. When the input is switched to B and the capacitor CHOLD is charged with the A / D conversion input voltage VADB of the channel B, the channel CH. B. The multiplexer 5 is controlled to switch between the A / D conversion input terminal and the output terminal of B, and the channel CH. A, CH. The multiplexer 5 is controlled to switch between the A / D conversion input terminal and the output terminal of C.

  At this time, the RC filter circuit 4 is connected to the channel CH. A, CH. C analog input signals VINA and VINC are independently charged while being RC filtered by resistors RA and RC and capacitors CA and CC. As a result, the analog input signals VINA, VINB, and VINC of one of the plurality of channels are charged to and discharged from the capacitor CHOLD, and the A / D conversion input voltages VADA, VADB, and VADC of the plurality of channels are capacitors CA, CB, and CC. Can be charged and discharged.

  As shown in FIGS. 2A to 2D, a plurality of channels CH. A, CH. B, CH. The C analog input signals VINA, VINB, and VINC exhibit independent time-varying characteristics. For this reason, for example, the A / D conversion device 3 is connected to the channel CH. A → B → A → B →... Or CH. When the A / D conversion process is switched in the order of A → B → C → A →. A, CH. B, CH. The sampling voltage of C may be greatly different, or conversely, may be approximately the same voltage. Therefore, the present embodiment is characterized in that the sampling time setting unit 11a calculates and sets the sampling time of another channel next time in accordance with the difference between the A / D conversion output and the comparison reference.

  FIG. 3 shows an example of the relationship of the sampling time Ts of the next channel corresponding to the A / D conversion output ADOUT of the current channel. As shown in FIG. 3, the comparison reference Vrcomp is set between the reference voltage VREF and the reference ground VGND.

  The sampling time setting unit 11a sets the next sampling time according to the difference between the A / D conversion output ADOUT of the current channel and the comparison reference Vrcomp. For example, the A / D conversion output ADOUT of the current channel is set as the comparison reference. When it matches Vrcomp, the sampling time Ts of the next channel is set to the minimum value Tsmin.

  In the example shown in FIG. 3, when the A / D conversion output ADOUT of the current channel is higher than the comparison reference Vrcomp, the sampling time setting unit 11a linearly sets the sampling time Ts between the comparison reference Vrcomp and the reference voltage VREF. Set a longer time. This linearity is expressed by the following equation (1) when the A / D conversion output of the current channel is ADOUT and the sampling time of the next channel is Ts.

Ts = K1 + ADOUT × (Tsmax−Tsmin) / (VREF−Vrcomp) (1)
However, K1 = Tsmin−Vrcomp × (Tsmax−Tsmin) / (VREF−Vrcomp).
When the A / D conversion output of the current channel is lower than the comparison reference Vrcomp, the sampling time setting unit 11a linearly sets the sampling time between the comparison reference Vrcomp and the reference ground VGND. This linearity is expressed by the following equation (2).

Ts = K2 + ADOUT × (Tsmin−Tsmax) / (Vrcomp−VGND) (2)
However, K2 = Tsmin−Vrcomp × (Tsmin−Tsmax) / (Vrcomp−VGND).
As shown in FIG. 3, it is desirable that the sampling time setting unit 11a sets the sampling time Ts longer as the difference between the A / D conversion output of the current channel and the comparison reference Vrcomp increases. At this time, as shown in FIG. 3, for example, it may be calculated and set so as to change linearly, but for example, it may be calculated and set so as to change nonlinearly using a quadratic function or the like. . Note that this calculation and setting method is not limited to the above-described formulas (1) and (2), and formulas obtained by modifying these formulas (1) and (2) may be applied. Can be applied to various forms.

  When the comparison unit 10 compares the A / D conversion output ADOUT of the current channel with the comparison reference Vrcomp to calculate the difference, the sampling time setting unit 11a determines that the current A / D conversion output ADOUT is the reference ground VGND. Alternatively, when it is determined that it corresponds to the reference voltage VREF, it is desirable to set the next sampling time Ts to a predetermined maximum value Tsmax. The sampling time Ts at this time is not limited to the maximum value Tsmax.

  FIG. 4 schematically shows the operation of the main part of the present embodiment in a timing chart. The example shown in FIG. 4 includes, for example, channel CH. The analog input signal VINB of A has a constant voltage value V1, and the channel CH. An example in which the analog input signal VINB of B is a constant voltage value V2 is shown. In FIG. 4, the A / D control unit 11 controls the control switch 12 to be off and the channel CH. In the state where the A / D conversion input voltage VADA of A is charged in the capacitor CHOLD, the A / D conversion unit 7 samples and holds the voltage VHOLD and actually performs the A / D conversion processing.

  In FIG. 4, the time TDA is the channel CH. A shows the time for analog / digital conversion and quantization of the sampling voltage VHOLD of A, and the time TOA is the channel CH. It shows the time to offset the error of the lower bit (for example, LSB) of the conversion result of A and output it as an A / D conversion output to the comparison unit 10 or to store it in the A / D conversion output storage unit 8 .

  At time TSB, the multiplexer 5 uses the channel CH. A to channel CH. It shows the time for switching to the B analog input signal VINB and charging and discharging the voltage VHOLD to and from the capacitor CHOLD. The time TDB is the channel CH. B shows the time for analog / digital conversion and quantization of the sampling voltage VHOLD of B, and the time TOB is the channel CH. It shows the time to offset the error of the B conversion result and output it as an A / D conversion output to the comparison unit 10 or to store it in the A / D conversion output storage unit 8. Also, at time TSC, the multiplexer 5 uses the channel CH. B analog input signal VINB to CH. The time for switching to the analog input signal VINC of C and charging and discharging the voltage VHOLD to the capacitor CHOLD is shown.

  Now, at the time TDA, the A / D converter 7 performs the channel CH. Analog / digital conversion processing is performed for A, but this channel CH. When A / D conversion output of A is performed, the A / D conversion output is simultaneously input to the comparison unit 10. The comparison unit 10 compares the comparison reference Vrcomp set by the comparison reference setting unit 9 with the A / D conversion output ADOUT, calculates a difference, and outputs the difference calculation result to the A / D control unit 11. The A / D control unit 11 sets the sampling time Ts1 by the sampling time setting unit 11a. For example, in the case of the example shown in FIG. 4, when the voltage value V1 is the maximum value (for example, 5 V) and corresponds to the reference voltage VREF shown in FIG. 3, the maximum value Tsmax of the sampling time is set to the sampling time Ts1.

  Sampling time setting unit 11a uses channel CH. When the sampling time Ts1 of B is calculated and set, the calculation processing of the sampling time Ts1 ends and the channel CH. Until the sampling time Ts1 of B is determined, the channel CH. The B A / D conversion sequence is not started. As a result, the channel CH. In the state where the sampling time Ts1 of B is not defined, the next A / D conversion sequence is not started.

  Next, the A / D control unit 11 connects the multiplexer 5 to the channel CH. B is switched to the input of the A / D conversion input voltage VADB of B, and the control switch 12 is turned on, whereby the capacitor CHOLD is set to the set channel CH. The standby input is performed for the sampling time Ts1 of B.

  At this time, the capacitor CHOLD is charged or discharged from the voltage value V1 to the voltage value V2 over the sampling time Ts1. In the example of FIG. 4, since the voltage value V1> the voltage value V2, the voltage VHOLD is set to the next channel CH. It is close to the analog input signal VINB of B. At this time, as shown in FIG. 3, the apparatus waits for a predetermined sampling time Ts1, so that it is possible to reduce offset errors that are likely to occur during sampling as much as possible. In addition, the sampling time Ts1 is not required longer than necessary.

  At the time when the sampling time Ts1 has elapsed, the A / D control unit 11 controls the control switch 12 to turn off and instructs the A / D conversion unit 7 to perform an A / D conversion command. As a result, the A / D converter 7 samples and holds the sampling voltage VHOLD, and performs A / D conversion processing at time TDB. Then, the A / D conversion unit 7 outputs the A / D conversion output ADOUT in which the error is corrected at the time TOB to the comparison unit 10 and the A / D conversion output storage unit 8.

  The subsequent processing is the same as described above, but the comparison unit 10 compares the comparison reference Vrcomp set by the comparison reference setting unit 9 with the A / D conversion output ADOUT to calculate a difference, and calculates the difference. The result is output to the A / D control unit 11. Thereafter, the sampling time setting unit 11a performs the next channel CH. The C sampling time Ts2 is processed.

  Next, the A / D control unit 11 connects the multiplexer 5 to the channel CH. C is switched to the input of the A / D conversion input voltage VADC, and the control switch 12 is turned on to set the channel CH. Wait for C sampling time Ts2. At this time, the capacitor CHOLD is charged or discharged from the voltage value V2 over the sampling time Ts2. Subsequent processing will be omitted because it will be repeated.

  According to the present embodiment, the sampling time setting unit 11a uses the current channel CH. A / D conversion output ADOUT of A and the other channel CH. The sampling time Ts1 for B A / D conversion processing was calculated and set. As a result, the offset error can be reduced as much as possible without adding an internal circuit. Moreover, the sampling time Ts1 does not become longer than necessary. As a result, A / D conversion processing can be performed while suppressing A / D conversion errors as much as possible without lengthening the A / D conversion processing time.

  The channel CH. As the difference between the A / D conversion output ADOUT of A and the comparison reference Vrcomp increases, the next channel CH. Since the B sampling time is set to be long, an appropriate sampling time can be set according to the difference between the A / D conversion output ADOUT and the comparison reference Vrcomp. The channel CH. It is not necessary to lengthen the sampling time Ts as the difference between the A / D conversion output ADOUT of A and the comparison reference Vrcomp increases, and the sampling time Ts may be set to a constant value within a certain section, as will be described later.

  The channel CH. When the A / D conversion output ADOUT of A is the reference voltage VREF or the reference ground VGND of the A / D conversion unit 7, the sampling time setting unit 11a desirably sets the sampling time Ts to a predetermined maximum value Tsmax. In this case, the sampling capacitor CHOLD can be sufficiently charged and discharged, and the offset error can be reduced.

  This channel CH. After the A / D conversion output ADOUT of A is output, the sampling time setting unit 11a determines whether the next channel CH.1 is in accordance with the difference between the A / D conversion output ADOUT and the comparison reference Vrcomp. B sampling time Ts1 is set, and then the multiplexer 5 is connected to the channel CH. B is switched to the A / D conversion input voltage VADB, and the A / D control unit 11 turns on the control switch 12 of the holding unit 6, and then the A / D conversion unit 7 controls the next channel CH. A / D conversion processing of B is performed. Therefore, A / D conversion processing can be performed in order along the A / D conversion sequence, and the next channel CH. It is possible to prevent the B A / D conversion process from starting.

  According to the present embodiment, the sampling time setting unit 11a performs the A / D conversion processing of the current channel CH. A / D conversion output ADOUT of A and the other channel CH. Since the sampling time Ts for B A / D conversion processing is calculated and set, it is not necessary to set the sampling time Ts to a predetermined maximum time, and the A / D conversion processing can be performed in a short time.

  When the sampling time setting unit 11a sets the sampling time Ts longer as the difference between the A / D conversion output ADOUT and the comparison reference Vrcomp is larger, a more appropriate sampling time Ts can be set. The offset error can be reduced.

  Since the sampling time setting unit 11a sets the sampling time Ts to a predetermined maximum value Tsmax when the A / D conversion output ADOUT is the reference voltage VREF or the reference ground VGND of the A / D conversion unit 7, the sampling time Ts is calculated. Save time.

  After the sampling time setting unit 11a sets the next sampling time Ts1 according to the difference between the A / D conversion output ADOUT and the comparison reference Vrcomp, the multiplexer 5 switching processing, the voltage charging / discharging processing by the holding unit 6, A / D Since the A / D conversion process is performed by the conversion unit 7, the A / D conversion process can be performed in order along the A / D conversion sequence, and the next channel is determined without the sampling time Ts1 being determined. CH. It is possible to prevent the B A / D conversion process from starting.

  The sampling time setting unit 11a may perform calculation processing of the sampling time Ts in parallel with the calculation processing of the A / D conversion output ADOUT by the A / D conversion unit 7. In this case, since processing can be performed in parallel, processing time can be reduced.

(Second Embodiment)
FIG. 5 shows an example of the relationship of the sampling time Ts of the next channel corresponding to the A / D conversion output ADOUT of the current channel instead of FIG. The comparison reference setting unit 9 sets comparison references Vrcomp1, Vrcomp2, Vrcomp3, and Vrcomp4 shown in FIG. The comparison references Vrcomp1, Vrcomp2, Vrcomp3 and Vrcomp4 are set between the reference voltage VREF and the reference ground VGND. At this time, the comparison references Vrcomp1, Vrcomp2, Vrcomp3, and Vrcomp4 are set so as to satisfy the relationship of VGND <Vrcomp1 <Vrcomp2 <Vrcomp3 <Vrcomp4 <VREF.

  At this time, as in the first embodiment, the sampling time setting unit 11a responds to the difference between the A / D conversion output ADOUT of the current channel calculated by the comparison unit 10 and the comparison references Vrcomp1, Vrcomp2, Vrcomp3, and Vrcomp4. The next sampling time Ts is set. That is, it is determined whether the A / D conversion output ADOUT of the current channel falls within any section defined by these comparison references Vrcomp1, Vrcomp2, Vrcomp3, and Vrcomp4. At this time, for example, when the A / D conversion output ADOUT of the current channel is within the range of the comparison reference Vrcomp2 and the comparison reference Vrcomp3, the sampling time Ts is set to the minimum value Tsmin. The sampling time Ts at this time is not limited to the minimum value Tsmin.

  The sampling time setting unit 11a compares the A / D conversion output ADOUT of the current channel with the comparison references Vrcomp1, Vrcomp2, Vrcomp3, and Vrcomp4 by the comparison unit 10 to calculate the difference. When it is determined that the converted output ADOUT corresponds to the reference voltage VREF or the reference ground VGND, it is desirable to set the next sampling time Ts to a predetermined maximum value Tsmax. The sampling time Ts at this time is not limited to the maximum value Tsmax.

  As shown in FIG. 5, when the A / D conversion output ADOUT of the current channel is not less than the reference ground VGND and not more than Vrcomp1, the sampling time setting unit 11a sets the maximum value Tsmax as the next sampling time Ts. When the A / D conversion output ADOUT of the current channel is not less than the comparison reference Vrcomp1 and not more than Vrcomp2, the sampling time setting unit 11a sets a predetermined sampling time Tsa between the maximum value Tsmax and the minimum value Tsmin. Set as the next sampling time. When the A / D conversion output ADOUT of the current channel is not less than the comparison reference Vrcomp2 and not more than Vrcomp3, the sampling time setting unit 11a sets the minimum value Tsmin as the next sampling time Ts. When the A / D conversion output ADOUT of the current channel is not less than the comparison reference Vrcomp3 and not more than Vrcomp4, the sampling time setting unit 11a sets a predetermined sampling time Tsa between the maximum value Tsmax and the minimum value Tsmin. Set as the next sampling time Ts.

  In the example shown in FIG. 5, the sampling time Tsa when the A / D conversion output ADOUT is between the comparison references Vrcomp1 and Vrcomp2, and the A / D conversion output ADOUT is between the comparison references Vrcomp3 and Vrcomp4. The sampling time Tsa is set to the same value, but may be different. In addition, when the comparison unit 10 determines that the A / D conversion output ADOUT of the current channel matches the comparison references Vrcomp1, Vrcomp2, Vrcomp3, and Vrcomp4, the sampling time setting unit 11a selects any sampling in the section across the boundary. The time Ts may be set.

  In this way, the sampling time setting unit 11a is, for example, the current channel CH. In response to the A / D conversion output ADOUT of A, the next channel CH. When setting the sampling time Ts1 for B, as shown in FIG. 5, constant sampling times Tsmin, Tsa, and Tsmax that are discretely set in advance may be set.

  According to the present embodiment, a plurality of comparison references Vrcomp1, Vrcomp2, Vrcomp3, and Vrcomp4 set by the comparison reference setting unit 9 are provided, and the sampling time setting unit 11a includes VGND to Vrcomp1, Vrcomp1 to Vrcomp2, Vrcomp2 to Vrcomp3, and Vrcomp3. .., Vrcomp4, and Vrcomp4 to VREF, when entering any one of three or more sections, a predetermined sampling time Tsmin, Tsa, Tsmax set in advance for each of the sections is set. I made it. As a result, the sampling time setting unit 11a only needs to perform processing for selectively setting any one of the plurality of sampling times Tsmin, Tsa, and Tsmax according to the condition determination processing. For example, FIG. 4 of the first embodiment. Compared to the case of having a linearly changing characteristic as shown in FIG. 5, the time for calculating the sampling time Ts is not required. Thereby, the sampling time Ts can be set quickly. In addition, although the form which determines which A / D conversion output ADOUT is contained in the some area of 3 or more was shown, you may apply the form which determines which of the two areas is contained.

  According to the present embodiment, the comparison reference setting unit 9 sets the comparison reference Vrcomp between the reference voltage VREF and the reference ground VGND, so that the range defining the current A / D conversion output ADOUT is divided into a plurality of sections. When the sampling time setting unit 11a determines that the A / D conversion output ADOUT is in any of the plurality of sections, the sampling time setting unit 11a is set to a predetermined sampling time Tsmax predetermined for each of the plurality of sections. , Tsa, and Tsmin are set, it is only necessary to selectively set certain sampling times Tsmax, Tsa, and Tsmin in accordance with the condition determination process, and the time for calculating the sampling time Ts can be reduced.

(Third embodiment)
6 and 7 show additional explanatory views of the third embodiment. Parts that are the same as or similar to those in the previous embodiment are given the same or similar reference numerals, and descriptions thereof are omitted. The A / D conversion device 203 includes an A / D control unit 211. The A / D control unit 211 includes a sampling time storage unit 11b in addition to the sampling time setting unit 11a. The sampling time storage unit 11b is configured by a memory such as a recording register or a RAM, for example. The sampling time storage unit 11b may be provided outside the A / D control unit 211. Since other configurations are the same as those of the first embodiment, description thereof is omitted.

  The operation of the above configuration will be described with reference to the timing chart of FIG. As shown in FIG. 7, the sampling time setting unit 11a of the A / D control unit 211 includes the channel CH. A to CH. At the time of the first A / D conversion process up to B, for example, the sampling time Ts1 is calculated and set using the method described in the first or second embodiment. At this time, the sampling time storage unit 11b stores the sampling time Ts1. In the present embodiment, the sampling time storage unit 11b is used as an initial sampling time storage unit.

  Thereafter, channel CH. A channel CH. When the analog input signal VINC such as C is A / D converted, the sampling time is calculated and set in the first A / D conversion process, and the sampling time storage unit 11b stores the sampling time. That is, the sampling time storage unit 11b stores each channel CH. A, CH. B, CH. The first sampling time Ts1 is stored for each C.

  Thereafter, the channel CH. When A / D conversion processing is performed on the B analog input signal VINB, the sampling time setting unit 11a uses the sampling time Ts1 stored in the sampling time storage unit 11b. At this time, it is desirable to use the sampling time Ts1 stored in the sampling time storage unit 11b as it is. Thereby, at the time of the second and subsequent conversion processing, the sampling time setting unit 11a can set using the sampling time Ts1 stored in the sampling time storage unit 11b, and the calculation processing of the second and subsequent sampling times Ts1 is omitted. it can.

  According to the present embodiment, since the sampling time setting unit 11a sets using the sampling time Ts1 stored in the sampling time storage unit 11b at the first processing after the second time of the same channel, the second and subsequent samplings are performed. The calculation process of time Ts1 can be omitted.

(Fourth embodiment)
FIG. 8 shows an additional explanatory diagram of the fourth embodiment. The same or similar parts as those in the third embodiment are denoted by the same or similar reference numerals, and the description thereof is omitted. FIG. 8 shows a timing chart instead of FIG. At time TDA in FIG. 8, the A / D conversion unit 7 performs channel CH. When A / D conversion processing of A is performed and the sampling time setting unit 11a of the A / D control unit 211 calculates and sets the sampling time Ts1 at the time TOA in FIG. 8, this sampling time Ts1 is applied to the time TSB. . At this time, the sampling time storage unit 11b of the A / D control unit 211 stores the first sampling time Ts1.

  Then, at time TDB in FIG. A / D conversion processing of B is performed, error processing is performed at time TOB, and A / D conversion output is performed. In such a flow, channel CH. A, CH. B, CH. The A / D conversion process of C is performed. During this process, the sampling time storage unit 11b of the A / D control unit 211 stores each channel CH. A, CH. B, CH. The initial sampling time Ts1 of C is stored for each channel.

  The A / D conversion unit 7 receives the same channel CH. Stored in the sampling time storage unit 11b. When performing the A / D conversion process of B, the sampling time setting unit 11a applies the sampling time Ts1 stored in the sampling time storage unit 11b.

  That is, at the time TDA2, TOA2, TSB2, TDB2, and TOB2 shown in FIG. A, CH. The A / D conversion process related to B is performed, and the sampling time Ts1 stored in the sampling time storage unit 11b is set to the time TSB2 in this, and the A / D conversion unit waits for this sampling time Ts1. 7 performs A / D conversion processing. This eliminates the need to repeatedly calculate the sampling time Ts1. At this time, the application period of the sampling time Ts1 is preferably continued until the reset signal RESET is given.

  As shown in FIG. 8, the reset signal RESET is based on, for example, a single pulse. If the microcomputer includes a module outside the A / D converter 203, such as a monitoring IC or the A / D converter 203, the microcomputer The reset control unit generates a reset signal RESET when any abnormality is detected. The A / D control unit 211 of the A / D conversion device 203 can receive a reset signal RESET.

  When the A / D control unit 211 receives the pulse of the reset signal RESET, the A / D control unit 211 invalidates the sampling time Ts1 stored in the sampling time storage unit 11b. Thereafter, when the sampling time setting unit 11a of the A / D control unit 211 calculates and sets the sampling time Ts2 at time TOA3 in FIG. 8, this sampling time Ts2 is applied to the time TSB3. At this time, the sampling time storage unit 11b stores the initial sampling time Ts2. Thereafter, this sampling time Ts2 is used until the reset signal RESET is received. In this way, the process is repeated.

  According to the present embodiment, the sampling time Ts1 can be applied until the reset signal RESET is received. When the reset signal RESET is received, the sampling time Ts1 is invalidated and can be updated and set again. Thus, until the reset signal RESET is input, the first sampling time Ts1 is stored in the sampling time storage unit 11b, and the calculation time can be reduced by applying the sampling time Ts1, and according to the input of the reset signal RESET. The sampling time Ts1 can be changed to a different sampling time Ts2.

(Fifth embodiment)
FIG. 9 shows an additional explanatory diagram of the fifth embodiment. Parts that are the same as or similar to those in the previous embodiment are given the same or similar reference numerals, and descriptions thereof are omitted. FIG. 9 shows a timing chart in place of FIG. 7 and FIG. In this embodiment, the A / D control unit 211 determines whether or not a predetermined time Ta has elapsed, or whether or not a predetermined number of A / D conversion processing cycles have been performed by the A / D conversion unit 7. It is used as a progress determination unit for determining whether or not. The A / D control unit 211 of the present embodiment includes a timer, for example, and can measure a predetermined time Ta. In addition, the A / D control unit 211 may be configured to include a counting unit for A / D conversion processing cycles.

  As shown in FIG. 9, the A / D control unit 211, for example, starts measuring a timer from the timing at which the sampling time Ts1 is set, determines whether or not a predetermined time Ta has elapsed, and this determination is correct. If it is determined to be correct, the sampling time Ts1 stored in the sampling time storage unit 11b is invalidated.

  At this time, the sampling time setting unit 11a updates the sampling time Ts1 stored in the sampling time storage unit 11b to Ts2 and stores it in the sampling time storage unit 11b at the timing when the predetermined time Ta has elapsed. Further, instead of the condition of the predetermined time Ta, each channel CH. A, CH. B, CH. The sampling time Ts1 may be updated and set to Ts2 at the timing when the predetermined number of C A / D conversion cycles are completed.

  In the present embodiment, the initial sampling time Ts1 is stored in the sampling time storage unit 11b until the predetermined time Ta elapses or until a predetermined number of A / D conversion cycles are completed. Thereby, calculation processing time can be reduced. Moreover, the sampling time Ts1 can be updated to Ts2 when the predetermined time Ta has elapsed or when a predetermined number of A / D conversion cycles have been completed.

(Sixth embodiment)
10 and 11 show additional explanatory views of the sixth embodiment. Parts that are the same as or similar to those in the previous embodiment are given the same or similar reference numerals, and descriptions thereof are omitted. FIG. 10 schematically shows a system configuration in place of FIG. 1, and FIG. 11 shows a timing chart in place of FIGS.

  As illustrated in FIG. 10, the A / D conversion device 303 includes an A / D control unit 311. The A / D control unit 311 receives the A / D conversion output ADOUT of the current channel from the A / D conversion unit 7 and the previous A immediately before the current of the channel from the A / D conversion output storage unit 8. The / D conversion output ADOUT can be referred to. As a result, the A / D control unit 311 causes the current A / D conversion output ADOUT of a certain channel (eg, CH.A) and the previous A / D conversion output immediately before this time of this channel (eg, CH.A). ADOUT can be compared with each channel CH. A to CH. The A / D conversion output ADOUT of C can be compared as a change in value with time, and functions as an output change determination unit.

  As shown in FIG. 11, when the A / D control unit 311 inputs the previous and current A / D conversion outputs, the sampling time setting unit determines that the difference between the A / D conversion outputs has changed by a predetermined threshold value or more. 11a changes the sampling time Ts1 to Ts2 and updates it.

  At time TOA3 in FIG. 11, the A / D converter 7 performs the current channel CH. A / D conversion output ADOUT of A is obtained. At this time, the channel CH. The previous A / D conversion output ADOUT of A is read, and the absolute value of the difference V1−V1a is compared with a predetermined threshold value. When the absolute value of the difference V1−V1a becomes less than the predetermined threshold, the sampling time setting unit 11a uses the sampling time Ts1 as it is for the next and subsequent sampling times, but the absolute value of the difference V1−V1a is greater than or equal to the predetermined threshold. If so, the sampling time Ts1 is changed to Ts2 and updated to the time TSB3. This is a process performed because the appropriate sampling time also changes when the A / D conversion output ADOUT changes greatly.

  According to the present embodiment, when a plurality of A / D conversion output differences between the previous time and the current time change more than a predetermined threshold, the sampling time setting unit 11a invalidates the sampling time Ts1 and changes it to the sampling time Ts2 and sets the update. I did it. For this reason, the previous sampling time Ts1 is stored in the sampling time storage unit 11b until the difference between the previous and current A / D conversion output changes by a predetermined threshold value or more. As a result, the calculation processing time can be reduced, and a certain channel CH. The sampling time Ts1 can be changed after the A / D conversion output ADOUT of A changes by a predetermined threshold value or more.

  In the above description, the difference V1−V1a obtained by comparing the successive A / D conversion outputs ADOUT of the previous time and the current time is used. However, any two A / D conversion outputs ADOUT may be compared. For example, when the difference between the first A / D conversion output ADOUT and the current A / D conversion output ADOUT changes by a predetermined threshold value or more, the sampling time Ts1 may be changed and updated. In other words, if it is determined that the arbitrary A / D conversion output ADOUT has changed by a predetermined threshold value or more, the sampling time setting unit 11a invalidates the sampling time Ts1 stored in the sampling time storage unit 11b, and the sampling time Ts2 may be calculated and updated. Even in this case, the arithmetic processing time can be reduced by using the first sampling time Ts1 until the A / D conversion output difference of a plurality of times changes to a predetermined threshold value or more, and the sampling time after changing the predetermined threshold value or more. Ts1 can be updated to Ts2.

(Seventh embodiment)
FIG. 12 shows an additional explanatory diagram of the seventh embodiment. Parts that are the same as or similar to those in the previous embodiment are given the same or similar reference numerals, and descriptions thereof are omitted. FIG. 12 shows a timing chart in place of FIGS. 7 to 9 and FIG. As shown in FIG. 12, a trigger signal input from the outside may be used instead of the reset signal RESET of the fourth embodiment.

The sampling time setting unit 11a may update and set the sampling time Ts using a trigger signal input from the outside as a trigger.
(Other embodiments)
The present invention is not limited to the above-described embodiments, and can be applied to various embodiments without departing from the scope of the invention. The configurations of the first to seventh embodiments can be combined as appropriate. Further, the switching unit is not limited to the multiplexer 5. The holding unit is not limited to the capacitor CHOLD. As long as there are a plurality of channels, the number of channels is not limited to three and may be four or more. Although applied for mounting on vehicles, it is not limited to this.

  The reference numerals in parentheses described in the claims indicate the correspondence with the specific means described in the embodiment described above as one aspect of the present invention, and the technical scope of the present invention is It is not limited.

  In the drawing, 3, 203, 303 are A / D converters, 5 is a multiplexer (switching unit), 6 is a holding unit, 7 is an A / D converter, 9 is a comparison reference setting unit, 11, 211, 311 are A / D control unit (211 is a progress determination unit, 311 is an output change determination unit, 11a is a sampling time setting unit, 11b is a sampling time storage unit (initial sampling time storage unit), and CHOLD is a capacitor (sampling capacitor).

Claims (11)

An A / D converter (3, 203, 303) for digitally converting analog input signals of a plurality of channels,
A switching unit (5) for switching the analog input signals of the plurality of channels;
A holding unit (6) for holding a voltage by inputting an analog input signal of one of the plurality of channels switched by the switching unit to a sampling capacitor (CHOLD) at a sampling time;
A / D conversion is configured such that a voltage in a range between a predetermined reference voltage and a reference ground can be quantized, the analog input signal is input, and the voltage of the holding unit that is input for the sampling time is subjected to A / D conversion processing. Part (7),
A comparison reference setting unit (9) for setting a comparison reference within the range of the reference voltage and the reference ground;
The sampling time of the A / D conversion process of the other channel next time is calculated according to the difference between the A / D conversion output of the current channel A / D converted by the A / D converter and the comparison reference. A sampling time setting section (11a) to be set. The A / D conversion device according to claim 1,
The sampling time setting unit (11a) is an A / D conversion device that sets the sampling time longer as the difference between the A / D conversion output and the comparison reference is larger. The A / D conversion device according to claim 1 or 2,
The comparison reference setting unit (9) divides the current A / D conversion output range into a plurality of sections by setting a comparison reference within the range of the reference voltage and the reference ground,
When the sampling time setting unit (11a) determines that the A / D conversion output is in any one of a plurality of sections, the sampling time setting unit (11a) sets a predetermined sampling time for each of the plurality of sections. D converter. In the A / D conversion device according to any one of claims 1 to 3,
The sampling time setting unit (11a) is an A / D conversion device that sets the sampling time to a predetermined maximum value when the A / D conversion output is a reference voltage or a reference ground of the A / D conversion unit. In the A / D conversion device according to any one of claims 1 to 4,
After the sampling time setting unit (11a) sets the next sampling time according to the difference between the A / D conversion output and the comparison reference,
The switching unit, the holding unit, and the A / D conversion unit are A / D conversion devices that perform processing related to A / D conversion processing of the next channel. In the A / D conversion device according to any one of claims 1 to 5,
The sampling time setting unit (11a) is an A / D conversion device that performs the sampling time calculation process in parallel with the A / D conversion output calculation process by the A / D conversion unit. In the A / D conversion device according to any one of claims 1 to 6,
An initial sampling time storage unit (11b) for storing the initial sampling time of the next channel set by the sampling time setting unit (11a);
The sampling time setting unit (11a) is an A / D conversion device that sets the sampling time stored in the initial sampling time storage unit after the second time of the channel. In the A / D conversion device according to any one of claims 1 to 7,
It is configured to be able to input a reset signal generated internally or externally,
A sampling time storage unit (11b) for storing the sampling time of the channel set by the sampling time setting unit (11a);
When the reset signal is input, the sampling time setting unit (11a) invalidates the sampling time stored in the sampling time storage unit, calculates the sampling time, and updates and sets the sampling time. In the A / D conversion device according to any one of claims 1 to 7,
A sampling time storage unit (11b) for storing the sampling time of the channel set by the sampling time setting unit (11a);
A progress determination unit (211) that determines whether or not a predetermined number of A / D conversion processing cycles have been performed by the switching unit, the holding unit, and the A / D conversion unit, or whether a predetermined time has elapsed; Further comprising
The sampling time setting unit (11a) invalidates the sampling time stored in the sampling time storage unit when the progress determination unit determines that it is correct, calculates the sampling time, and updates and sets the A / D Conversion device. In the A / D conversion device according to any one of claims 1 to 7,
A sampling time storage unit (11b) for storing the sampling time of the channel set by the sampling time setting unit;
When the A / D conversion unit outputs the A / D conversion output of the channel only a plurality of times, an output change for determining whether or not a plurality of A / D conversion output differences of the channel have changed by a predetermined threshold value or more. A determination unit (311),
The sampling time setting unit (11a) invalidates the sampling time stored in the sampling time storage unit and calculates the sampling time of the channel when it is determined that the output change determination unit has changed by a predetermined threshold value or more. A / D conversion device for update setting. In the A / D conversion device according to any one of claims 1 to 7,
An external trigger signal can be input,
A sampling time storage unit (11b) for storing the sampling time of each of a plurality of channels set by the sampling time setting unit;
When the trigger signal is input, the sampling time setting unit (11a) invalidates the sampling time stored in the sampling time storage unit, calculates the sampling time, and updates and sets the sampling time.

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