WO2018085972A1

WO2018085972A1 - Capacitor detection circuit and control method therefor

Info

Publication number: WO2018085972A1
Application number: PCT/CN2016/105002
Authority: WO
Inventors: 汪正锋
Original assignee: 深圳市汇顶科技股份有限公司
Priority date: 2016-11-08
Filing date: 2016-11-08
Publication date: 2018-05-17
Also published as: CN106796259B; CN106796259A

Abstract

A capacitor detection circuit and a control method therefor, which relate to the technical field of electronics. The capacitor detection circuit comprises: a switch capacitor amplifier, a comparator (C_omp), and a sequential control unit (H). The switch capacitor amplifier comprises a variable capacitor array (C_c) that is connected to a to-be-detected capacitor and that has N capacitor branches, N being an integer and N being greater than 1. A first input end of the comparator (C_omp) is connected to an output end of the switch capacitor amplifier, and a second input end of the comparator (C_omp) is connected to a first reference voltage (V_cm). An input end of the sequential control unit (H) is connected to an output end (D)_of the comparator (C_omp), and an output end of the sequential control unit (H) is connected to a capacitor adjustment end of the variable capacitor array (C_c). By means of the capacitor detection circuit, the structure of a circuit is simplified, and a capacitance value is directly converted into a digital value, thereby greatly reducing the area and the power consumption of the capacitor detection circuit.

Description

Capacitance detecting circuit and control method thereof

Technical field

Embodiments of the present invention relate to the field of electronic technologies, and in particular, to a capacitance detecting circuit and a control method thereof.

Background technique

Currently, capacitive sensors are commonly used as input devices and are widely used in a variety of electronic systems to provide information about the input (such as position, motion, force, duration, etc.) to the electronic system. Generally, the user generates a capacitive effect by sensing (eg, approaching, contacting, pressing, sliding, etc.) one or more sensing regions of the capacitive sensor, and by measuring the capacitive effect, the user's operation can be determined. . Among them, the capacitance detection circuit is the core of the capacitive sensor, and its circuit design directly affects the overall cost and power consumption of the capacitive sensor.

Figure 1 shows the existing capacitance detection circuit diagram, including the capacitor C _x to be detected, the integrator F _x and the analog-to-digital converter ADC. The first end of the capacitor C _x to be detected is connected to the analog-to-digital converter ADC through an integrator F _x , and the second end of the capacitor C _x to be detected is grounded to GND ₀ . Among them, the integrator F _x converts the capacitive effect into a voltage amount, and then samples and quantizes it into a digital quantity through an analog-to-digital converter ADC, thereby performing capacitance detection.

However, in the process of implementing the present invention, the inventors have found that the prior art has the following problems: the existing capacitance detecting circuit is relatively complicated, and the analog to digital converter ADC is used, resulting in a very large area and power consumption of the capacitance detecting circuit. It is very disadvantageous for capacitive sensors.

Summary of the invention

An object of embodiments of the present invention is to provide a capacitance detecting circuit and a controller thereof The method simplifies the circuit structure and directly converts the capacitance value into a digital quantity, which greatly reduces the area and power consumption of the capacitance detecting circuit.

To solve the above technical problem, an embodiment of the present invention provides a capacitance detecting circuit, including: a switched capacitor amplifier, a comparator, and a timing control unit; the switched capacitor amplifier includes an N capacitor branch connected to a capacitor to be detected Variable capacitance array; wherein N is a natural number and N>1; a first input of the comparator is coupled to an output of the switched capacitor amplifier, and a second input of the comparator is coupled to a first reference a voltage; an input of the timing control unit is coupled to an output of the comparator, an output of the timing control unit is coupled to a capacitance adjustment terminal of the variable capacitor array; wherein, in N clock cycles, The timing control unit sequentially disables N capacitor branches in the variable capacitor array, and the output of the comparator sequentially outputs N digital quantities for characterizing the capacitance to be detected.

The embodiment of the present invention further provides a method for controlling a capacitance detecting circuit, which is applied to the above-mentioned capacitance detecting circuit, and the control method includes: controlling the switched capacitor amplifier to enter the first non in the i+1th clock cycle An overlap phase; in the non-overlap phase, discharging the switched capacitor amplifier, and when i+1≥2, if the comparator outputs the ith number in the ith clock cycle The quantity is 0, enabling the Nith capacitor branch in the variable capacitor array; controlling the switched capacitor amplifier to enter a reset phase; in the reset phase, charging the switched capacitor amplifier; controlling the The switched capacitor amplifier enters a second non-overlapping phase; in the second non-overlapping phase, the N-(i+1)th capacitive branch in the variable capacitor array is disabled; and the switched capacitor is controlled The amplifier enters an amplification phase; in the amplification phase, the comparator outputs an i+1th digital quantity; wherein, i=0, 1, 2, .....N-1; in N clock cycles, The N digital quantities sequentially output by the comparator are used to characterize the waiting Measuring capacitance.

Compared with the prior art, an embodiment of the present invention provides a capacitance detecting circuit including a switched capacitor amplifier, a comparator, and a timing control unit. The switched capacitor amplifier includes a variable capacitor array with N capacitive branches (N is a natural number and N > 1). Timing control in N clock cycles The unit sequentially disables the N capacitor branches in the variable capacitor array, and the output ends of the comparator sequentially output N digital quantities for characterizing the capacitor to be detected; that is, the analog-to-digital converter ADC is omitted in the embodiment of the present invention, and The capacitance value of the capacitor to be detected is directly converted into a digital quantity by successive approximation, which simplifies the circuit structure and greatly reduces the area and power consumption of the capacitance detecting circuit.

In addition, the first reference voltage is greater than the third reference voltage and smaller than the second reference voltage, and the first input end and the second input end of the comparator are a non-inverting input end and an inverting input end, respectively. In this embodiment, a connection mode of the switched capacitor amplifier and the comparator is provided.

In addition, the first reference voltage is greater than the second reference voltage and smaller than the third reference voltage, and the first input end and the second input end of the comparator are respectively an inverting input end and a non-inverting input end. In this embodiment, another connection mode of the switched capacitor amplifier and the comparator is provided.

In addition, the first reference voltage is half of a sum of the second reference voltage and the third reference voltage. In this embodiment, a value manner of the first reference voltage is provided, so that the circuit reduces the calculation amount and saves power consumption.

In addition, the timing control unit is a timing control circuit; or the timing control unit is a control chip. In this embodiment, two implementations of the timing control unit are provided.

DRAWINGS

The one or more embodiments are exemplified by the accompanying drawings in the accompanying drawings, and FIG. The figures in the drawings do not constitute a scale limitation unless otherwise stated.

1 is a schematic diagram of a capacitance detecting circuit in the background art;

2 is a schematic diagram of a capacitance detecting circuit of the first embodiment;

3 is a schematic diagram of a variable capacitor array in the first embodiment;

4 is a schematic diagram showing timing control of a capacitance detecting circuit in a third embodiment;

5 is a schematic diagram of the capacitance detecting circuit in the first non-overlapping phase in the third embodiment;

6 is a schematic diagram of the capacitance detecting circuit of the third embodiment in a reset phase;

7 is a schematic diagram of the capacitance detecting circuit of the third embodiment in a second non-overlapping phase;

Fig. 8 is a schematic view showing the capacitance detecting circuit of the third embodiment in an amplification stage.

detailed description

In order to make the objects, technical solutions, and advantages of the present invention more apparent, the embodiments of the present invention will be described in detail below. However, it will be apparent to those skilled in the art that, in the various embodiments of the present invention, numerous technical details are set forth in order to provide the reader with a better understanding of the present application. However, the technical solutions claimed in the present application can be implemented without these technical details and various changes and modifications based on the following embodiments.

A first embodiment of the invention relates to a capacitance detecting circuit. As shown in FIG. 2, the capacitance detecting circuit includes a switched capacitor amplifier, a comparator C _omp, and a timing control unit H.

In this embodiment, the first input of the comparator C _omp is connected to the output of the switched capacitor amplifier, and the second input of the comparator C _omp is connected to the first reference voltage V _cm .

In the present embodiment, the switched capacitor amplifier is connected to the capacitor to be detected is C _x, which has N comprising a variable capacitance array capacitor branch C _c, the operational amplifier O _p, feedback capacitor C _f, and the first to fifth switches S ₀ ～S ₄ ; wherein N is a natural number and N>1. Specifically, the first end of the capacitor C _x to be detected is connected to the second reference voltage V _refp through the first switch S ₀ , and the second end of the capacitor C _x to be detected is grounded to GND ₀ . The first end of the variable capacitor array C _c is connected to the third reference voltage V _refn through the second switch S ₁ , and is connected to the first end and the fourth switch S _{3 of the} capacitor C _x to be detected through the third switch S ₂ ; The second end of the variable capacitance array C _c is connected to the third reference voltage V _refn . Inverting input terminal of the operational amplifier O _p is connected through a fourth switch S ₃ to be detected the capacitance C _x of the first terminal and the third switch S _2, the operational amplifier O _p-inverting input terminal is connected to a first reference voltage V _cm . A feedback capacitor C _f S ₄ and the fifth switch are connected across the inverting input terminal and the output terminal of the operational amplifier O _p.

As shown in FIG. 3, the variable capacitor array C _c in this embodiment includes N capacitor branches, and each capacitor branch includes a capacitor C _i and a branch switch S _c,i . In the i-th capacitor branch, and branch switching capacitor C _i S _{c, i} series. The branch switch S _{c,i is} turned on, indicating that the capacitor C _{i is} connected to the variable capacitor array C _c ; the switch S _{c,i is} disconnected, indicating that the capacitor C _{i is} removed from the variable capacitor array C _c . Wherein, the capacitance of the ith capacitor branch can be expressed as: C _i = 2 ⁱ C _u , i = 0, 1, 2, ..., N-1; wherein C _i represents the capacitance of the ith capacitor branch, C _u represents the unit capacitance, and its size can be selected according to the need; according to the formula, the capacitance values of the capacitors C _i to C _Ni increase sequentially. However, the present embodiment does not impose any limitation on the capacitance of each capacitor branch, and can be set by a person skilled in the art according to actual needs.

In the present embodiment, the timing control unit H is configured to generate a control signal of the variable capacitance array C _c and the first to fifth switches (S _{0 to 4} ). The input of the timing control unit H is connected to the output D of the comparator C _omp , and the output of the timing control unit H is connected to the capacitance regulating terminal of the variable capacitor array C _c . Specifically, the timing control unit H includes first to fourth control terminals. The first control end is connected to the first switch S ₀ and the second switch S ₁ ; the second control end is connected to the third switch S ₂ and the fourth switch S ₃ ; the third control end is connected to the fifth switch S ₄ ; The control terminal (ie, the output of the timing control unit H) is connected to the capacitance regulating terminal of the variable capacitance array C _c .

In fact, the timing control unit H can be understood as a timing control unit comprising a successive approximation register (SAR); the successive approximation register is used to generate a control signal of the variable capacitance array C _c from the output signal of the comparator C _omp .

In the present embodiment, the timing control unit H is a timing control circuit; that is, a control signal is generated by hardware. Alternatively, the timing control unit H is a control chip; that is, the timing control signal is generated by software; however, the specific implementation manner of the timing control unit H is not limited in this embodiment, and may be specifically designed according to actual conditions.

In this embodiment, the first reference voltage V _{cm is} between the second reference voltage V _refp and the third reference voltage V _refn . Specifically, the first reference voltage V _{cm is} greater than the third reference voltage V _refn and smaller than the second reference voltage V _refp . At this time, the first input end and the second input end of the comparator C _omp are the positive phase input end and the opposite end respectively. Phase input. Preferably, the first reference voltage V _cm can be set to be half of the _sum of the second reference voltage V _refp and the third reference voltage V _refn ; thereby reducing the calculation amount of the circuit and saving power consumption; The set value of the test voltage V _cm is not limited as long as it satisfies between the second reference voltage V _refp and the third reference voltage V _refn .

In the capacitance detecting circuit of the present embodiment, the one-time detecting process for the capacitance detecting circuit substantially includes N clock cycles; in N clock cycles, the timing control unit H sequentially disables the N capacitor branches in the variable capacitor array C _c The output terminal D of the comparator C _omp sequentially outputs N digital quantities d _{N-1 ～ 0} for characterizing the capacitance C _x to be detected. That is, the capacitance value of the capacitor _Cx to be detected is directly converted into N digital quantities by successive approximation. When the capacitance value of the capacitor _Cx to be detected changes, the converted N digital quantities also change; therefore, By continuously detecting multiple times and comparing the changes of N digital quantities, the change of the capacitance to be detected can be detected in real time.

Embodiments of the present invention provide a capacitance detecting circuit including a switched capacitor amplifier, a comparator, and a timing control unit with respect to the prior art. The switched capacitor amplifier includes a variable capacitor array with N capacitive branches (N is a natural number and N > 1). In N clock cycles, the timing control unit disables the N capacitor branches in the variable capacitor array in descending order of capacitance values, and the output terminals of the comparator sequentially output N capacitors for characterizing the capacitor to be detected. The digital quantity; that is, the existing analog-to-digital converter ADC is omitted in the embodiment of the present invention, and the circuit value is simplified by directly converting the capacitance value of the capacitor to be detected into a digital quantity by a binary search algorithm or the like, thereby simplifying the circuit structure. The area of the capacitance detecting circuit and the power consumption are greatly reduced.

A second embodiment of the present invention relates to a capacitance detecting circuit. The second embodiment is substantially the same as the first embodiment. The main difference is that in the first embodiment, the first reference voltage is greater than the third reference voltage and smaller than the second reference voltage, and the first input end of the comparator The two input terminals are a positive phase input terminal and an inverting input terminal, respectively. In the second embodiment of the present invention, the first reference voltage is greater than the second reference voltage and less than the third reference voltage, and the first input end and the second input end of the comparator They are the inverting input and the positive input.

Embodiments of the present invention provide another way of connecting a switched capacitor amplifier to a comparator with respect to the first embodiment.

A third embodiment of the present invention relates to a method of controlling a capacitance detecting circuit, which is applied to a capacitance detecting circuit in the first embodiment or the second embodiment. The control method of this embodiment can be understood as performing continuous multiple detections on the capacitance to be detected. The one-time detection process of the detection capacitor essentially includes N clock cycles. In each clock cycle, the comparator outputs a digital quantity; that is, the N digital quantities sequentially output by the comparator are used to characterize the capacitance to be detected.

As shown in FIG. 4, in the timing control diagram of the capacitance detecting circuit in the present embodiment, the primary circuit detecting process includes N clock cycles. In each clock cycle, the first control terminal of the timing control unit H generates a clock signal φ1 to control the first switch S0 and the second switch S1, and the second control terminal generates a clock signal φ2 to control the third switch S2 and the fourth switch S3, The third control terminal generates a signal φ3 to control the fifth switch S4, and the fourth control terminal generates a signal φc,0 to control the branch switch Sc,0. Among them, φ1 and φ2 are two-phase non-overlapping clocks, clk is the system clock, and T1 is the first conversion (T1 to N indicate the first to Nth conversions); when the rising edge of the start signal comes, the detection process starts.

In each clock cycle, the timing control unit has similar control signals to the switched capacitor amplifier output; as follows:

In the i+1th clock cycle:

First, the switched-capacitor amplifier is controlled to enter the first non-overlapping phase. In the first non-overlapping phase, the switched capacitor amplifier discharges, and when i+1 ≥ 2, if the ith digital quantity output by the comparator in the ith clock cycle is 0, the variable capacitor is enabled. The Ni-th capacitor branch in the array.

Second, the switched-capacitor amplifier is controlled to enter the reset phase. During the reset phase, the switched capacitor amplifier is charged.

Again, the switched-capacitor amplifier is controlled to enter a second non-overlapping phase. In the second non-overlapping phase, The N-th (i+1)th capacitor branch in the variable capacitor array is disabled.

Finally, the switched-capacitor amplifier is controlled to enter the amplification phase. In the amplification phase, the comparator outputs the i+1th digital quantity.

Wherein, i=0, 1, 2, .....N-1; in N clock cycles, the N digital quantities sequentially output by the comparator are used to characterize the capacitance to be detected.

The following takes i=0 as an example for description, that is, the first clock cycle is taken as an example for description.

First, when φ ₁ =0 and φ ₂ =0, the switched capacitor amplifier is controlled to enter the first non-overlapping phase A ₁ . At this time, φ ₃ =1, φ _{c, N-1 ～ 0} =1, as shown in FIG. 5, the switches S _{0 ～3 are} turned off, the switches S ₄ , S _{c , N-1 ～ 0 are} closed, and the switched capacitor amplifier is turned off. The feedback capacitor C _f is discharged.

Next, when φ ₁ =1 and φ ₂ =0, the switched capacitor amplifier is controlled to enter the reset phase B. At this time, φ ₃ =1, φ _{c, N-1 ～ 0} =1, as shown in FIG. 6 , the switches S _{0 ～1 are} closed; the capacitance C _{x to} be measured is charged, and the variable capacitance array C _c is discharged. And continue to discharge the feedback capacitor C _f , at which time the output voltage V _{out of the} switched capacitor amplifier is equal to the first reference voltage V _cm (ie, V _out = V _cm ).

In fact, if the amount of charge in the variable capacitor array C _c is zero before entering the reset phase B, there is no charge flow between the ends of the variable capacitor array C _c after entering the reset phase B (not After experiencing the actual discharge process); if the voltage at one end of the variable capacitor array C _c is greater than the voltage at the other end before entering the reset phase B, the voltage in the variable capacitor array C _c is higher after entering the reset phase B One end of the capacitor discharges to the lower voltage end until the amount of charge in the variable capacitor array C _c is zero. At this time, the voltage across the variable capacitor array C _c is V _refn ; that is, at the end of the reset phase B, The amount of charge in the variable capacitance array C _c is zero.

Then, when φ ₁ =0 and φ ₂ =0, the switched capacitor amplifier is controlled to enter the second non-overlapping phase A ₂ . At this time, φ ₃ =0, φ _{c, N-1} =0, φ _{c, N-2 ～ 0} =1, as shown in Fig. 7, the switches S _{0 to 4} , S _{c, N-1 are} off, the switch S _{c, N-2 ～ 0 is} closed; C _{N-1 is} removed from the variable capacitor array Cc, that is, the disable capacitor C _N-1 .

Finally, when φ ₁ =0 and φ ₂ =1, the switched capacitor amplifier is controlled to enter the amplification phase C. At this time, φ ₃ =0, φ _{c, N-1} =0, φ _{c, N-2 ～ 0} =1, as shown in Fig. 8, the switches S _{2 ～ 3 are} closed; the capacitance to be measured C _x and the variable capacitance C _c for charge redistribution array, and amplified via the amplifier; switched capacitor amplifier output terminal voltage Vout = Vcm + [((Vcm -Vrefn) Cc + (Vcm-Vrefp) Cx) / Cf].

In this embodiment, it is determined whether the bit capacitance is re-connected into the variable capacitor array C _c by comparing the comparator C _omp with the common mode voltage (in the present embodiment, the first reference voltage V _{cm is} used as the common mode voltage); That is, the magnitudes of V _out and V _cm are compared by the comparator C _omp . If V _out ≥ V _cm , the output D of the comparator C _omp outputs a digital quantity d _N-1 =1, keeping C _N-1 removed from the variable capacitance array C _c . If V _out <V _cm , the output D of the comparator C _omp outputs a digital quantity d _N-1 =0, then in the next clock cycle, when the circuit is in the non-overlapping state A ₁ , the C _{N-1 is} reconnected. It enters the variable capacitor array C _c (ie, remains connected to the variable capacitor array C _c ); after the comparison is completed, the first period ends.

In this embodiment, the process of the first cycle is repeated N times. When the capacitance C _{0 is} determined, the capacitance detection is completed; that is, the capacitors C _N-2 , C _N-3 , . . . , C _{0 are} sequentially removed from the variable capacitor. The array C _c is compared by the comparator C _omp to obtain an N-bit digital quantity D=d _N-1 d _N-2 ... d ₁ d ₀ , N-bit digital quantity (D=d _N-1 d _N-2 ...d ₁ d ₀ ) corresponds to the capacitance value of the capacitor C _x to be detected.

In this embodiment, the capacitance value of the capacitor C _x to be detected can be expressed as:

When C _i =2 ⁱ C _u (i=0, 1, 2, ... N-1), the capacitance value of the capacitance C _x to be detected can be expressed as

Taking the above-mentioned N-bit digital quantity as the reference D ₀ , when the capacitance C _x to be detected changes, another set of N-bit digital quantity D _{1 is obtained} , and the change amount ΔC _{x of the} capacitance to be detected can be expressed as: ΔCx=[(Vcm -Vrefn) / (Vrefp - Vcm)] * (D _{1 -} D ₀ ) * Cu.

Compared with the prior art, the embodiment of the present invention applies the capacitance detecting circuit provided by the embodiment of the present invention to detect the change of the capacitance in real time, and performs corresponding control on the stage of the switched capacitor amplifier in each clock cycle. (including a first non-overlapping phase, a reset phase, a second non-overlapping phase, and an amplifying phase), so that the comparator sequentially outputs N digital quantities to correspond to the capacitance to be detected. Capacitance value.

The steps of the above various methods are divided for the sake of clear description. The implementation may be combined into one step or split into certain steps and decomposed into multiple steps. As long as the same logical relationship is included, it is within the protection scope of this patent. The addition of insignificant modifications to an algorithm or process, or the introduction of an insignificant design, without changing the core design of its algorithms and processes, is covered by this patent.

It is not difficult to find that the present embodiment is an embodiment of the method corresponding to the first and second embodiments, and the present embodiment can be implemented in cooperation with the first and second embodiments. The related technical details mentioned in the first and second embodiments are still effective in the present embodiment, and are not described herein again in order to reduce repetition. Accordingly, the related technical details mentioned in the present embodiment can also be applied to the first and second embodiments.

Those skilled in the art can understand that all or part of the steps of implementing the above embodiments may be completed by a program instructing related hardware, and the program is stored in a storage medium, and includes a plurality of instructions for making a device (which may be a single chip microcomputer). , a chip, etc. or a processor performs all or part of the steps of the methods described in various embodiments of the present application. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and the like. .

A person skilled in the art can understand that the above embodiments are specific embodiments for implementing the present invention, and various changes can be made in the form and details without departing from the spirit and scope of the present invention. range.

Claims

A capacitance detecting circuit, comprising: a switched capacitor amplifier, a comparator, and a timing control unit;

The switched capacitor amplifier includes a variable capacitor array having N capacitor branches connected to a capacitor to be detected; wherein N is a natural number and N>1;

a first input of the comparator is coupled to an output of the switched capacitor amplifier, and a second input of the comparator is coupled to a first reference voltage;

An input end of the timing control unit is connected to an output end of the comparator, and an output end of the timing control unit is connected to a capacitance adjustment end of the variable capacitor array;

Wherein, in the N clock cycles, the timing control unit sequentially disables the N capacitor branches in the variable capacitor array, and the output of the comparator sequentially outputs N for characterizing the capacitor to be detected. A digital quantity.
The capacitance detecting circuit according to claim 1, wherein the switched capacitor amplifier further comprises an operational amplifier, a feedback capacitor, and first to fifth switches;

The first end of the capacitor to be detected is connected to the second reference voltage through the first switch, and the second end of the capacitor to be detected is grounded;

The first end of the variable capacitor array is connected to the third reference voltage through the second switch, and is connected to the first end of the capacitor to be detected through the third switch; The two ends are connected to the third reference voltage; wherein the first reference voltage is between the second reference voltage and the third reference voltage;

The inverting input terminal of the operational amplifier is connected to the first end of the capacitor to be detected through the fourth switch, and the non-inverting input terminal of the operational amplifier is connected to the first reference voltage;

The feedback capacitor and the fifth switch are respectively connected across an inverting input of the operational amplifier End and output;

The timing control unit includes first to fourth control terminals, the first control terminal is connected to the first switch and the second switch, and the second control terminal is connected to the third switch and the fourth switch; The control terminal is connected to the fifth switch, and the fourth control terminal is connected to the capacitance regulating end of the variable capacitor array.
The capacitance detecting circuit according to claim 2, wherein the first reference voltage is greater than the third reference voltage and smaller than the second reference voltage, the first input and the second input of the comparator The terminals are a positive phase input terminal and an inverting input terminal, respectively.
The capacitance detecting circuit according to claim 2, wherein the first reference voltage is greater than the second reference voltage and smaller than the third reference voltage, and the first input and the second input of the comparator The terminals are an inverting input and a positive input.
The capacitance detecting circuit according to claim 2, wherein the first reference voltage is half of a sum of the second reference voltage and the third reference voltage.
The capacitance detecting circuit according to claim 1, wherein the timing control unit is a timing control circuit; or the timing control unit is a control chip.
The capacitance detecting circuit according to claim 1, wherein the capacitance of the ith capacitor branch in the variable capacitor array is expressed as:

C i =2 i C u ,i=0,1,2,...N-1;

Where C i represents the capacitance of the ith capacitor branch and Cu represents the unit capacitance.
A method of controlling a capacitance detecting circuit, which is characterized by being applied to the capacitance detecting circuit according to any one of claims 1 to 7, wherein the control method comprises:

In the i+1th clock cycle,

Controlling the switched capacitor amplifier to enter a first non-overlapping phase; in the non-overlapping phase, discharging the switched capacitor amplifier, and when i+1≥2, if the comparator is at the The i-th digital quantity outputted in one clock cycle is 0, enabling the N-ith capacitive branch in the variable capacitance array;

Controlling the switched capacitor amplifier to enter a reset phase; in the reset phase, charging the switched capacitor amplifier;

Controlling the switched capacitor amplifier to enter a second non-overlapping phase; in the second non-overlapping phase, disabling the N-(i+1)th capacitive branch in the variable capacitor array;

Controlling the switched capacitor amplifier to enter an amplification phase; in the amplification phase, the comparator outputs an i+1th digital quantity;

Wherein, i=0, 1, 2, . . . , N-1; in N clock cycles, the N digital quantities sequentially output by the comparator are used to characterize the capacitance to be detected.