JPH09181604A - Semiconductor integrated circuit device and its noise reduction method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the effect of noise generated in a digital circuit onto an analog circuit in an analog/digital hybrid integrated circuit. SOLUTION: In this device, a circuit 21 susceptible to noise effect, a circuit 23 generating noise are formed on a same substrate with a noise reduction circuit 11 and a correction circuit 22 detecting the effect of noise and calculating the correction amount. A voltage comparator is used to measure in real time over a broad band the effect of the noise generated from the digital circuit onto the analog circuit. Thus, the effect of the noise generated by the digital circuit onto the analog circuit is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device in which a circuit generating noise and a circuit affected by the noise are formed on the same semiconductor substrate, and a method for reducing the influence of the noise and a method for reducing the noise. The present invention relates to an integrated circuit device that can reduce the influence.

[0002]

2. Description of the Related Art In a mixed IC in which an analog circuit and a digital circuit are formed on the same substrate, there is a problem that the analog circuit malfunctions due to the influence of substrate noise generated by the operation of the digital circuit driven by a clock or data signal. is there.

In order to solve this problem, it is first necessary to quantitatively grasp and investigate the magnitude of noise generated by a digital circuit and its influence. So far, a noise measuring method using a voltage comparator has been proposed. This is to change the input signal of the voltage comparator by a small amount and to perform the comparison operation with the reference voltage as the standard, measure the frequency of appearance of the high level of the output of the comparator, and synchronize with the digital circuit operation. This is a method of measuring the waveform of noise by performing equivalent sampling. Such a measuring method is described in Japanese Patent Laid-Open No. 54315/1994.

An analog / digital converter provided with a voltage converter and an arithmetic circuit for addition / subtraction in order to reduce the influence of power supply voltage fluctuation is disclosed in Japanese Patent Laid-Open No. 201826.

[0005]

However, conventionally, no consideration has been given to a circuit configuration capable of removing and reducing the influence of the substrate noise generated in the digital circuit section, etc., and the influence of the noise generating source is effectively eliminated. No possible integrated circuit has been provided. The above-mentioned Japanese Patent Laid-Open No. 3-201826 discloses an analog / digital converter that employs a voltage comparator and an arithmetic circuit in order to reduce the influence of fluctuations in power supply voltage, but the influence of substrate noise is taken into consideration. Not not.

Further, in the conventional noise measuring method using the voltage comparator, the operating clock of the voltage comparator is operated in synchronization with the clock of the digital circuit which generates noise, and the clock is sequentially shifted from the clock of the digital circuit. It is measured by driving. Each sampling value is measured by equivalent sampling by changing the input voltage of the voltage comparator to obtain the output voltage frequency distribution. Therefore, according to the conventional method, it is possible to know the temporal change of the influence of noise, but it takes a long time to measure, and it is possible to measure only when synchronized with a digital clock. As described above, it is difficult to quantitatively evaluate the influence of noise transmitted from the substrate in the analog / digital mixed integrated circuit in real time,
Reduction of noise by establishing a real-time measuring means is an important issue to be solved by the present invention.

Therefore, an object of the present invention is to solve the above-mentioned problems of the conventional technique.

Another object of the present invention is to provide a method capable of reducing the influence of noise generated from a circuit and an integrated circuit device capable of reducing the provision of such noise.

Still another object of the present invention is to provide a noise detection method and a noise detection circuit suitable for the above method and integrated circuit device.

Still another object of the present invention will be apparent from the specification and drawings of the present invention.

[0011]

A noise reduction means for solving the above-mentioned problems comprises at least one noise detection means and a correction means for the noise detected by this means.

Further, a typical embodiment of the present invention includes a first circuit which operates in synchronization with a clock, a second circuit which is affected by noise generated by the first circuit, and the first circuit.
A noise detection circuit that detects noise generated by the circuit of FIG. 3 and an arithmetic circuit that calculates a correction amount in response to the output of the noise detection circuit. The output of the second circuit is the output of the arithmetic circuit. Configured to be corrected.

As a result, the output of the circuit affected by noise can be corrected corresponding to the generated noise, and a semiconductor integrated circuit device having high noise resistance can be obtained.

Further, according to a typical embodiment of the present invention, since the noise detection circuit detects noise in synchronization with the clock signal of the circuit that generates noise, it is possible to detect noise with high accuracy. .

Further, according to a typical embodiment of the present invention, the arithmetic circuit is configured to perform correction by applying a weight corresponding to the noise detection sensitivity of the second circuit. As a result, it becomes possible to perform correction according to the characteristics of the circuit affected by noise.

Further, according to a typical embodiment of the present invention, the arithmetic circuit is configured to perform weighting and correction according to the noise detection sensitivity of the second circuit.

Further, according to the representative embodiment of the present invention, the noise detection circuit is constituted by the sampling type voltage comparison, and the noise detection can be performed by a relatively simple means.

Further, according to the representative embodiment of the present invention, it becomes possible to remove the influence of noise from the analog / digital conversion circuit which is influenced by noise. Further, since the correction amount is calculated according to the noise transfer function of each analog / digital conversion stage, it is possible to reduce the noise effect of the pipeline type analog / digital conversion circuit.

Further, according to the typical embodiment of the present invention, it becomes possible to input the pseudo noise to the substrate through the capacitance connection portion or the resistance connection portion and obtain the noise transfer function of the circuit in advance. It is possible to correct the influence of noise.

Further, according to a typical embodiment of the present invention, in the noise reduction means, the noise detection means is manually configured by using a plurality of voltage comparators, and the influence of noise generated by the digital circuit is wide banded. It is possible to measure in real time.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

A first embodiment of the present invention relating to a method of reducing the influence of noise in a mixed analog / digital integrated circuit will be described with reference to FIG.

In the integrated circuit 20, a circuit 21 that is affected by noise and a circuit 23 that generates noise are formed on the same integrated circuit board together with the noise reduction circuit 11 and the correction circuit 22. The noise affects the circuit 21 via the integrated circuit board. Circuit 23 for generating noise
Is a digital circuit that generally handles high-level and low-level signals, and the circuit 21 that is affected by noise is generally an analog circuit that handles weak analog signals. The noise reduction circuit 11 includes a noise detection circuit 1 and a noise correction amount calculation circuit 12. The noise detection circuit 1 is composed of, for example, a sampling type voltage comparator, detects noise by comparing input voltages V1 (1) to V1 (n) with a reference voltage V2, and outputs a high or low level signal. . The correction amount calculation circuit 12 determines the correction amount based on the magnitude of the noise detected by the noise detection circuit 1. The correction circuit 22 re-determines the correction amount by weighting according to the noise detection sensitivity of the analog circuit, and corrects the output result of the analog circuit.

Here, the magnitude of noise generated by the digital circuit changes depending on the scale of the digital circuit and the number of gates that operate synchronously. Therefore, it is effective to change the values of the input voltages V1 (1) to V1 (n), which are the reference for detecting the noise, according to the magnitude of the noise generated by the digital circuit. Therefore, the input voltage control circuit 14 is provided inside or outside the integrated circuit 20 and the magnitude of the input voltage is controlled to correct the analog circuit output according to the magnitude of noise generated by the digital circuit. Is effective.
For example, the input voltage control circuit 14 uses the correction amount calculation circuit 12
A large noise can be dealt with by controlling V1 (n) to be small when all the outputs of are high level, and setting V1 (1) to be large when all the outputs are low level. Also,
By controlling the voltage of V1 (2) to V1 (n-1), the transition point due to noise can be finely determined. By this method, the influence of noise can be measured with higher resolution, so that noise can be reduced more accurately. In addition,
The input voltage may be controlled by feedback at any time during circuit operation, or the circuit that generates noise may be operated before the operation of the circuit that is actually affected by noise. The input voltage may be set to a constant value to operate the circuit when the circuit is affected by noise.

Further, it is possible to operate the noise detection circuit in synchronization with the digital circuit, and by performing the equivalent operation, it is possible to investigate the influence of noise that occurs periodically. Analog for this /
A second embodiment of the present invention relating to a method for reducing the influence of noise in a digital mixed integrated circuit will be described with reference to FIG.

In the present embodiment, the noise detection circuit 1 is
The clock generation / adjustment circuit 15 operates in synchronization with the clock of the circuit 23 that generates noise. Further, the operation clock of the noise detection circuit 1 is set to a long or short cycle with respect to the clock of the circuit 23 that generates noise for a minute time Δt. As a result, the influence of noise can be sampled at intervals of Δt. For the circuit 22 that is affected by noise, a circuit 23 that generates noise is generated in advance.
By operating the and measuring the effect of noise, the effect of high frequency noise can be grasped in advance. According to the present embodiment, the influence of noise can be measured with high time resolution, and it is extremely effective in reducing noise in a wideband analog circuit.

Next, a third embodiment of the present invention relating to a method of correcting the effect of noise when the circuit affected by noise is a sampling type A / D converter will be described with reference to FIG. In the present embodiment, the A / D converter 24 operates in synchronization with the noise detection circuit 1 to obtain an output. As a result of matching the operation clock of the A / D converter 24 and the operation clock of the noise detection circuit 1, the noise detection circuit and the A / D converter will detect noise at substantially the same timing.
The noise detection circuit makes it possible to accurately grasp the influence of high frequency noise on the A / D converter. here,
When the influence of noise is large and it is difficult to correct the A / D converter, it is possible to specify to stop selecting the converted output data at the sampling point. Further, by holding the digital conversion value one clock before as data, it is possible to easily perform control such as interpolating and outputting the digital value at the sampling point.

Now, the noise correction method will be described in detail by taking a pipeline type A / D converter as an example. The circuit configuration is shown in FIG.

The pipeline type A / D converter 50 is an example of a sample and hold type circuit which utilizes a clock of a plurality of cycles and performs conversion while amplifying the residual. The pipeline type A / D converter in the present embodiment is composed of three stages of an upper 40, a middle 41, and a lower 42, and a sample / hold circuit 43, an A / D converter 44, and a D / A converter, respectively. It has 45 and an amplifier 46.

First, the operation of the A / D converter will be described. The analog input voltage Vin is quantized by the upper A / D 44a, and the difference voltage between the input voltage Vin and the D / A conversion result of the quantized value is amplified by m1 times by the amplifier 46a. The same conversion is performed using the difference voltage multiplied by m1 at the middle position 41 as the input voltage, and the difference voltage is
Amplify m2 times. Finally, the digital output Y is obtained by encoding the quantized value of each stage.

Next, the influence of noise on the pipeline type ADC and the noise detection and correction circuit will be described with reference to the timing chart shown in FIG. For convenience of explanation, only the process of acquiring one conversion data is shown in the figure. The noise affects the S / H circuit of the pipeline type A / D converter, the amplifier, the analog circuits of the A / D section and the D / A section, but here the S / H of each stage is used.
It is assumed that the noise generated at the timing t1, t2, and t3 when the circuit switches the signal from the sample detected to the state of saving the sample and the hold has the largest influence on the conversion accuracy of the pipeline type A / D converter, and the noise is detected. To do. If the substrate noise at this time is ΔV (t1), ΔV (t2), ΔV (t3), and the noise transfer coefficient of each S / H circuit is xyz, noise ΔY included in the conversion result is obtained.
Is represented by the following equation.

ΔY = m2 (m1xΔV (t1) + yΔV (t2)) + zΔV (t3) (1) The noise detected on the upper level is amplified by the amplifier gain, and has a large effect. I'm giving. Therefore, it is necessary to correct and subtract noise at each timing with a coefficient according to the amplification gain.

Next, a noise correction method using the noise detection circuit will be described. The noise detection circuit 1 has a pipeline A
When operating with the same clock as the / D converter, the noise at t1, t2, and t3 is measured with sensitivity a. The correction amount calculation circuit 12 calculates the coefficient from the circuit constant based on the equation (1) and secures it in the conversion table to obtain the correction amount. A / D correction circuit 2
If the correction amount is removed from the conversion result in 5, a correct output digital value can be obtained. In this method, a minute analog signal is measured as a digital amount and digitally corrected, so that it is hardly affected by other noise and the circuit configuration is easy.

In the above embodiment, the case where one circuit is affected by noise is shown, but it is also possible to realize it when there are a plurality of circuits. A fourth embodiment of the present invention for this purpose will be described with reference to FIG. In the present embodiment, based on the signal detected by the noise detection circuit 1, a correction amount for the circuits 21a and 21b affected by noise is obtained and correction is performed. The correction amount calculation circuit 12 may be one or plural.
Since only one detection circuit can be used, it is not necessary to increase the chip area. In addition, the circuit affected by noise is D /
The correction can be performed even with the A converter.

Here, as in the case where the circuit affected by noise is composed of a plurality of sample and hold circuits, it is effective to evaluate the influence of noise in advance as the operation becomes more complicated and determine the weighted coefficient. Is. Therefore, a fifth embodiment of the present invention relating to the method of determining the weighted coefficient will be described with reference to FIG. The weighted coefficient for the circuit 21 affected by noise gives a known signal to the integrated circuit substrate 30 as substrate noise, and the influence is given to the circuit 2 affected by noise.
1, for example, by the A / D converter 24 and the noise detection circuit 1, and can be determined from the ratio of their noise transmission amounts. As a signal input means, the capacitive coupling section 31 of the integrated circuit board 30 is used.
This can be realized by inputting a square wave into the and measuring the response characteristic to a high frequency signal, or by inputting a sine wave into the resistance coupling section 32, measuring the frequency characteristic and examining the response characteristic. Here, the signal generation circuit 3 that generates a square wave, a sine wave, or the like input to the capacitive coupling section 31 or the resistive coupling section 32.
3 may be formed on the same substrate or outside the integrated circuit.

Next, a sixth embodiment of the present invention relating to the noise reduction circuit described above will be described with reference to FIG. The noise reduction circuit 11 includes a noise detection circuit 1 and a correction amount calculation circuit 12. In this embodiment, a case where there are four noise detection circuits will be described as an example. The noise detection circuit 1 is composed of, for example, a sampling type voltage comparator, and receives the reference voltage V2 and the input voltages V1 (1) to V1 (4). Here, V1
(1) to V1 (4) and V2 are set apart from each other by the potential difference ΔV. The outputs O11 to O42 of the noise detection circuit 1 are input to the correction amount calculation circuit 12. The correction amount calculation circuit 12 calculates a correction amount for reducing the influence of noise from the detected noise level.

The operation of this circuit will be described with reference to FIG. When there is no noise, the output of the noise detection circuit is (1) in Fig. 9.
, The input voltage is higher than V2, V1 (1),
In V1 (2), the high level is lower than V2. V1 (3), V1
(4) indicates a low level. Assuming that the noise voltage Vn is equivalently input to V2, the output level of V1 (3) changes from low level to high level, as shown in (2) of FIG. This output result indicates that noise larger than ΔV is equivalently input to V2.
Therefore, by correcting the output result by -ΔV,
It is possible to reduce the influence of noise.

FIG. 10 shows the correction amount for the output level. By monitoring the comparator output level, FIG.
The correction amount for the input noise can be obtained as shown in (1). As a result, the influence of noise can be reduced. Further, it is not necessary that all the step widths of the input voltage are the same, and it is possible to set different values as shown in FIG. In this case, as shown in FIG. 10 (2), the correction amount can be changed according to the set value of the input voltage. In the present embodiment, the case where the noise reduction circuit is composed of four noise detection circuits is shown. However, if the number of noise detection circuits is increased and the potential difference ΔV is set small, noise can be detected with higher resolution. Is clear.

Next, a configuration example and basic operation of the voltage comparator used in the noise detection / detection circuit will be described with reference to FIG. The voltage comparator 2 is a circuit that compares the voltage values of the input voltage V1 input from the first input terminal and the reference voltage V2 input from the second input terminal, and operates according to the timing chart of FIG. First, when the switch 5 is in the ON state, the amplifier circuit 6 is in the auto-zero state and V1 is input. Next, when the switch 5 is in the off state, the amplifier circuit 6 is in the comparison state, and V2 is input. V1 and V2
Is amplified to Vout, and Vout, that is, the comparison result is output from OUT1 as a high / low level, that is, a digital value via the latch circuit 7.
Here, the influence of noise is great at the timing T1 at which the control clock φ1 of the auto-zero switch 5 switches from a high level to a low level and at the final comparison timing T2, and the noise at these timings T1 and T2 is the voltage comparator. The comparison result of 2 is affected and held in the latch circuit 7.

Here, the gain of the amplifier circuit 5 is G, the noise transfer coefficient at the time of auto-zero, a and b at the time of comparison, and times T1 and T2.
Assuming that the influence of noise in ΔV (1) and ΔV (2) in FIG.

Vout = G {(V1-aΔV (1))-(V2-bΔV (2))} (2) Here, if V1 = V2, Vout = G {-aΔV ( 1) + b · ΔV (2)} (3) holds.

When this voltage comparator is used, T
Since the effects of noise at 1 and T2 are combined and output as a noise component, there is a problem that the effects of noise at each timing cannot be measured separately.

A seventh embodiment of the present invention for solving this problem will be described with reference to FIG. Generally, the noise transfer coefficient at the time of auto zero has a wider band than that at the time of comparison and is excellent for detecting high frequency noise. Therefore, it is effective to obtain a sampling value of noise by selectively detecting noise at the time of auto-zero. In the present embodiment, the capacitance C1 is connected to the input section of the amplifier circuit 6 through the switch 8 and the ground, and the output section of the amplification circuit is connected through the switch 9 and the capacitance C2 to the ground. Switch 8 and switch 9 are off when the comparator is auto zero,
It is controlled so that it is turned on during comparison. By connecting capacitors C1 and C2 to the ground during comparison,
Since the high frequency noise measured at the time of comparison is absorbed by the capacitance, this effect can be reduced. As a result, the noise sampling value at the time of auto-zero is selectively obtained. Although FIG. 14 shows the case where the two capacitors C1 and C2 are connected, the influence of the high frequency noise measured at the time of comparison can be reduced by using only C1 or C2. Further, in the present embodiment, the case where the switch 8 or the switch 9 is in the off state at the time of auto zero and the on state at the time of comparison is shown. However, it is controlled so that the switch 8 or the switch 9 is in the on state at the time of auto zero and the off state at the time of comparison. It is also possible to reduce the influence of high-frequency noise that is sometimes measured and detect noise during comparison. Furthermore, C1 and C2 may be realized by a mirror capacitor combined with an amplifier circuit. In this case, since it is possible to create a larger capacitance value, the effect of reducing the influence of high frequency noise becomes greater.

Here, when the input or output of the inverter is connected to the ground via the capacitor, if the offset level, that is, the initial voltage of the capacitor deviates from that of the Vout terminal, it takes time until the steady state is set, and the conversion is performed. May slow down. An eighth embodiment of the present invention for solving this problem will be described with reference to FIG. In the present embodiment, only the capacitance of C2 is described, and the case where the influence of high frequency noise measured during comparison is reduced is shown. Vou
An auto-zero inverter 19 having an auto-zero switch is connected to t via a switch 9. The inverter 19 for auto-zero is in the ON state between the input and output terminals when the switch 9 is not connected, and is in the OFF state when the switch 9 is connected.
The initial voltage and offset level of C2 are set to the threshold voltage of the inverter 19 for auto zero. If the inverter 19 for auto-zero is made equal to, for example, the inverter that constitutes the amplifier circuit 6, Vo when the capacitor is connected and not connected
The offset level of ut can be set equally. As a result, it is possible to prevent the setting time from increasing due to the level change and to secure the conversion time of the voltage comparator.

Next, details of noise measurement by the voltage comparator will be described with reference to the pseudo noise waveform shown in FIG. Here, p to z represent sampling values of the noise waveform generated by the digital circuit operation. The noise generated by the operation of the digital circuit is considered to be a high-frequency ringing waveform that occurs at the rising and falling edges of the clock for driving the digital circuit and has peaking immediately after the change. When detecting noise with one voltage comparator,
As shown in (1) of FIG. 16, noise is measured as a differential voltage, for example, −ap + bq, at the time of comparison when φ1 becomes low level. By using the noise detection circuit shown in the seventh or eighth embodiment of the present invention, as shown in FIG. 16 (2), it is possible to selectively measure the noise at the time of auto-zero or at the time of comparison.

Here, when the noise detection circuit is operated by using only the clock having the same timing as that of the circuit affected by noise, only the influence of noise at the time of comparison or at the time of auto-zero can be examined. If the circuit affected by noise is a sampling type circuit that performs a complicated operation, it is useful to detect and correct the effect of noise at both auto-zero and comparison. A ninth embodiment of the present invention for this purpose will be described with reference to FIG. In this embodiment, the noise detection circuit 1 is composed of voltage comparators 2a and 2b controlled by clocks φ1 and φ2, respectively. The input voltages V1 and V2 are both input to the voltage comparators 2a and 2b, and the comparison results OUT1 and OUT2 are output from the noise detection circuit 1.

The operation of this embodiment will be described with reference to the timing chart shown in FIG. The voltage comparator 2a and the voltage comparator 2b operate in opposite phases by φ1 and φ2, and both V1 is input during auto-zero and V2 is input during comparison.
Here, one operation of the noise detection circuit 1 will be shown. First, the voltage comparator 2a measures the difference voltage between V1 and V2 captured at the timing of T1 and T2, and outputs it as OUT1. Similarly, in the voltage comparator 2b, the voltage comparator 2a
The difference voltage between V1 and V2 captured at the timing of T2 and T3 with a delay of a half cycle is measured and output as OUT2. By thus configuring the noise detection circuit 1 with the two voltage comparators, it is possible to detect noise for each half cycle. As a result, as shown in FIGS. 16 (3) and (4), it is possible to measure the noise delayed by a half cycle from φ1 at the timing of φ2, for example, −aq. As a result, it becomes possible to measure noise at twice the sampling rate as compared with the case of using one voltage comparator.

Since the time resolution can be improved by operating the plurality of voltage comparators with the phases shifted as shown in (2) of FIG. 18, the noise waveform can be measured at a high sampling rate.

Further, a tenth embodiment of the present invention relating to a method of converting a measurement result into a value corresponding to a noise sampling value will be described with reference to FIG. In the present embodiment, the outputs OUT1 and OUT2 of the noise detection circuit 1 are added by the cumulative addition circuit 10 and output. By sequentially adding the outputs of the voltage comparator 2a and the voltage comparator 2b shown in FIG. 16 (4), the sampling value becomes the initial value −ap and the final value bz, and the intermediate sampling as shown in FIG. 16 (5). The sum is (ab) times the value. If the noise transfer coefficients a and b are equal, the noise sampling value can be obtained as a change amount from the initial value. The present embodiment can also be realized by the circuit shown in FIG. FIG.
At 0, outputs Vout1 and Vout of the voltage comparators 2a and 2b
After out2 is added by the cumulative addition circuit 10, the latch circuit sets it to a digital level and holds it. The cumulative addition circuit 10 can be composed of, for example, a switched capacitor circuit. According to this circuit configuration, one latch circuit can be configured for two voltage comparators.

Although the voltage comparator in the above embodiment is composed of one amplifier circuit and a latch circuit, there is no problem even if the amplifier circuit is further provided in the preceding stage of the latch circuit in order to improve the resolution. Absent.

[0051]

According to the typical embodiment of the present invention, it is possible to correct the influence of noise on a circuit affected by noise and improve the noise resistance of the circuit.

Further, according to the representative embodiment of the present invention, noise is detected and corrected in synchronization with the clock signal, so that it is possible to detect and correct noise with high accuracy.

Further, according to the representative embodiment of the present invention, since the arithmetic circuit can perform the weighting correction according to the characteristics of the circuit affected by noise, the correction can be performed appropriately according to the characteristics of the circuit. It becomes possible.

Further, according to the typical embodiment of the present invention, it is possible to reduce the influence of noise in the analog / digital conversion circuit of the pipeline type or the like.

Further, according to the representative embodiment of the present invention, the influence of noise generated by the digital circuit on the analog circuit can be measured in real time, so that the influence of noise can be known and its correction or reduction can be performed. It can be carried out.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a second embodiment of the present invention.

FIG. 3 is a diagram illustrating a third embodiment of the present invention.

FIG. 4 is a diagram illustrating a method of correcting noise of an A / D converter.

FIG. 5 is a diagram illustrating timings of an A / D converter and a miscellaneous detection correction circuit.

FIG. 6 is a diagram illustrating a fourth embodiment of the present invention.

FIG. 7 is a diagram illustrating a fifth embodiment of the present invention.

FIG. 8 is a diagram illustrating a sixth embodiment of the present invention.

FIG. 9 is a diagram for explaining the operation of the sixth embodiment of the present invention.

FIG. 10 is a diagram for explaining the operation of the sixth embodiment of the present invention.

FIG. 11 is a diagram for explaining the operation of the sixth embodiment of the present invention.

FIG. 12 is a diagram showing a configuration of a voltage comparator for detecting noise.

FIG. 13 is a diagram illustrating an operation timing of a voltage comparator.

FIG. 14 is a diagram illustrating a seventh embodiment of the present invention.

FIG. 15 is a diagram illustrating an eighth embodiment of the present invention.

FIG. 16 is a diagram illustrating a noise measuring method according to the present invention.

FIG. 17 is a diagram for explaining the ninth embodiment of the present invention.

FIG. 18 is a diagram illustrating operation timing of the ninth embodiment of the present invention.

FIG. 19 is a diagram illustrating a tenth embodiment of the present invention.

FIG. 20 is a diagram illustrating a tenth embodiment of the present invention.

[Explanation of symbols]

1 ... Noise detection circuit, 2 ... Voltage comparator, 3, 4, 5 ... Switch, 6 ... Amplification circuit, 7 ... Latch circuit, 8, 9 ... Switch, 10 ... Addition circuit, 11 ... Noise reduction circuit, 12 ... Correction Quantity arithmetic circuit, 13 ... Clock generation circuit, 14 ... Input voltage control circuit, 15 ... Clock generation / control circuit, 19 ... Auto-zero inverter, 20 ... Integrated circuit, 21 ... Circuit affected by noise, 22 ... Correction circuit, 23 ... Noise generating circuit, 24 ... A / D converter, 25 ... A / D converter correction circuit, 30 ... Integrated circuit board, 31 ... Capacitive coupling section, 32 ...
Resistance coupling section, 33 ... Signal generating circuit, 40 ... Upper level, 41 ...
Middle, 42 ... Lower, 43 ... Sample hold circuit, 44
... A / D converter, 45 ... D / A converter, 46 ... Amplifier,
47 ... Encoder, 50 ... Pipeline type A / D converter.

Claims (27)

[Claims] 1. A first circuit which operates in synchronization with a clock, a second circuit which is affected by noise generated by the first circuit, and noise which detects noise generated by the first circuit. A detection circuit and an arithmetic circuit that calculates a correction amount in response to the output of the noise detection circuit, and the output of the second circuit is configured to be corrected by the output of the arithmetic circuit. Semiconductor integrated circuit device. 2. The semiconductor integrated circuit device according to claim 1, wherein the first circuit is a circuit that generates substrate noise in synchronization with the clock signal. 3. The semiconductor integrated circuit device according to claim 1, wherein the noise detection circuit is configured to detect the noise in synchronization with the clock signal. 4. The semiconductor integrated circuit according to claim 1, wherein the arithmetic circuit is configured to perform correction by weighting according to the noise detection sensitivity of the second circuit. Circuit device. 5. The semiconductor integrated circuit device according to claim 1, wherein the noise detection circuit is driven at a timing deviated by a predetermined time from a rise or a fall of the clock. 6. The semiconductor integrated circuit device further comprises a clock generation circuit for supplying a clock signal to both the noise detection circuit and the first circuit so that the operation timing of the circuit is synchronized with that of the first circuit. The semiconductor integrated circuit device according to any one of claims 1 to 4. 7. The noise detecting means includes a sampling type voltage comparator formed on the same semiconductor substrate as the first and second circuits. Item 7. A semiconductor integrated circuit device according to item 6. 8. The noise detecting means has first, second and third voltage comparators formed on the same semiconductor substrate as the first and second circuits, and the first and second voltage comparators are provided. 2, a reference voltage is commonly applied to one input of the third voltage comparator, a voltage smaller than the reference signal is applied to the other input of the first voltage comparator, and the third voltage is applied. 7. The semiconductor integrated circuit device according to claim 1, wherein a voltage higher than the reference signal is applied to the other input of the comparator. 9. The first, second and third voltage comparators are sampling type voltage comparators.
13. The semiconductor integrated circuit device according to claim 1. 10. A first circuit which generates noise in synchronization with a clock signal, a second circuit which is affected by the noise and is formed on the same semiconductor substrate as the first circuit, Means for reducing the influence of noise on the second circuit, the means for weighting according to the noise detection sensitivity of the second circuit to correct the output of the second circuit. A semiconductor integrated circuit device having a structure. 11. The semiconductor integrated circuit device according to claim 10, wherein the noise is substrate noise generated by the first circuit in synchronization with the clock. 12. The semiconductor integrated circuit device according to claim 1, further comprising means for driving the clock of the noise reduction means with a time lag from the drive clock of the first circuit. 12. A semiconductor integrated circuit device according to claim 10 or 11, further comprising means for holding an output of the noise reduction circuit in time. 13. The semiconductor integrated circuit device further comprises a clock generating means for synchronizing a clock of the second circuit and a clock of the reducing means, and a weighting according to a noise detection sensitivity of the second circuit for correction. And a correction circuit for performing
0 or the semiconductor integrated circuit device according to claim 11. 14. The semiconductor integrated circuit device according to claim 10, further comprising a resistance junction portion for inputting a signal from the outside. 15. The semiconductor integrated circuit device according to claim 10 or 11, wherein the semiconductor integrated circuit device further includes a capacitive junction portion for inputting a signal from the outside. 16. The semiconductor integrated circuit device according to claim 13, wherein said means for reducing noise includes a noise detection circuit composed of a voltage comparator. 17. The semiconductor integrated circuit device according to claim 16, further comprising means for controlling a voltage value of one input signal of the voltage comparator. 18. A first circuit, an analog / digital conversion circuit that is affected by noise generated by the first circuit, a noise detection circuit that detects noise generated by the first circuit, and the noise. A semiconductor integrated circuit device comprising: an arithmetic circuit that calculates a correction amount in response to an output of a detection circuit, and correcting an output value of the analog / digital conversion circuit by an output signal of the arithmetic circuit. 19. The semiconductor integrated circuit device according to claim 18, wherein the correction amount is calculated so as to have a value corresponding to a noise transfer function of the analog / digital conversion circuit. 20. The analog / digital conversion circuit includes a plurality of analog / digital conversion units, and the arithmetic circuit is configured to calculate a correction amount corresponding to a noise transfer function of each analog / digital conversion unit. 19. The semiconductor integrated circuit device according to claim 18, wherein: 21. The semiconductor integrated circuit device according to claim 20, wherein the analog / digital conversion circuit is a pipeline type analog / digital conversion circuit composed of a plurality of analog / digital conversion units. 22. The noise detection circuit is configured to include a sampling type voltage comparator formed on the same semiconductor substrate as the analog / digital conversion circuit. The semiconductor integrated circuit device described. 23. The noise detection circuit has first, second and third voltage comparators formed on the same semiconductor substrate as the analog / digital conversion circuit, and the first, second, and third voltage comparators are provided. A reference voltage is commonly applied to one input of the third voltage comparator, a voltage smaller than the reference signal is applied to the other input of the first voltage comparator, and the third voltage comparator is applied. 22. The semiconductor integrated circuit device according to claim 18, wherein a voltage larger than the reference signal is applied to the other input of the semiconductor integrated circuit device. 24. The semiconductor integrated circuit device according to claim 23, wherein the first, second and third voltage comparators are sampling type voltage comparators. 25. A first circuit that operates in synchronization with a clock, a second circuit that has a sampling type comparator circuit and is affected by noise generated by the first circuit, and the first circuit. In a semiconductor integrated circuit device having a noise detection circuit for detecting generated noise and a calculation circuit for calculating a correction amount in response to the output of the noise detection circuit, in the calculation of the correction amount, the auto-zero of the sampling type comparison circuit is performed. A method for reducing noise in a semiconductor integrated circuit, wherein a correction amount is calculated by applying a weight corresponding to noise detection sensitivity at the time of comparison and the output of the second circuit is corrected. 26. A first circuit which operates in synchronization with a clock, a second circuit which has a sampling type comparator circuit and which is affected by noise generated by the first circuit, and the first circuit. A semiconductor integrated circuit device having a noise detection circuit for detecting generated noise, a calculation circuit for calculating a correction amount in response to an output of the noise detection circuit, and a capacitance junction receiving a signal from the outside. Pseudo noise is input to obtain noise transfer coefficients of the second circuit and the noise detection circuit, a noise correction amount is obtained in advance, and the output signal of the second circuit is corrected based on the noise correction amount. A method for reducing noise in a semiconductor integrated circuit device characterized. 27. A first circuit, which operates in synchronization with a clock, a second circuit having a sampling type comparator circuit, which is affected by noise generated by the first circuit, and the first circuit. In a semiconductor integrated circuit device having a noise detection circuit for detecting generated noise, an arithmetic circuit for calculating a correction amount in response to an output of the noise detection circuit, and a resistance junction portion receiving a signal from the outside, the resistance junction portion Pseudo noise is input from the above, noise transfer coefficients of the second circuit and the noise detection circuit are obtained, a noise correction amount is obtained in advance, and the output signal of the second circuit is corrected based on the noise correction amount. A method for reducing noise in a semiconductor integrated circuit device characterized.