SU930627A1 - Frequency multiplier - Google Patents

Description

The invention relates to radio engineering and may be used to multiply the frequency of the pulse signals in the measurements of the frequency and phase of low-frequency signals, as well as the shape of periodic signals. A frequency multiplier is known, containing a series of short pulses, a delay unit, a first pulse counter, a first memory block whose recording control input is connected to the output of a short pulse former, a counter counter and an OR element, the second input of which is connected to the output of the former short pulses, and the output with the control input of the counting counter, the clock generator, as well as the first frequency divider, the output of which is combined with the counting input of the first pulse counter l. The drawback of the device is the impossibility of increasing the frequency multiplying range without increasing the capacity of the pulse counter. The purpose of the invention is to increase the range of multiplied frequencies. For this purpose, a frequency multiplier comprising a serially connected short pulse shaper, a delay unit, a first pulse counter, a memory unit, a recording control input; which is connected to the output of the short pulse generator, the countdown counter and the OR element, the second input of which is connected to the output of the short pulse generator, and the output to the recording control input of the counting counter, clock pulse generator, and the first frequency divider whose output is connected the counting input of the first pulse counter, entered the second frequency divider, the input of which is connected to the output of the clock pulse generator, the first and second milenders, the inputs of which are connected to the corresponding The outputs of the second frequency divider, and the outputs, respectively, with the input of the first frequency divider and with the counting input of the countdown counter, as well as serially connected second pulse counter, the outputs of which are also connected to the control inputs of the first multiplexer, and the second memory block, whose outputs connected to the control inputs of the second multiplexer, and the recording control input to the output of the short pulse generator, while the high bit output of the first pulse counting is connected to the The first input of the pulse counter and the counting input of the second pulse counter, and the zero-setting second counter of the pulse counter is connected to the output of the delay unit. The drawing shows a structural electrical circuit of the proposed frequency multiplier. The frequency multiplier contains a pulse counter 1, a first memory block 2, a count counter 3, a clock generator 4, a first frequency divider 5, a shaper 6 short pulses, a delay unit 7, an OR element 8, a second frequency divider 9 first multiplexer 10, the second counter 11, the second memory block 12, into the second GZ multiplexer. The frequency multiplier works as follows. At the beginning of the input signal period, the pulse counter 1 is set to the zero state by a short pulse from the output of the imaging unit 6 through the input delay setting 7 of the zero setting of counter 1. After that, the counter 1 begins to fill with the pulses with the frequency of the pulse repetition frequency of the generator 4; K - multiplication factor. The capacity of the counter 1 is chosen equal to twice the capacity, J where is the multiplication error. . If the period of the multiplied frequency T is 2%, then counter 1 is filled with frequency pulses fo / K to value 2, after which the overflow pulse arrives at the counting input of counter 11 and the set input of counter 1, while counter 1 is set to the state when the number N is written. Counter 11 controls the operation of multiplexer 10, and after the first overflow of counter 1, the frequency of the multiplexer 10 begins to arrive. The frequency at the counting input of counter 1 begins - frequency 4 eill-eifi-. . 1 k 2K The subsequent overflow pulses of counter 1 change the state of counter 11, while the output of multiplexer 1O begins to receive a frequency of 1 lir.io and a counter input of the counter of 1 begins to receive a frequency. 1 "where h is the number of pulses of the counter 1 full charge. The process of changing the frequency f delivered to. divider 5 frequency input, repeats until the end of the signal period. In the Number of Switches of the counter 11 (and, correspondingly, frequency 1) is. T. R . x to «-tr-- sp at the end of the period of the input frequency in the counter 1 will be recorded the number of N-T - 2. K BH. -Ti from counter 1 This number is transferred to memory block 2 and to counter 3 by a short pulse coming from the output of a form M-level 6 to the inputs of a block 2, -pam and counter 3. By the same pulse, the number of from the counter 11 to the memory block 12. In the next period, the counting input of the counter 3 enters the frequency f and the number N is calculated from the counter 3 through the time VI, J On. The output of counter 3 is a short pulse, the leading edge of which is information from memory block 2.

t number N) is counted again.: cnc 3.

Thus, at the output of the frequency multiplier (output of the counter 3), the TC pulses in, the frequency of which is repeated

out and out

At the end of the first period of the input frequency after overwriting the numbers of counter 1 into memory block 2 and counter 3, as well as from counter 11 into the block. The 12 memories with the pulse from the output of the delay unit 7, the counters 1 and 11 are set to the zero state. After that, the counter input 1 starts to flow to the counter.

  0 / k

the process of changing the frequency f occurs as described above.

In the proposed device, the range of multiplied Bq of frequencies is increased, as well as the range of multiplication coefficients, and the error of multiplication is reduced with a significant gain in equipment.

Claims (1)

1. TIIZR, 1975, No. 9, Vol. 63, p. 116-117 (prototype).