SU1292177A1 - Pulse repetition frequency divider with variable countdown - Google Patents

Abstract

The invention can be used in digital frequency synthesizers. The purpose of the invention is to simplify the process of setting the division factor while maintaining speed. The frequency divider contains a controlled high-frequency divider 2 frequencies with two values of the division coefficients (s), n-bit low-frequency divider 3 frequencies, containing in each bit U th

Description

1292177

de one low-frequency counting of flip-flops 9 and 10, element 12

4-7, trigger 8, element 11 and p-bit identification block 14. The divider 13 frequency nine allows you to achieve your goal. 2 Il.

The invention relates to a pulse technique and can be used in digital frequency synthesizers.

The purpose of the invention is to simplify the process of setting the division ratio while maintaining speed.

FIG. 1 shows an electrical structural diagram of a pulse frequency divider with a variable division factor; in fig. 2 - timing diagrams explaining the operation of the device (for example, division with a factor).

The device contains an input bus 1 connected to the counting frequency of the controlled high-frequency divider.

2 frequencies with two values of the division factors (s), p-bit low-frequency divider

3 frequencies, containing in each discharge one low-frequency counter 4-7, first, second and third trigger 8-10, first and second elements

Both 11 and 12, the frequency divider 13 by de b (the division factor Kd, 9) and the n-bit identification block 14.

The counting inputs of low-frequency counters 4 and 5 are connected together and form the counting input of an n-bit low-frequency divider 3 frequencies, the outputs of low-frequency counters 4-7 are connected bitwise to the corresponding inputs of the recognition unit 14, the output of the first bit of the recognition unit 14 is connected to S - to the input of the first trigger 8, the output of the second bit of the identification unit 14 is connected to the S-input of the second trigger 9, the R-inputs of the first and second 8 and 9 flip-flops are connected to the output of the first element I 11, to the output bus 15 and to the installation input to O counters 6 and 7 p-bit low-frequency divider 3 frequencies, the first output of the first trigger 8 is connected to the control input of the controlled high-frequency divider 2 frequency.

and divider 13, frequency nine, allows to achieve the goal. 2 Il.

the second output - with the installation input in About counter 4, the first inputs of the elements. Both 11 and 12 are connected to the output of a controlled high frequency divider 2 frequency, connected to the counting input of an n-bit low frequency divider 3 frequency, the second input of the second element And 12 is connected to the output of the second trigger 9 and k. the input of the installation of the counter 5, the output of the second element I 12 is connected to a countable input of the frequency divider 13 (division factor Ka-9) and the R-input of the third trigger lO, whose S input is connected to the output of the frequency divider 13 (division factor), connected to the counting input of the counter 6, the output of the third trigger 10 is connected to the input of the frequency divider 13 (dividing factor) in the n-bit low-frequency divider 3 frequency in the frequency counter three to the n-th bit (respectively, counters 4 and 7) are connected successively -th bits Bloggs AIS 14 are connected respectively to the second to (n + 1) -th inputs of the first AND gate 11.

In block 14, all bits have the same circuit construction, for example, each bit contains a 1-2-4-8 binary code decoder into the decimal, the inputs of which are connected to the trigger outputs of the corresponding bit of the n-bit low frequency divider 3 frequencies, and the outputs are switched using a switch, the output of which is connected to the corresponding input of the element

.And ii. The switch can be replaced by a multiplexer, providing remote control of the device

Consider the operation of the device on the example of obtaining the division ratio K.-232,

312921

Divider 2 has two possible values of the division factors, and. Moreover, when trigger 8 is set to the zero (initial) position, the divider 2 has, and when the trigger 8 is switched, it is in the one state.

L1

Until time t (until the input pulses are fed to bus 1), all counters 4-7, dividers 2, and triggers 8-10 are in the zero (initial) state, in which divider 2 has a conversion factor, and in addition , in block 14, the set conversion factor is set by (bit) switches;

The specified value of the division factor K can be represented as

K-232 2 10 ° + 3-10 + 2-.10.

To obtain the division factor in the device, the switches of block 14 should be set to the following positions: for counter 4 (first bit) - K 2, for counter 5 (second bit) -, for counter 6 (third bit) -, for counter 7 (fourth bit) -, and also (generally) for counters of subsequent bits - K, K (,,., ,, ,,

When the input pulses are fed to bus 1, divider 2 starts counting them and during the time ut, an output pulse appears every time eleven inputs and outputs are read (Fig. 3, and the latter arrives at counting input of divider 3, in which the counters 4 and the number K.2 of the pulses at the output of the first bit of the block 14 turn on a signal that switches the trigger 8 to one state (Fig. 3.6), at which input installation in O, counter 4 is set to O and stops further operation, Tel divider 2 is switched (by the control input) to work with the dividing ratio mode ends at this first time interval &.. t, At this point The apparatus reads The relative number of pulses A, K.

With the beginning of the second time interval atj, the divisor 2 has. With

7 4

In this case, counter 5 continues its work on counting pulses from the output of divider 2 and calculates one more (the third in time from the time tg) pulse. After counting this pulse, the counter 5 has the number of counted pulses equal to the number, and at the output of the second bit of the block 14. A signal that switches the trigger 9 into one state is shown (Fig. 3, c). To this point in time since the start of the interval and tj, the device counts the number A of the input pulses from the bus 1.

After the trigger 9 is switched to the single state, the further operation of the counter 5 (during the remaining interval time and t) is prohibited (at the installation input to the O), and a resolution signal appears at the second input of the And 12 element. In this case, the pulses from the output of the divider 2 begin to flow through the element I 12 (Fig. 3, d) to the counting input of the divider 13. The latter has a fixed conversion factor. After counting by the divider, 13 nine pulses from the output of element 12 or, together with the divider 2, the numbers A, K, .- C.Y.-9

five /

90 input pulses from bus 1 at the output of the body of bodies 13, a first pulse appears (Fig. 3, e), which is considered to be counter 6 and at the same time switches trigger 10 to a single connection, which prohibits (at the installation input to O) further operation dekhsh- bodies 13. In this case, the next pulse from the output of the element I 12 will switch trigger 10 to the zero (initial) state. From the moment switching of the trigger 10 to the unit state until the moment of its return to the initial position, the device will calculate the number A.К.10 of the input pulses from the bus 1.

t g

After switching 11 and trigger 10 into a similar state, the divider 13 starts working again, at the output (after counting the number of pulses post-discharge from the output of the element 12, or after counting together with the divider 2, the number A of C 1. input and fflylc from bus 1) the second pulse (Fig. 3, d), which is considered to be counter 6 and at the same time switches trigger 10 repeatedly to one state, prohibiting further operation of divider 13. Since the second in the account im 51292177 arrived at the counting input of counter 6

pulse from the output of divider 13, then count 6 will finish counting the number of pulses. In this case, at the output of the third bit of the block 14, the Vitsat signal (Fig. 3, e) acts as a resolving element 11, which has warning signals on the third and subsequent inputs, which arrived before

-Sh

5 F

The time t from the outputs of the corresponding Lok 14 bit switches (when a given division factor is set). Moreover, the counters of the fourth and subsequent bits have zero conversion factors (...) And do not participate in the operation of the device.

Consequently, when the next pulse appears at the output of divider 2, the last pulse will go through element 12 to the R input of trigger 10 and will switch it to the zero (initial) state and, moreover, will go to the first input of element 11, which will trigger as on all its inputs there are permissive signals. In this case, the output pulse at the output of the element 11 and on the bus 15 is as follows (Fig. 3, g).

The appearance of a pulse on bus 15 corresponds to the moment when the interval ut ends. In this case, from the moment of the last switching of the trigger 10 to the unit state until the moment of its switching to the zero state, the device calculates the number A of the input pulses from the bus 1.

Thus, from the time t (the start of ut,) and until the end of the interval ut (the appearance of a pulse on bus 15), the device calculates the number

A A, + A, + A, + A4 + A5. + Ag

22 + 10 + 90 + 10 + 90 + 10 232 input pulses and, therefore, will provide a given conversion factor. Analytically described algorithm of the device can be represented as.

, + K (iq-K,) + V Ka + K (K +1) (K, -1), K2-K "K, +, + K" K, -K.K, -K "+ K.

Where, after casting like, we get

K () K ,, (). Further, taking into account the values of Ka.9, Kg, n, we have

K K, + K1 .. 10.

15 h. n 20 p

25 l

30 d

35 n

40 d

- x

45 n

50 p

55 and

A pulse on bus 15 returns the entire device to its original state and the 1TC repeat cycle.

Claims (1)

5 claims A variable division pulse frequency divider containing a controlled high-frequency frequency divider with two values of the division factor, a n-bit low-frequency frequency divider, a n-bit identification block, the bit inputs of which are connected to the outputs of the counters of the corresponding n bits -discharge low-frequency divider, the output of the first bit of the identification block is connected to the S input of the first trigger, the R input of which is connected to the output of the first element I, to the installation inputs in O connected in series with the third to the nth bits of the n-bit low-frequency splitter and 5 l of the frequency and output bus, the first output of the first trigger is connected to the control input of the controlled high-frequency frequency divider, the output of which is connected to the counting input of the n-bit low-frequency frequency divider and with the first input of the first element I, the input with the input bus, characterized in that, in order to simplify the process of setting the division factor while maintaining speed, a frequency divider of nine , Second and third flip-flops, a second AND gate having a first input connected to the home vyho0 controllably high frequency divider, the second input - with the output of the second trigger and with the additional input of the installation in O of the second discharge counter of the n-discharge 5 low-frequency frequency divider, S-input of the second trigger is connected to the output of the second bit of the identification block, R-input - to the output of the first element I, the inputs of which are from the second 0 to p-th are connected to the outputs, respectively, from the third to (n + 1) -th bits of the identification block, the output of the second element I is connected to the counting input of the frequency divider by nine 55 and with the R input of the third trigger, the S input of which is connected to the output of the frequency divider by nine and to the counting input of the third discharge counter of the n discharge of the low frequency frequency divider, the output of the third trigger is connected to the input of the installation on the frequency divider by nine In this case, the counting inputs of the counters of the first and second bits of the n-bit low-frequency frequency divider are connected Compiler A. Sokolov Editor S. Pekar Tehred I. Popovich. Proofreader A. Ilyin Order 286/58 Circulation 902 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab, 4/5 Production and Printing Enterprise, Uzhgorod, ul. Design, 4. 1292177 - 8 You are with a counting input of a low-frequency frequency divider, while the second output of the first trigger is connected to the input of the installation in O of the first-digit counter of the n-bit low frequency frequency divider.