SU1396277A1 - Frequency divider with variable countdown - Google Patents

Abstract

The invention relates to a pulse technique and can be used in frequency synthesizers. The purpose of the invention — extending the functionality — is achieved by allowing a discrete change in the division factor relative to a predetermined value while simultaneously maintaining the reliability of the device in the recording mode of control of these codes. For this, the multiplexer 8, the dividing factor manipulation bus 9, two RS-flip-flops 1 and 14, two D-flip-flops 12 and 16, the OR 13 element, and the reset 18 bus are added to the divider. The device also contains, counter I pulses, input bus 2, D-flip-flop 3, RS-flip-flop 4, elements AND-NO 5 and 6, bus 7, 10, 15, element OR-NOT 17, inverter 19. On bus 15 divider formed by the action of the fronts of the output signal pulse duration equal to the period of the input signal. The range of the discrete change in the division ratio of the device relative to a predetermined division ratio is determined from the expression provided in the description of the invention. 1 pe. S with:

Description

Od SO GO

The invention relates to a pulsed technique and can be used in frequency synthesizers.

The purpose of the invention is the expansion of

rational capabilities due to the possibility of a discrete change in the division factor relative to the preset one, while at the same time increasing the reliability of the device in the recording mode of control moves,

The drawing shows the electrical circuit of the device.

The variable divider frequency divider contains a pulse counter 15 1, the counting input of which is connected to the input bus 2 and the clock input of the first D-flip-flop 3, the first RS flip-flop 4, the single input of which is connected to the output of the first 20 OR-NOT 5 element, the inputs of which are connected to the direct outputs of the corresponding high-order bits of the pulse counter 1, the second element of the RUI-NOT b, the output of which is connected to the information input of the first D-flip-flop 3, inu 7 control the high bits

pulse counter 1, which is connected to its corresponding information inputs, multiplexer 8, 30

the outputs of which are connected to the information inputs of the lower bits of the pulse counter 1, the first group of inputs - with the bus 9 manipulation division ratio, the second group of inputs - with the bus 10 control the younger bits of the counter 1 pulses. The control input is connected to the direct output of the second RS flip-flop 11, the zero and single inputs of which are connected AQ with the inverse outputs of the first and second D-flip-flops 3 and 12, respectively. The front output of the first D-flip-flop 3 is connected to the first input of the OR 13 and with the zero inputs of the first and the third 14 RS-flip-flops, as well as with the output bus 15. The second input of the ISh 13 element is connected to the single input of the third RS-flip-flop 14 and to the direct output of the second D-flip-flop 12, the output to the enable input records of the first bits of the counter 1 pulses, the resolution input the high-order records of which are connected to the direct output of the third D-flip-flop 16, the clock input of which is connected to the input bus, 2 and the clock input of the second D-flip-flop 12, the information input of which is connected to the output of the 35

50

0 5

0

Q -

five

0

of the second element of the IPI-NOT 17. The single input of the first 3, the zero input of the second 12 and the single input of the third 16 D-flip-flops are connected to the fault bus 18. The direct output of the first KZ-flip-flop 4 is connected to the information input of the third D-flip-flop 16. The first input of the second element OR-NOT 6 is connected to the inverse output of the first bit of the counter 1 pulses, the remaining inputs - to the direct outputs of the lower bits, except the first , counter.a 1 pulses. The auxiliary input is connected to the inverse output of the first RS trigger 4 and to the first input of the third element OR NOT 17, the second input of which is connected to the direct output of the third RS trigger 14, the third input to the inverse output of the first discharge of the pulse counter 1, the fourth the input is via the inverter 19, and the remaining inputs are directly, with direct outputs of the lower bits, except for the first, counter 1 pulses.

The divider works in a specific way.

Under the action of 1, coming from bus 18 to / inputs of D-flip-flops 3, 12, and 16, on the inverse output of RS-flip-flop 4, the recording inputs of the lower VI and older V2 bits of counter 1 are set to 1, elements 6 and 17 are locked , counter 1 enters a state in which its counting input is closed, and a code is preset coming from bus 10 through multiplexer 8 and from bus 7. By removing the reset signal from bus 18 and applying a subsequent pulse to bus 2 on. bus 15, at the output of RS flip-flop P, at the inputs of recording resolution VI and V2. Counter 1 appears, Counter 1 turns on and starts counting the input pulses from the code set in it. The information inputs of the lower bits of counter 1 receive signals from pin 9 through multiplexer 8. From this point on, we begin the conditional counting of input pulses. After all outputs of the higher bits of counter 1 are set to O, the output signal from element 5 of the RS flip-flop 4 is thrown into one state and opens elements 6 and 17. By the action of a clock pulse on bus 2 at the output of the D flip-flop 16 1 is generated which allows the recording of information

313

When the state of counter 1 is reached, all its outputs have minor bits, except for the first and last, the signal from which is inverted by inverter 19, is established. O, at the output of element 17 appears 1, which with the arrival of a clock pulse passes to the output of D-flip-flop 12. 1 at the output of D-flip-flop 12 resets the RS-flip-flop 14 into one state, the signal at its output closes the element 17 and, having passed through element 13, closes the counting input of counter I and sets the code arriving from Gain 9 through multiplexer 8. The next clock pulse sets at the output of D-flip-flop 12 O, which resets RS-flip-flop 11 to one state. Counter 1 starts counting the input pulses from the code that is newly installed in the junior bits, and

N-2 + 2 M4; N +

2 1,

where N 7/2 + 2.

Minimum division ratio of the device MMUH

Claims (1)

Invention Formula A variable divider frequency divider containing a pulse counter, the counting input of which is connected to the input bus and the clock input of the first D-flip-flop, the direct output of which is connected to the zero input of the first RS-flip-flop, the single input of which is connected to the output of the first OR element NOT, the inputs of which are connected to the direct outputs of the corresponding high-order bits of the pulse counter, whose information inputs are connected to the high-order control bus, the low-order control bus, the output bus. inputs of the lower bits of the counting-25 inverter and the second element OR NOT, When code 1 is set to enter through multiplexer 8 from bus 10, after all the low-order bits, except for the first one, are set to O, 1 appears at the output of element 6, which under the action of a clock pulse passes to the output of the D-flip-flop 3 and pin 15 and, having passed through element 13, sets the code arriving from bus 10 through multiplexer 8, and also sets RS-triggers 4 and 14 to the zero state. Then the next cycle of work begins, proceeding as described. Thus, on the bus 15, a pulse of duration equal to the period of the input signal is formed under the action of the edges of the output signal. The division ratio of the variable-ratio divider is determined by the formula M (, - 21 + ... + a, 2) - 2 + + (bo + b, -З + .-.) N + bo + + b, - 24 ... + b., - (1 - B) thirty 35 whose first input is connected to. the reverse output of the first discharge, the restful ones with direct outputs of the other lower-order bits of the counter output pulse, with the information input D of the trigger, characterized in that, with the aim of expanding the functional possibilities while simultaneously ensuring the reliability of operation, the third or-NOT element, the OR element, the second and the third RS-flip-flops, the second and third D-flip-flops, the multiplexer, the SSS and the control panel manipulation factor of 40 divisions, which is connected to the first group of multiplexer inputs, the second group of inputs of which soy INE with the control bus of the lower bits I, the outputs with the information inputs of the lower bits of the impulse counter, the control input is connected to the direct output of the second RS flip-flop, the left input of which is connected to the inverse output of the first D-flip-flop whose direct output the third RS-trigger is connected to the input bus, with the zero input, and the first input of the OR element, the second input of which is connected to the direct output of the second B-trigger and the single input of the third RS trigger; pulse and pulse dov, resolution input recordings of which bits are connected to n 45 50 k-1. subject to bo + b, 2 +.,. 7l 2, where ar ,, and k + 1 bj ,, , and - the code on the bus 10; and fi is the code on bus 7; ., b "is the code on bus 9. The range of the discrete change in the division ratio of the device relative to a given N division ratio is determined by the expression thirty 35 whose first input is connected to. the inverse output of the first bit, the rest with the direct outputs of the other low bits of the pulse counter, the output with the information input of the D-trigger, characterized in that, in order to expand the functional capabilities while simultaneously maintaining the reliability of the function, the OR-NOT element, the OR element, the second and third RS-flip-flops, the second and third D-flip-flops, the multiplexer, the reset zone and the manipulator of the 40 division factor, which is connected to the first group of multiplexer inputs, the second group of inputs in which is connected the low-order control bus is I, the outputs are connected to the low-end data inputs of the pulse counter, the control input is connected to the direct output of the second RS flip-flop, the zero input of which is connected to the inverse output of the first D-flip-flop, the direct output of which is connected with output bus, with zero input of the third RS-trigger, and with the first input of the OR element, the second input of which is connected to the direct output of the second B-trigger and the single input of the third RS-trigger, output - with the enable input of the low-resolution counter impulse recording in, write enable input star-: Shih discharge which is connected to the straight rows 45 50 55 5 13962776 my output of the third D-flip-flop, which is connected to the additional the clock input of which is connected with the input of the second element OR NOT and with the input bus I-clock input of the second-first input of the third element of the Illy GNTrigger is the inverse output of the co-, NOT, the second input of which is connected to three is connected to the single input of the third RS flip-flop,  second RS flip-flop, informational 1 input with inverse output input - with the output of the third element of the first discharge of the pulse counter, OR NOT, zero input - with a single fourth input - through an inverter with the input of the first D-flip-flop, with the bus on the last, and the rest - directly and with a single input thirdgly, with direct outputs of the lower D-flip-flop, the information input of which, besides the first, connected to the forward output of the per-pulses. first RS flip-flop, inverse output