SU1473081A1 - Pulse repetition rate divider - Google Patents

Abstract

The invention relates to a pulse technique and can be used in frequency synthesizers. The purpose of the invention — extending functionality — is achieved by providing a controllable division factor of 10/16. The division factor is controlled by applying a control signal to bus 7. Each frequency division bit consists of a first trigger 1-1.1-2 and 1-3, a second trigger 2-1.2-2 and 2-3, and an OR element - NOT 3-1.3-2 and 3-3. The pulse frequency divider also contains elements 4 and 5 of coincidence, input bus 6 and output bus 8. D-type triggers can be used as second triggers 2-1, 2-2 and 2-3 of all bits. The proposed frequency divider has high speed and reliable operation, which is provided by a synchronous mode of operation. 1 tab. 1 il.

Description

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The invention relates to a pulse technique and can be used in frequency synthesizers.

The purpose of the invention is to enhance the functionality by providing a controllable division factor of 10 (11).

The drawing shows the electrical functional scheme of the device

The following frequency divider, pulses contains the first, second and third bits (frequency division), which consist of the first triggers 1-1, 1-2 and i-3, the second triggers 22-2 and 2-3 and the elements OR NOT 3-1, 3-2 and 3-3, the first inputs of which are connected to the 1 inputs of the second triggers 2-1, 2-2 and 2-3 and to the direct and outputs of the first triggers 1-1, 1-2 and 1 -3, the inverse outputs of which are connected to the K-inputs of the second triggers 2-1, 2-2, and 2-3, the inverse outputs of which are connected to the second outputs of the elements OR-NOT 3-1, 3-2 and 3-3. The outputs of the first and second elements 4 and 5 coincidence are connected respectively with the I and K inputs of the first trigger 1-1 of the first bit and with the additional 1 input of the first trigger 1-2 of the second bit. C-inputs of all triggers 1-1, 2-1, 1-2, 2-2, 1-3 and 2-3 are connected to the bus 6 clock (input) pulses. The first and second inputs of the first element 4 coincidence are connected respectively with an inverse output and with 1 input of the second. trigger 2-3 of the third bit, the third input - with bus 7 control. The first and second inputs of the second coincidence element 5 are connected respectively to the direct output and to the K input of the second flip-flop 2-3 of the third bit. The outputs of the elements OR-NOT 3-1 and 3-2 of the first and second bits are connected to the I- and K-inputs of the first triggers 1-2 and 1-3, respectively, of the second and third bits; the output of the third-order element OR-NOT 3-3 is connected to the output bus 8. D-triggers can be used as second triggers 2-1, 2-2, and 2-3 all bits, each of which is connected to direct output of the previous trigger.

The device works as follows.

When applied to the I- and K-inputs of flip-flops 1-1, 1-2 and 1-3 of a single level, these triggers with the arrival of the front

the impulses from the bus 6 to their C-inputs change their state to the opposite, when applying the zero level they retain their previous state. Triggers 2-1, 2-2 and 2-3 operate in

D-flip-flop mode: rewrite along the pulse front from bus 6 to their forward and inverse outputs, the levels available respectively at their I- and K-inputs.

When applying a zero level to the bus 7, the device provides a division factor of 10 (see Table 1); when applying a unit level, it is equal to 11 (see Table 2); at

this as the initial state of the triggers 1-1, 2-1, 1-2, 2-2, 1-3 and 2-3 (in table 1 and 2, the states are designated Q, Q, Qj, Q, respectively Qb) a state of 100000 is assumed. With the appearance of the front of each pulse (Table 1 and 2 are marked with TI), the state of all triggers of the device changes in accordance with Table 1 and 2. The proposed device has high speed and reliable operation due to synchronous operation.

Claims (1)

Invention Formula A pulse frequency divider containing the first match element, control bus, output bus and three bits, each of which consists of the first and second triggers, wherein the C-inputs of the first and second triggers of the first bit and the second triggers of the second and third bits are connected to the clock pulse bus, characterized in that, in order to extend the functionality, a second element is introduced into it match and in each of the three bits - an OR-NOT element, the first input of which in each channel is connected to the 1 input of the second trigger and to the direct output of the first trigger, the inverse output of which is connected to the K-input of the second trigger, inverse output which is connected to the second input of the element OR-NOT, the output of which, except for the element FID-NOT of the third discharge, is connected to the I- and K-inputs of the first the trigger of the subsequent bit, the output of the third-order OR-NO element is connected to the output pin, the C inputs of the first triggers of the second and third bits are connected to the C input of the second trigger of the third discharge, the inverse output and the 1 input of which are connected respectively and the second inputs of the first matching element, the third input of which is connected to the control bus, the output to the I and K inputs of the first trigger of the first discharge, while the additional 1 input of the first trigger of the second discharge is connected to the output of the second matching element,the first and second inputs of which are connected respectively to the direct output and to the K input of the second trigger of the third bit. Table I Continued tabl, 1