SU1241446A1 - Pulse repetition frequency multiplier - Google Patents

Abstract

The device relates to a pulse technique. It can be used in devices of measuring equipment, for example, in converters of the reference pulse frequency. The purpose of the invention is to expand the functionality by providing multiplication factors that are multiples of 0.5. To do this, set2G (L tc 4 li O)

Description

an array containing delay elements 1, 5 and 16, input bus 2, elements of equivalence 3 and 4, elements NAND- 6, 10 and 13, elements OR 8, 9, 11, 12 and 17, element OR-NOT 14, output bus 15, bus 7 control, introduced a quarter element 19 AND-NOT, element 20. And, the sixth and seventh elements OR 22 and 23, additional control bus 21, counting trigger 18. The delay in element 16 is set tfl 1/2 to fgjj where k - odds, "

The invention relates to a pulse technique and can be used in devices for measuring technology, automation and remote control, for example, in converters of a reference pulse frequency.

The purpose of the invention is to expand the functionality by providing multiplication factors that are multiples of 0.5.

. FIG. 1 shows an electrical functional diagram of the device; in FIG. 2 - time diagrams that show his work.

The pulse frequency multiplier contains the first delay element 1, whose input is connected to the internal bus 2 and the first input of the first equivalence element 3, the second input of which is connected to the output of the first delay element 1, to the first input of the second equivalence element 4 and through the second element 5 delays with the second input of the second equivalence element 4, the first AND-NOT element 6, the first input of which is connected to the 7th control, the first element OR8 the first and second inputs of which are connected respectively with the first and second m inputs of the second element OR 9, the output of which is connected to the first input of the second element AND-NOT 10, the second input of which is connected to the output of the third element OR 11, the first and second inputs of which are connected respectively to the first and second inputs of the fourth element OR 12, the output of which connected to the first input of the third element AND-NOT 13, the second

multiplier, f „, - frequency

1 of the input pulses on the bus 2. If the set delay is less than the required value, then two times during the follow-up period of the input pulses, the negative pulses are extended. If c is greater than the set value, then these pulses are shortened. Similarly, twice during the period following the input pulses, the phase of the output pulses is corrected for odd Q. 2 Il.

the input of which is connected to the output of the first element OR 8, the output to the first input of the element SHI-NO 14, the second input of which is connected to the output bus 15 - and through the third delay element 16 to the code of the fifth element 17 OR, the first input of which is connected to the output element OR - NOT 14, the second input - with the output of the second element AND- NOT 10, the counting trigger 18, the input of which is connected to the output of the second element 5 delay: ki, the output - with the first input of the fourth element AND-NOT 19, the output of which is connected with the second input of the first element AND-NOT 6, the right of which my output is En with the second input of the third element OR 11, the fourth output with the second input of the first element OR 8, the third input with the first input of the first equivalence element 3, the second input of which is connected to the first input of the AND element 20, the second input of which is connected to the auxiliary bus 21 control and with the second input of the fourth element AND- NOT 19, the output with the first inputs of the sixth and seventh elements OR 22 and 23, the second inputs of which are connected to the outputs of the first and second equivalence elements 3 and 4 respectively, the outputs with the first inputs venno second and third elements 9 and OR 11.

The padoTaeT device is as follows ,,

When applying to the bus 21 a zero potential at the output of the element 20, a zero potential is established, and at the second input of the element 6 - a single potential. The input pulse sequence is as follows; with a duty cycle of two (Fig. 2q), is delayed by the elements -1 and 5 (Fig. 25, fe). At the output of edements 3 and 4, at the moments of level mismatch, negative impulses are formed on their lines (Fig. 2g). , l), the duration of which is equal to the delay of the input pulses by elements 1 and 5, as which you can use, for example, integrating RC-chains or one or several pairs of inverters.

If the multiplication factor K is an integer, then zero potential is supplied to bus 7. In this case, the pulses from the outputs of elements 3 and 4 arrive at the inputs of elements 10 and 13, respectively, only through elements 8 and 9. At the same time, at the outputs of elements 10 and 13, positive pulses appear (Fig. 2e,) k). For odd K, pulses come from the output of element 5 to the second input of element 6, the first input of which is supplied by a single potential from bus 7, elements 8 and 12, and also 9 and 11 are switched alternately. As a result of this, the order of the pulses from the outputs of elements 10 and 13 varies (Fig. 2, U).

The magnitude of the delay in element 16 (for which you can use any type of delay element; with additional delay adjustment, for example, using an integrating RC-chain with a potentiometer)

It rushes Kf, where the frequency

following the input pulses on the bus 2.

If the set delay T is less than the required value, i.e. T. and the number K is even, then twice during the period following the input pulses, the negative pulses generated at the inputs of elements 14 and 17 are prolonged (Fig. 2 n) by the pulses coming from element 13. At the same time, the voltage at the output of element 16 The delay has 50 view, shown in FIG. 2m If 1d, then these pulses are shortened (fig. 2ts, 2o) by pulses coming from the output of element 10. At the same time, the voltage at the output of element 16 55 has the form shown in fig. 2.p.

Similarly, twice the follow-up period of the input pulses.

j 10

f5 2 25 jq

.

five

0

0 5

the phase of the output pulses is corrected for odd K.

The duration of the correction pulses formed by elements 3 and 4 is set to the maximum possible phase accumulation, accumulated over 1/2 f, which should not exceed the value of T.

To set the multiplication factor of the pulse frequency K i + 0.5, where i 1,2, ..., n, single potentials are applied to buses 7 and 21. In this case, the pulses generated by the elements of Zi4 (Fig. 2-2,), pass through the elements 22 and 23 only at the moment of receipt of a positive pulse on the bus 2, i.e. every second pulse of elements 3 and 4 passes through these elements. Moreover, the sequence of arrival of these pulses into elements 8, 9 and 12, 11 varies (Fig. 2p, c) depending on the state of trigger 18 (Fig. 2t), controlled by Switching elements 8, 9, and 12 and 11 through the elements 19 and 6. The trigger 18 changes its state at the moment when the positive front of the output pulse of the delay element 5 arrives at its input (Fig. 25). Corrective pulses from the outputs of elements 6 or 12 and 9 or 11 are fed through elements 13 and 10 to the inputs of element 14 and element 17, respectively. The choice of the delay of pulses in the element 16, as well as the correction of the phase of the output pulses on the bus 15, is carried out similarly to the mode with an odd multiplication factor, but not two, but once during the follow-up period of the input pulses. The output voltage diagrams at the outputs of elements 14, 17, and 16, when setting the multiplication factor K 4.5, are shown in Figs. 2i, f, k, respectively. As a result of an inaccurate setting of the delay in the element 16, the output pulse rate is corrected at times t, and so on.

Claims (1)

Invention Formula A pulse frequency multiplier containing the first delay element, the input of which is connected to the input bus and the first input of the first equivalence element, the second input of which is connected to the output of the first delay element, with the first the Bioporo input of the equal value element and, through the second delay element, to the second input of the second equivalence element, the first AND – NOT element, the first input of which is connected to the bus, the control, the first OR element, the first and second inputs of which are connected respectively to the first and the second inputs of the second OR element, the output of which is connected to the first input of the second element ItNET, the second input of which is connected to the output of the third OR element, the first and second inputs of which are connected respectively to the first and second inputs of the fourth ji, by the OR elements whose output is connected to the first input of the third NAND element, whose second input is connected to the output of the first OR element, output r to the first input of the OR-20 element, the second input to which is connected to the output bus and through the third delay element to the output the fifth OR element, the first input of which is connected to the output of the OR-NOT element, the second input to the output of the second AND-NOT element, characterized in that, in order to extend the functionality by providing the possibility of obtaining multiplication factors that are multiples of 0.5,It has the fourth AND-NOT element, the AND element, the sixth and seventh OR elements, an additional control and counting trigger whose input is connected to the output of the second delay element, the output is connected to the first input of the fourth AND-NOT element, the output of which is connected to the second the input of the first AND-NOT element whose direct output is connected. the second input of the third element or the inverse output — with the second input of the first element OR; the third input — With the first input of the first equivalence element, and with the first input of the AND element, the second input of which is connected to the additional control bus and the second input of the fourth AND-NOT element , the output is with the first inputs of the sixth and seventh OR elements, the second inputs of which are connected to the outputs of the first and second equivalence elements, respectively, the outputs with the first inputs of the second and third OR elements, respectively. if / FIG 2 Editor M.Nedoluzhenko Compiled by A.Sokolov Tehred L.Oleynik Korrek -or L.PipIypenko Order 3612/54 Circulation 816 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4