SU834857A2 - Sawtooth current generator - Google Patents

Description

(54) POWER-FORM CURRENT GENERATOR

one

The invention relates to a pulsed technique that can be used in a sawtooth current driver. . .

According to the main author. St. No. 721903, a sawtooth current generator is known, which contains a clock pulse generator, the output of which is connected to the input of the first pulse counter, a second pulse counter, the outputs of which are connected to the inputs of the current amplifier connected to the deflection system, elements, elements NOT, the first direct outputs of the first the pulse counter is connected to the inputs of the first element NAND, the reverse outputs of the first counter are connected to the inputs of the second element NAND, the outputs of these elements are connected to the inputs of the third element AND: -NO, the stroke of which is through the first, the element is NOT connected to the first input of the fourth NAND element, the second input of which is connected to the output of the clock generator and to the input of the second element NOT, the output of which is connected to the first input of the generic NAND element, the second input of which is connected to the output of the fifth element AND-NOT, whose inputs are connected to the second group of direct outputs of the first pulse counter, and the output of the third element AND-NOT, is connected to the first input of the seventh AND-NOT element, the second input of which is connected to the output of the third element nTA is AND-NOT, and the output is with the first input of the eighth element AND-NOT, the second input of the fourth element connected to the output of the AND is NOT, and the outputs through the third element NOT to the input of the second pulse counter, the control input of which is connected to the control the input of the first pulse counter and is connected to the clock signal bar 1.

A disadvantage of the known device is the low reliability of its operation.

The purpose of the invention is to increase the reliability of the device.

The goal is achieved by the fact that a key, a capacitor connected in parallel to the key outputs, and an additional element NOT, the input of which is connected to the clock signal bar, the output connected to the control input of the key, the first output of which is connected to the sawtooth-shaped current generator, are entered. - with the output of the adder current amplifier.

The drawing shows a structural electrical circuit of the device.

The device contains a generator of 1 clock pulses, a counter of 2 pulses, the first, second, third elements AND-NOT 3-5, the first element NOT 6, the fourth, fifth elements AND-NOT 7 and 8, the second element NOT 9, the sixth, seventh, the eighth element is NOT-10-12, the third element is NOT 13, the counter 14, the current amplifier 15, the deflection system 16, the capacitor 17, the key 18, the additional element NOT 19.

The device works as follows.

The clock pulse generator 1 generates clock pulses that are applied to the counting input of counter 2. In the initial state, when the control inputs of counter 2, the low-level voltage pulse corresponding to the logic zero level (prohibitory signal), counter 2 is reset. The clock pulses of the generator 1 do not pass through the first counter 2, since the outputs of this counter are constant, they do not enter the second counter 14 either, so there is no current at the output of the current amplifier 15 and in the deflecting system 16.

With the arrival at the control inputs of the first counter 2 of a high-level clock signal corresponding to the level of the logical unit (enabling signal), this counter passes generator 1 clock pulses, counts them and divides them bit by bit, forming a parallel binary code on the forward and reverse outputs. In this case, voltage pulses are applied to the first AND-3 unit, for example, from the direct outputs of the last triggers of counter 2, forming the first pulse of the correction section at the output of this element. The duration of this pulse depends on the number of the connected last direct outputs of the triggers of the first counter (practically the number of the connected outputs is two). At the same time, voltage pulses from the reverse outputs of the same last flip-flops of the same counter are applied to the second AND-NOT 4 element. In this case, at the output of the element AND-HE 4, a second voltage pulse is generated in the correction portion. The duration of this pulse also depends on the number of the connected reverse outputs of those last triggers of counter 2 (almost the number of connected outputs is also equal to two). Further, both pulses from the outputs of the AND-HEY elements 3 and 4 are applied to the inputs of the AND-HAY element 5. In it, these pulses are combined and at its output voltage pulses of correction sections are formed. From the output of the AND-HI element 5, the voltage pulses of the correction sections are fed to the input of the first element HEN 6, inverted therein and then fed to the per-input of the fourth element HAND 7.

At the same time, voltage pulses from clock generator 1 are applied to its second input. At the output of the element AND- NOT 7, voltage pulses are generated, which are a sequence of clock pulses of the generator 1 and are the sequential code of the uncorrectable region. At the same time, the voltage pulses from the direct outputs of the first triggers of the first counter 2 are fed to the inputs of the NAND element 8. The inverted pulses of the correction code are generated at the output of this element. The duration of each of these pulses is usually selected three times the pulse of the generator 1 clock pulses, and their number depends on the number of the connected direct outputs, the first triggers of the first counter 2. From the output of the NE-8 element 8, the inverted correction code pulses are fed to the first input of the I-NE 1 smart element 0. To the second input of this element, through the second element NOT 9, inverted voltage pulses of the generator 1 of clock pulses are applied. At the output of the element AND-NOT 10 a sequence of pulses is formed. These voltage pulses are applied to the first input of the seventh element AND-HE 11, to the second input of which voltage pulses of the correction sections are applied. At the output of this element a pulse sequence is formed, the extreme parts of which with respect to

0 to the average are filled with correction pulses and clock pulses of the clock pulse generator 1 and represent a sequential course of the correction sections. The voltage pulses of the sequential code of the uncorrectable area from the output of the fourth element AND-NOT 7 and the voltage pulses of the serial code of the correction sections from the output of element AND-HE 11 are simultaneously applied to the inputs of the eighth element AND-NOT 12 and in it

0 are combined. At the output of the NAND 12 element, a pulse sequence of an inverted full sequential code is formed. The pulse sequence of this code from the output of the NAND 12 element is fed to the input of the third element HE 13, inverted in it and then fed to the counting input of the counter 14. This group of pulses is the sequential input code of the counter 14. At the same time, the control inputs of this counter are fed the sync pulse in time and parameters is the same as arriving at counter 2. The construction and operation of counter 14 are similar to counter 2. At the output of counter 14, a parallel code is also generated, but taking into account the adjustments of its input successive code. The parallel counter code 14, the bit bottom, is fed to the input of current amplifier 15, where it is converted into a similar sawtooth current.

Claims (1)

Claim Sawtooth current generator according to ed. St. No. 721903, characterized in that, in order to increase the reliability of operation, a key is introduced into it, a capacitor connected in parallel with the key outputs, and an additional element NOT, whose input is connected to the clock bus, the output is connected to the control input of the input, the first output of which connected to the input, and the second output to the output of the adder current amplifier.