SU1150743A1 - Adaptive pulse repetition frequency multiplier - Google Patents

Abstract

1. ADAPTIVE MULTIPLE OF FREQUENCY OF PULSE MONITORING, containing two delay elements, the input of the first of which is connected to the input bus, two AND-NOT elements, the AND element and two OR elements, the first input of which is connected to the output of the AND element, characterized in that , in order to expand the dynamic range of multiplied pulse frequency, a pulse counter, a code voltage converter, an adjustable delay line, an OR — NOT element, and two inverters, the first input of which is connected to the output of the first element, are entered into it. the delay, and the output with the first inputs of the first NAND element and the OR NONE element (directly and through the series-connected second delay element and the second inverter - with the second input of the OR-NO element, the output of which is connected to the second input of the first OR element and with the first input of the second element OR NOT, the output of which is connected to the first input of the pulse counter, the second input of which is connected to the output of the second element OR, the first input of which is connected to the first input of the AND element, to the output bus and to the output adjustable l delay, the second input is with the BTOpbiM input of the AND element and with the output of the first NAND element, the second input of which is connected to the input bus, and the pulse input of the adjustable delay line is connected to the output of the first OR element, the control input is connected to the output of the code-eg converter live, the code inputs of which are connected to the corresponding outputs of the pulse counter. 2. A multiplier according to claim 1, characterized in that the adjustable delay line comprises a multi-drop delay line, the input of which is connected to a pulse input, and the outputs through a switch are connected to the first integrating chain consisting of a series-connected resistor, capacitor and varicap whose output through the first inverter is connected to the input of the second, analogous to the first, integrating chain, the output of which through the second inverter is connected to the output of the adjustable delay line, the control input of which through These resistors are connected to points 4 of the capacitor and varicap connection of the first oo and second integrating circuits ..

Description

The invention relates to a pulse technique and can be used in measurement technology, automation and remote control.

A pulse multiplying frequency multiplier is known, containing N − f 1 sequentially connected pending multivibrators, the AND-NOT multi-input logic element, the inverter, the second NAND element and the inequality logic 1.

The disadvantages of this multiplier device are low phase stability and complexity, increasing with a multiplication factor due to a corresponding increase in the number of pending multivibrators, which determines its small dynamic range.

Closest to the proposed technical entity is a device containing the first and second single vibrators, the first and second equivalence elements, five AND-NOT elements, four OR elements, and the first and second delay elements, with the input of the first delay element connected to the input bus device and the first input of the first element of equivalence, the output of which is connected to the first inputs of the first and second elements OR, the second inputs of which are connected respectively to the inverse and direct outputs of the fifth element - NOT, the first input of which is connected to the control input of the device, and the second input is connected to the output of the second delay element and to the first input of the second equivalence element, the output of which is connected to the first inputs of the third and fourth OR elements, the second inputs of which are connected respectively to the forward and inverse outputs of the pth element NAND, and the outputs from the first to the fourth elements OR are connected respectively to the first inputs of the first, second, third and fourth elements AND –NE, and the output of the first element of the INE connection This unit is connected to the second input of the third NAND element, the output of which through the first one-shot is connected to the second input of the second NAND, the output of which is connected to the second input of the fourth AND-NES element, the output of which through the second one-shot is connected to the second input of the first AND element NOT 2.

This device has greater structural and operational simplicity and a higher phase stability following output pulses. However, under the conditions of climatic changes in a wide range (temperature, humidity), as well as as a result of aging of the device elements, leading to a change in the duration of one-shot pulses and delays of other elements, the stability of the output pulse phase is not enough

high due to accumulation of phase error in the interval of half the period of the input signal. In addition, the deviation of the duty cycle of the input pulses from two also leads to a phase error. These factors limit the dynamic range of the multiplied pulse repetition frequencies with a small phase error.

The purpose of the invention is to expand the dynamic range of the multiplied pulse frequency.

The goal is achieved by the fact that in the adaptive pulse frequency multiplier, containing two elements

2 delays, the input of the first of which is connected to the input bus, two AND-NOT elements, the AND element and two OR elements, the first input of the first of which is connected to the output of the AND element, a pulse counter, a code-voltage converter, are adjustable

0 delay lines, an OR-NOT element and two inverters, the input of the first of which is connected to the output of the first delay element, and the output to the first inputs of the first NAND element and the OR-NOT element directly and through the series-connected second delay element and the second inverter - with the second input of the element ILINE, the output of which is connected to the second input of the first element OR, and with the first input of the second element NAND, the output of which

0 is connected to the first input of the pulse counter, the second input of which is connected to the output of the second OR element, the first input of which is connected to the first input of the AND element, to the output bus and to the output, adjusts the O.T delay line, the second input to the second input of the AND element and the output of the first NAND element, the second input of which is connected to the input bus, the pulse input of the adjustable delay line connected to the output of the first OR element, the control input to the output of the code-voltage converter, the code inputs of which are connected to favoring the outputs of the pulse counter.

An adjustable delay line of the adaptive pulse frequency multiplier contains a multi-drop delay line, the input of which is connected to a pulse input, and the outputs through a switch are connected to the first integrating chain consisting of a connected resistor, a capacitor and a varicap, whose output is connected to an input through the first inverter the second, similar to the first, integrating chain, the output of which through the second inverter is connected to the output of an adjustable delay line, the control input of which through The corresponding resistors are connected to the junction point of the capacitor and the varicap of the first and second integrating circuits.

FIG. 1 shows the structural electrical circuit of the proposed device; in fig. 2-4 - time diagrams that show his work.

The adaptive pulse multiplying frequency multiplier contains two elements 1 and 2 of the delay of the input of the first of which is connected to the input bus 3, two elements of AND-NO 4 and 5, the element of AND 6 and two elements of OR 7 and 8, the first input of the first of which is connected to the output element 6, pulse counter 9, code-voltage converter 10, adjustable delay line 11, element OR-NOT 12 and two inverters 13 and 14, the input of the first of which is connected to the output of the first delay element 1, and the output with the first inputs the first element AND-NOT 4 and the element OR-NOT 12 directly and black Without serially connected the second delay element 2 and the second inverter 14 with the second input of the element OR NOT 12, the output of which is connected to the second input of the first element OR 7 and with the first input of the second element AND-NOT 5, the output of which is connected to the first input of the counter 9 pulses, the second input of which is connected to the first input of the second element OR 8, the first input of which is connected to the first input of the element 6, the output bus 15 and the output of the adjustable delay line 11, the second input to the second input of the ibis element the output of the first element i- NOT 4 The second input of which is connected to the input bus 3, the pulse input of the adjustable delay line 11 is connected to the output of the first element OR 7, the control input to the output of the converter 10 code-voltage, the code inputs of which are connected to the corresponding outputs of the pulse counter 9, adjustable line delays 11 contains a multi-tap delay line 16, the input of which is connected to a pulse input, and the outputs via switch 17 are connected to the first integrating chain (integrating chains consist of connected in series the resistor 18-1, (18-2), the capacitor 19-1 (19-2) and the varicap 20-1 (20-2). The output of the first integrating chain through the first inverter 21 is connected to the input of the second integrating chain, the output of which through the second inverter 22 is connected to the output of an adjustable delay line, the control input of which is connected to the junction point of the capacitor and varicap through corresponding resistors 23-1 (23-2) first and second integrating chains.

The device works as follows.

The input sequence of the pulse bus 3 (Fig. 2a) is delayed and inverted by element 1 and inverter 13 (fig. 26), as well as element 2 and inverter 14 (fig. 2 c). At the same time, the output of element 4 produces negative and positive pulses n (Fig. 2 g, e), respectively, the duration of which is equal to 5 the magnitude of the delays of the pulses in the corresponding delay elements, for which you can use integrating chains or one or several pairs of HE elements. The delay is set in accordance with the maximum phase error of the output pulses accumulated in the interval of one period of the following impulses under any permissible climatic and temporal conditions of operation. The multiplication factor K is established by means of a switch 17, which commutes the corresponding tap of the multi-tap delay line 16 and the first integrating circuit containing resistor 18-1, capacitor 19-I and varicap 20-1. This chain, together with a second integrating chain connected in series with it through an inverter 21, comprising a resistor 18-2, a capacitor 19-2, and a varicap 20-2, together with the inverter 22, allows to smoothly adjust the pulse delay,

5 passing through the switch 17. Connections of the second integrating chain and inverters are caused, firstly, by the need to expand the range of the pulse delay variation, and secondly, by the requirement to equalize the delays of the front and rear edges of the pulses, since the delays of the front and rear edges of one integrating the chain is not equal.

The delay is controlled by applying voltage to the control input of an adjustable delay line 11, which

 through resistors 23-1 and 23-2 go to varicaps 20-1 and 20-2, respectively, whose junction capacitance depends on this voltage.

The discrete delay values provided by the multi-tap delay line 16 are set so that, in the absence of a phase error, the control voltage on the varicaps corresponds to the middle of their operating characteristics at average temperatures and other environmental parameters, which allows both increasing and decreasing the delay of pulses passing through the adjustable delay line 11. If the delay t of pulses is equal to the required value to

0 where fer is the follow frequency of the input pulses, then the voltages at the outputs of elements 6 and 7 and bus 15 take the form shown in FIG. 2e, g, s, respectively. The phase of these pulses is set at times ti using pulses.

5 corrections from the outputs of the elements 7 and 12 shown in FIG. 2d, d, respectively, and their duty cycle is equal to two, regardless of the duty cycle of the input pulses.

If (,, then the voltage diagrams shown in Fig. 2 g, d, e, g, h take the form shown in Fig. 3 g, d, e, g, 3, respectively, and the output element 5 at time ti A negative pulse appears (Fig. 3k), which increases the number n recorded in the counter 9 by one, thus increasing the voltage at the output of the converter 10, as a result of which the capacity of the varicaps 20-1 and 20-2 decreases, and, accordingly, the delay t is reduced. If t is all more than to, then in the next period this process is repeated, increasing / number n by one more The process is repeated until t becomes equal to tp, with the outputs of elements 5 and 8 being the unit potential (Fig. 2k, and respectively).

If (Fig. 4), then at the output of element 8 a negative pulse is formed (Fig. 4 "), reducing the number n by one

as a result, the capacity of the varicaps 20-1 and 20-2 is increased, which ultimately eliminates the phase error.

The use of the proposed device makes it possible to virtually eliminate the phase error of the output pulses during any care of the parameters of the elements of the device caused by climatic and temporal factors varying within acceptable limits. In the prototype device, the phase error is not excluded and increases with the expansion of the range of changes in parameters, and in some cases may lead to a change (jump) in the multiplication factor.

Thus, the proposed adaptive pulse frequency multiplier allows to increase the dynamic range of the multiplied pulse frequency.

AND

ti

FIG. 2

Claims (2)

1. ADAPTIVE FREQUENCY FREQUENCY FREQUENCY OF PULSE FOLLOWING, containing two delay elements, the input of the first of which is connected to the input bus, two AND elements, the AND element and two OR elements, the first input of the first of which is connected to the output of the AND element, characterized in that , in order to expand the dynamic range of the multiplied pulse repetition frequencies, a pulse counter, a code-voltage converter, an adjustable delay line, an OR-HE element and two inverters, the input of the first of which is connected to the output of the first element behind holding, and the output - with the first inputs of the first AND-NOT element and the OR-HE element directly and through the second delay element and the second inverter connected in series with the second input of the OR-HE element, the output of which is connected to the second input of the first OR element and to the first input of the second element OR-HE, whose output is connected to the first input of the pulse counter, the second input of which is connected to the output of the second element OR, the first input of which is connected to the first input of the AND element, with the output bus and the output of the adjustable delay line, the second input - with the second input of the element And with the output of the first AND-NOT element, the second input of which is connected to the input bus, and the pulse input of the adjustable delay line is connected to the output of the first OR element, the control input is with the output of the code-voltage converter, the code inputs of which oedineny with respective pulse counter output. 2. The multiplier in π. 1, characterized in that the adjustable delay line contains a multi-tap delay line, the input of which is connected to a pulse input, and the outputs through the switch are connected to the first integrating circuit consisting of a resistor, a capacitor and a varicap connected in series, the output of which is connected to the input through the first inverter a second, similar to the first, integrating circuit, the output of which through the second inverter is connected to the output of an adjustable delay line, the control input of which is connected through the corresponding resistors to the connection points of the capacitor and varicap of the first and second integrating chains .. SU „„ 1150743