KR920022687A - PCM / ADPCM Data Interconverter - Google Patents

PCM / ADPCM Data Interconverter Download PDF

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Publication number
KR920022687A
KR920022687A KR1019910008983A KR910008983A KR920022687A KR 920022687 A KR920022687 A KR 920022687A KR 1019910008983 A KR1019910008983 A KR 1019910008983A KR 910008983 A KR910008983 A KR 910008983A KR 920022687 A KR920022687 A KR 920022687A
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South Korea
Prior art keywords
pcm
data
adpcm
signal
control means
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KR1019910008983A
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Korean (ko)
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KR930004860B1 (en
Inventor
유득수
신동진
이형호
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경상현
재단법인 한국전자통신연구소
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Publication of KR920022687A publication Critical patent/KR920022687A/en
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Publication of KR930004860B1 publication Critical patent/KR930004860B1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

내용 없음.No content.

Description

PCM/ADPCM 데이터 상호 변환장치PCM / ADPCM Data Interconverter

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명에 의한 PCM/ADPCM 데이타 상호 변환장치의 블럭도,1 is a block diagram of a PCM / ADPCM data interchange apparatus according to the present invention;

제2도는 본 발명에 의한 ADPCM트랜스코더부의 신호파형도,2 is a signal waveform diagram of an ADPCM transcoder unit according to the present invention;

제3도는 본 발명에 의한 타임슬롯 제어부의 구성도,3 is a configuration diagram of a timeslot control unit according to the present invention;

제4도는 제3도의 각 부분의 신호파형도,4 is a signal waveform diagram of each part of FIG.

제5도는 타임스롯 제어데이터의 포맷도,5 is a format diagram of time slot control data;

제6도는 본 발명에 의한 PCM복부호부의 구성도,6 is a block diagram of a PCM coder according to the present invention;

제7도는 제6도의 각부분의 신호 파형도,7 is a signal waveform diagram of each part of FIG.

제8도는 본 발명에 의한 PCM정합부의 구성도,8 is a configuration diagram of the PCM matching unit according to the present invention;

제9도는 본 발명에 의한 클럭공급부의 구성도.9 is a block diagram of a clock supply unit according to the present invention.

Claims (6)

아날로그 신호가 디지틀 데이터로 변환되어 신호처리되거나 저장될때 뮤-로우 PCM데이타를 대역폭이 줄어든 ADPCM 데이터로 바꾸거나 ADPCM 데이터를 뮤-로우 PCM 데어터로 바꾸는 PCM/ADPCM 데이터 상호 변환장치에 있어서; PCM/ADPCM 데이터 상호 변환장치 전체를 제어하는 중앙제어수단(110), 상기 중앙제어수단(110)에 연결되어 상기 중앙제어수단(110)의 제어데이터로 32개의 타임슬롯으로 시분할 다중화된 신호선의 배정채널에 디지틀 데이터를 실어주기 위한 타임슬롯 프레임 동기신호를 생성하는 타임슬롯 제어수단(120), 상기 타임슬롯 제어수단(120)에 연결되어 애널로그 신호를 뮤-로우 PCM신호로 변환시키거나 뮤-로우 PCM 신호를 애널로그 신호로 변환시키는 PCM복부호수단(130), 상기 중앙제어수단(110)과 PCM복부호수단(130)에 연결되어 상기 PCM 복부호수단(130)의 뮤-로우 PCM 신호를 ADPCM 데이터로 변환하여 상기 중앙제어수단(110)의 데이터버스에 실거나 상기 데이터 버스에서 ADPCM 데이터를 받아 뮤-로우 PCM 신호로 변환하고 상기 PCM 복부호수단(130)으로 출력하는 ADPCM 트랜스코더수단(150), 상기 중앙제어수단(110)과 PCM 복부호수단(130)과 ADPCM 트랜스코더수단(150)에 연결되어 상기 ADPCM 트랜스코더수단(150)과 PCM 복부호수단(130)으로 부터 출력되는 신호를 PCM 서브하이웨이에 정합시키는 PCM정합수단(10)으로 구성되는 것을 특징으로 하는 PCM/ADPCM 데이터 상호 변환장치.A PCM / ADPCM data interconversion device for converting mu-low PCM data into bandwidth-reduced ADPCM data or converting ADPCM data into mu-low PCM data when an analog signal is converted into digital data for signal processing or storage; Central control means 110 for controlling the entire PCM / ADPCM data interconversion device, the time-division multiplexed signal lines assigned to 32 time slots as control data of the central control means 110 connected to the central control means 110 Time slot control means 120 for generating a time slot frame synchronization signal for carrying digital data on a channel, and connected to the time slot control means 120 to convert an analog signal into a mu-low PCM signal or to mu- PCM decoding means 130, which converts the low PCM signal into an analog signal, is connected to the central control means 110 and the PCM decoding means 130 to convert the mu-low PCM signal of the PCM decoding means 130 into the ADPCM data. The ADPCM transcoder converts the data into the data bus of the central control unit 110 or receives the ADPCM data from the data bus, converts the signal into a mu-low PCM signal, and outputs the result to the PCM decoding unit 130. A signal output from the ADPCM transcoder means 150 and the PCM decoding means 130 connected to the central control means 110, the PCM decoding means 130, and the ADPCM transcoder means 150. PCM / ADPCM data interconversion device, characterized in that consisting of a PCM matching means (10) for matching the PCM subhighway. 제1항에 있어서, 상기 중앙제어수단(110)과 타임슬롯제어수단(120)과 PCM복부호수단(130)과 PCM정합수단(140)과 ADPCM 트랜스코더 수단(150)에 연결되어 상기 각 수단에서 필요로 하는 클럭을 공급하는 클럭공급수단(160)을 더 포함하여 구성되는 것을 특징으로 하는 PCM/ADPCM 데이터 상호 변환장치.According to claim 1, wherein the central control means 110, the timeslot control means 120, PCM decoding means 130, PCM matching means 140 and ADPCM transcoder means 150 are connected in each of the means; PCM / ADPCM data inter-conversion device further comprises a clock supply means for supplying the clock required. 제1항 또는 제2항에 있어서, 상기 타임슬롯 제어수단(120)은 상기 중앙제어수단(110)에 연결된 데이터래치수단(210), 상기 중앙제어수단(110)에 연결된 D플립플롭(230), 상기 중앙제어수단(110)과 D플립플롭(220)에 연결된 논리곱수단(250), 상기 데이터래치수단(210)과 논리곱수단(250)과 PCM 복부호수단(130)에 연결된 제1쉬프트 레지스터수단(220), 및 상기 PCM 복부호수단(130)과 논리곱수단(250)에 연결된 제2쉬프트 레지스터 수단(240)으로 구성되는 것을 특징으로 하는 PCM/ADPCM 데이터 상호 변환장치.The apparatus of claim 1 or 2, wherein the timeslot control means (120) is a data latch means (210) connected to the central control means (110), and a D flip-flop (230) connected to the central control means (110). A first shift connected to the central control unit 110 and the D flip-flop 220; the first latch connected to the data latch unit 210 and the logical multiplication unit 250 and the PCM decoding unit 130; And a second shift register means (240) connected to the register means (220) and the PCM decoding means (130) and the logical product means (250). 제1항 또는 제2항에 있어서, 상기 PCM 복부호수단(130)은 상기 타임슬롯 제어수단(120)에 연결되어 해당 타임슬롯에 대해 입출력 PCM용 프레임 동기신호(FSR,FSX)를 출력하는 타임슬롯배정기(310), 및 상기 타임스롯 배정기(310)에 연결되어 PCM 신호를 아날로그 신호로 변환하거나 아날로그 신호를 PCM신호로 변환하는 PCM복부호기(320)로 구성되는 것을 특징으로 하는 PCM/ADPCM 데이터 상호 변환장치.3. The time slot according to claim 1 or 2, wherein the PCM decoding means (130) is connected to the time slot control means (120) and outputs a frame synchronization signal (FSR, FX) for input / output PCM to the corresponding time slot. A PCM / ADPCM data interconnector comprising a assignor 310 and a PCM decoder 320 connected to the time slot assigner 310 to convert a PCM signal to an analog signal or to convert an analog signal to a PCM signal. Inverter. 제1항 또는 제2항에 있어서, 상기 PCM 정합수단(140)은 상기 중앙처리수단(110)과 ADPCM 트랜스코더수단(150)과 PCM 복부호수단(130)에 연결된 PCM 데이터 방향제어수단(510), 및 상기 PCM 데이터 방향 제어수단(130)에 연결되어 PCM 신호를 송수신하는 PCM신호 송수신 수단(520)으로 구성되는 것을 특징으로 하는 PCM/ADPCM 데이터 상호 변환장치.The PCM data direction control means 510 according to claim 1 or 2, wherein the PCM matching means 140 is connected to the central processing means 110, the ADPCM transcoder means 150, and the PCM decoding means 130. And PCM signal transmission / reception means (520) connected to the PCM data direction control means (130) to transmit / receive PCM signals. 제2항에 있어서, 상기 클럭공급수단(160)은 상기 중앙제어수단(110)과 타임슬롯 제어수단(120)에 연결된 중앙제어수단 동작클럭 발생수단(710), 상기 ADPCM 트랜스코더수단(150)에 연결된 자체클럭발생수단(720), 및 상기 PCM 정합수단(140)과 PCM 복부호수단(130)과 자체클럭 발생수단(720)에 연결된 클럭선택수단(730)으로 구성되는 것을 특징으로 하는 PCM/ADPCM 데이터 상호 변환장치.The clock supply means 160, the central control means 110 and the time slot control means 120 is connected to the operation clock generating means 710, ADPCM transcoder means 150 PCM / characterized in that it is composed of a clock selection means 730 connected to the self-clock generating means 720, and the PCM matching means 140 and PCM decoding means 130 and the self-clock generating means 720. ADPCM data interconverter. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910008983A 1991-05-31 1991-05-31 Interconvert instrument of pcm/adpcm data KR930004860B1 (en)

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KR1019910008983A KR930004860B1 (en) 1991-05-31 1991-05-31 Interconvert instrument of pcm/adpcm data

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KR1019910008983A KR930004860B1 (en) 1991-05-31 1991-05-31 Interconvert instrument of pcm/adpcm data

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KR930004860B1 KR930004860B1 (en) 1993-06-09

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000043468A (en) * 1998-12-29 2000-07-15 김영환 Subscriber interface of wireless local loop system increasing signal processing capacity

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000043468A (en) * 1998-12-29 2000-07-15 김영환 Subscriber interface of wireless local loop system increasing signal processing capacity

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