JPH09172424A - Signal speed converting circuit for data highway - Google Patents

Abstract

PROBLEM TO BE SOLVED: To use the same circuit for conversion from the speed of a high bit rate to that of a low bit rate and conversion from the speed of a low bit rate to that of a high bit rate. SOLUTION: A drawing timing generation circuit 11 generates the writing timing of a memory circuit 12 based on a reception clock signal and drawing timing data read from a data memory circuit 15. An insertion timing generation circuit 14 generates the reading timing of the memory circuit 12 based on insertion timing data read from an insertion timing data memory circuit 16 and a transmission clock signal generated from a transmission clock generation circuit 17. The memory circuit 12 holds data from a highway data receiving circuit 10 with the writing timing and reads data with reading timing to send it to a highway data transmission circuit 13.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data speed conversion circuit for data highways, and more particularly to a method for converting a signal speed between data signals transmitted via respective data highways (time division multiplex transmission lines) having different transmission speeds. Regarding

[0002]

2. Description of the Related Art Conventionally, in a transmission method for transmitting a test result obtained by a device under test to a measuring device, a test result of the device under test is sent at a transmission speed of the device under test and stored in a storage device. There is. Of the test results stored in the storage device, only the required test result is read out by software, and the read test result is sent to the measuring device at the transmission speed.

When data is transferred between data highways having different transmission speeds in the above-described transmission method, etc., the signal speed for converting the transmission speed of one data highway into the transmission speed of the other data highway. A conversion circuit is used.

In this signal speed conversion circuit, a digital signal sent at a constant transfer speed is converted into a digital signal having a transfer speed different from the transfer speed, and the digital signal having the converted transfer speed is transmitted. Has been done.

That is, as shown in FIG.
1 input from PCM (Pulse Code Mo
signal) is applied to the delay circuits 21, 22 and FI.
After the speed is converted by the FO (First In First Out) memory circuits 23 and 24, two output routes 2
It is output from 02, 203.

Reading from the FIFO memory circuits 23 and 24 is performed by the read pulses created by the read pulse creating circuits 27 and 28, respectively.
It is performed at a timing such that the data from 3 and 24 have the frame configurations b and c shown in FIG. 7, respectively.

Writing to the FIFO memory circuits 23 and 24 is performed by the write pulses created by the write pulse creating circuits 25 and 26, respectively. Writing to the FIFO memory circuits 23, 24 is performed by writing to the FIFO memory circuits 23, 2
When the reading from 4 is performed at the above timing, the FIFO memory circuits 23 and 24 become empty,
Alternatively, it is performed only for necessary signals at a timing that does not cause overflow.

The PCM signal from the input route 201 is delayed by the delay circuits 21 and 22 to obtain the FIFO memory circuits 23 and 2 described above.
4 is adapted to the write timing. The circuit configuration described above converts the frame configuration a of a 30-channel PCM signal having a bit rate of 2.048 MHz into the frame configurations b and c of a 24-channel PCM signal having a bit rate of 1.536 MHz (see FIG. 7).

On the other hand, the bit rate of 1.536 MHz is 2
When converting the frame configurations b and c of the 4-channel PCM signal into the frame configuration a of the 30-channel PCM signal having a bit rate of 2.048 MHz, a circuit configuration as shown in FIG. 6 is used.

That is, P from the incoming routes 301 and 302
The CM signal is speed-converted by the FIFO memory circuits 31 and 32 and then output from the output path 304 via the delay circuit 37.

The PCM signals from the input paths 301 and 302 are written in the FIFO memory circuits 31 and 32 by the write pulses created by the write pulse creating circuits 33 and 34. Reading from the FIFO memory circuits 31 and 32 is performed by the read pulses created by the read pulse creating circuits 35 and 36, respectively, and the read PCM signal is the signal line 3
It is synthesized on 03.

Writing to and reading from the FIFO memory circuits 31 and 32 do not cause the FIFO memory circuits 23 and 24 to become empty or overflow, and the signal line 3
The PCM signal read from the FIFO memory circuits 31 and 32 on 03 is performed at the timing such that the PCM signal has the frame structure a shown in FIG. The PCM signal on the signal line 303 is adapted to the timing of the output route 304 by the delay circuit 37. Regarding the signal speed conversion circuit described above, there is a technique disclosed in JP-A-57-24141.

[0013]

In the transmission method for transmitting the test result obtained by the above-described conventional device under test to the measuring device, the test result of the device under test is transmitted and stored at the transmission speed of the device under test. Only the required test result is read out by software from the test result stored in the device, and the read test result is sent to the measuring device at the transmission speed.

Therefore, the test result of the device under test cannot be transmitted to the measuring device in real time, and the test result of the device under test cannot be immediately processed by the measuring device, which requires a long processing time. , The content of the software must be changed to get different test results.

On the other hand, the signal speed conversion circuit described above requires a write pulse generation circuit and a read pulse generation circuit in accordance with the bit rate, so that a circuit for converting a high bit rate speed to a low bit rate speed is required. , A circuit for converting from a low bit rate speed to a high bit rate speed must be created separately.

Therefore, the object of the present invention is to perform the conversion from a high bit rate speed to a low bit rate speed and the conversion from a low bit rate speed to a high bit rate speed using the same circuit. It is to provide a signal speed conversion circuit for a data highway.

Another object of the present invention is that the test result of the device under test can be transmitted to the measuring device in real time, and the test result of the device under test can be immediately processed by the measuring device. It is an object of the present invention to provide a signal speed conversion circuit for a data highway that can easily obtain different test results.

[0018]

A first data highway signal conversion circuit according to the present invention transmits a data signal on a first time division multiplex transmission line that transmits a data signal at a constant bit rate, to the constant bit rate. A signal speed conversion circuit for a data highway for converting and outputting a data signal to a second time division multiplex transmission line for transmitting a data signal at a bit rate different from that of the first time division multiplex transmission. Storage means for storing a data signal on the path; first storage means for storing extraction timing data indicating extraction timing of the data signal on the first time division multiplex transmission path; and contents of the first storage means. First timing generation means for generating a storage timing of the data signal on the first time division multiplex transmission path in the storage means based on Second storage means for storing insertion timing data indicating the insertion timing of the generated data signal on the second time division multiplex transmission line, and the second storage means based on the contents of the second storage means. Second timing generation means for generating the read timing of the data signal from the storage means on the time division multiplex transmission line.

In a second data highway signal conversion circuit according to the present invention, in the above structure, the first timing generation means is based on a reception clock signal accompanying the data signal on the first time division multiplex transmission line. Is configured to read the extraction timing data from the first storage means, and the second timing generation means is configured to read the extraction timing data based on a transmission clock signal accompanying the data signal on the second time division multiplexing transmission line. The insertion timing data is read from the second storage means.

The third data highway signal conversion circuit according to the present invention has, in addition to the above configuration, a receiving means for receiving a data signal on the first time division multiplex transmission line and temporarily holding the data signal. Holding the data signal read from the storage means and storing the data signal in the second
And transmitting means for transmitting on the time division multiplex transmission line.

In a fourth data highway signal conversion circuit according to the present invention, in the above structure, the first timing generation means is based on a reception clock signal accompanying the data signal on the first time division multiplex transmission line. And a means for generating a read address for the first storage means, the second timing generation means based on the transmission clock signal accompanying the data signal on the second time division multiplex transmission path. It has means for generating a read address for the second storage means.

A fifth data highway signal conversion circuit according to the present invention receives a data signal sent from a device under test via a first time division multiplex transmission line which transmits the data signal at a constant bit rate. A second for transmitting a data signal at a bit rate different from the constant bit rate
A data speed conversion circuit for a data highway for converting to a data signal to be sent to a measuring device through the time division multiplex transmission line and outputting the data signal, the storing means storing the data signal on the first time division multiplex transmission line. And first storage means for storing extraction timing data indicating the extraction timing of the data signals sent from the device under test in a predetermined sequence, and based on the contents of the first storage means, First timing generation means for generating a storage timing of the data signal on the first time division multiplex transmission path in the storage means, and the measurement device for the data signals stored in the storage means in a predetermined fixed order. Second storage means for storing the insertion timing data indicating the insertion timing for the data signal to be sent to the second storage means, and the second time based on the contents of the second storage means. And a second timing generating means for generating a read timing from the storage means of the data signals to division multiplexing transmission path.

In a sixth data highway signal conversion circuit according to the present invention, in the above structure, the first timing generation means is based on a reception clock signal accompanying the data signal on the first time division multiplex transmission line. Is configured to read the extraction timing data from the first storage means, and the second timing generation means is configured to read the extraction timing data based on a transmission clock signal accompanying the data signal on the second time division multiplexing transmission line. The insertion timing data is read from the second storage means.

The seventh data highway signal conversion circuit according to the present invention has, in addition to the above configuration, a receiving means for receiving a data signal on the first time division multiplex transmission line and temporarily holding the data signal. Holding the data signal read from the storage means and storing the data signal in the second
And transmitting means for transmitting on the time division multiplex transmission line.

In the eighth data highway signal conversion circuit according to the present invention, in the above configuration, the first timing generation means is based on the reception clock signal accompanying the data signal on the first time division multiplex transmission line. Means for generating a read address for the first storage means, the second timing generation means based on a transmission clock signal associated with a data signal on the second time division multiplex transmission line. It has means for generating a read address for the second storage means.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the operation of the present invention will be described below.

Extraction timing data indicating the extraction timing of the data signal on the first data highway for transmitting the data signal at a constant bit rate is stored in the timing data memory circuit in advance, and a bit different from the constant bit rate is stored. Insertion timing data indicating the insertion timing for the data signal on the second data highway that transmits the data signal at the rate of rate is stored in advance in the timing data memory circuit.

The data signal of the first data highway is stored in the memory circuit based on the extraction timing data,
A data signal is read from the memory circuit based on the insertion timing data and transmitted to the second data highway.

This makes it possible to perform conversion from a high bit rate speed to a low bit rate speed and conversion from a low bit rate speed to a high bit rate speed using the same circuit.

Extraction timing data indicating the extraction timing of the data signals sent from the device under test in a predetermined order through the first data highway that transmits the data signals at a constant bit rate. Data to be stored in the timing data memory circuit in advance and to be sent to the measuring device in a predetermined fixed order through the second data highway that transmits a data signal at a bit rate different from the constant bit rate. Insertion timing data indicating the insertion timing for the signal is stored in the timing data memory circuit.

The data signal on the first data highway is stored in the memory circuit based on the extraction timing data, and the data signal on the second data highway is read from the memory circuit based on the insertion timing data. .

As a result, the test result of the device under test can be transmitted to the measuring device in real time, and the test result of the device under test can be immediately processed by the measuring device. Furthermore, by rewriting the timing data of the timing data memory circuit, it becomes possible to easily obtain different test results.

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention. In the figure, the data highway signal speed conversion circuit 1 is shown in FIG.
The test result input via the 2.768 MHz data highway 101 is subjected to speed conversion to obtain a bit rate of 8.19.
Measuring device 4 via 2 MHz data highway 102
Send to

The data highway signal speed conversion circuit 2 performs speed conversion of the test data input from the measuring device 4 via the data highway 103 with a bit rate of 8.192 MHz, and via the data highway 104 with a bit rate of 32.768 MHz. It is sent to the device under test 3.

FIG. 2 is a block diagram showing the configuration of the data highway signal speed conversion circuit 1 of FIG. In the figure, a data highway signal speed conversion circuit 1 includes a highway data reception circuit 10 and an extraction timing generation circuit 1.
1, a memory circuit 12, and a highway data transmission circuit 1
3, an insertion timing generation circuit 14, an extraction timing data memory circuit 15, an insertion timing data memory circuit 16, and a transmission clock generation circuit 17.

The highway data receiving circuit 10 receives the received data signal 110 and the received clock signal 111 via the data highway 101 having a bit rate of 32.768 MHz and outputs write data to the memory circuit 12.

The extraction timing generation circuit 11 receives the reception clock signal 111 and the extraction timing data memory circuit 1
The write timing of the memory circuit 12 is generated based on the pull-out timing data read from the memory 5, and the write timing is output to the memory circuit 12.

The memory circuit 12 holds the write data from the highway data receiving circuit 10 in the first-in first-out order in accordance with the write timing from the pull-out timing generating circuit 11. That is, the data extracted from the received data signal 110 at the extraction timing generated by the extraction timing generation circuit 11 is held in the memory circuit 12 in a first-in first-out order.

Further, the memory circuit 12 inserts the data held in the first-in first-out order into the insertion timing generating circuit 14.
It is read out based on the insertion timing from and is sent to the highway data transmission circuit 13. That is, the data held in the memory circuit 12 in the first-in first-out order is read at the insertion timing generated by the insertion timing generation circuit 14, and is inserted into the transmission data signal 112.

The highway data transmission circuit 13 transmits the data signal read from the memory circuit 12 as a transmission data signal 112 in synchronization with the transmission clock signal 113 generated by the transmission clock generation circuit 17.

The insertion timing generation circuit 14 generates the read timing of the memory circuit 12 based on the insertion timing data read from the insertion timing data memory circuit 16 and the transmission clock signal 113 generated by the transmission clock generation circuit 17, and reads it. Timing the memory circuit 12
Output to

The extraction timing data memory circuit 15 stores in advance timing data indicating at what timing data is to be extracted from the received data signal 110. The insertion timing data memory circuit 16 stores in advance timing data indicating at what timing the data read from the memory circuit 12 is inserted into the transmission data signal 112.

The transmission clock generation circuit 17 generates a transmission clock signal 113 to be transmitted to the data highway 102 having a bit rate of 8.192 MHz.

The data highway signal speed conversion circuit 2 has the same structure as the data highway signal speed conversion circuit 1, and its operation is also the same. However, the highway data reception circuit 10 and the extraction timing generation circuit 11 operate with the clock signal of the data highway 103 having a bit rate of 8.192 MHz, and the highway data transmission circuit 13 and the insertion timing generation circuit 14 have a data rate of 32.768 MHz. The transmission clock generation circuit 17 operates with the clock signal of 104, and the transmission clock generation circuit 17 has the data highway 104 of the bit rate 32.768 MHz.
Generates a clock signal.

3 and 4 are diagrams showing the relationship between the receiving operation and the transmitting operation and the contents held in the memory circuit 12 according to an embodiment of the present invention. The operation of the embodiment of the present invention will be described with reference to FIGS.

First, the case where the data A, B, C and D to be extracted in the received highway data signal 110 are continuous will be described. In this case, the extraction timing data memory circuit 15 stores the timing data of "1" at the addresses corresponding to the timings of the data A, B, C, D, and the timing data of "0" at the addresses corresponding to the other timings. Is stored. Therefore, “1” is stored in four consecutive addresses of the extraction timing data memory circuit 15.

The extraction timing generating circuit 11 sequentially counts up an address counter (not shown) for generating the memory address of the extraction timing data memory circuit 15 with the received highway clock signal 111, and extracts the extraction timing according to the memory address from this address counter. The extraction timing data is read from the data memory circuit 15.

If the pull-out timing data read out from the pull-out timing data memory circuit 15 is "1", the pull-out timing generating circuit 11 pulls-out timing 12
1 is generated and output to the memory circuit 12 as a write timing.

Therefore, continuous data A, B, C, D are written in the memory circuit 12 at the extraction timing 121. At that time, the highway data receiving circuit 10 temporarily holds the received highway data signal 110 for the time required for the extraction timing generation circuit 11 to read the extraction timing data from the extraction timing data memory circuit 15 and to generate the extraction timing 121. Has been done.

Next, the case where the data A, B, C and D to be inserted in the transmission highway data signal 112 are continuous will be described. In this case, the insertion timing data memory circuit 16 stores the timing data of "1" at the addresses corresponding to the timings of the data A, B, C, and D, and the timing data of "0" at the addresses corresponding to the other timings. Is stored. Therefore, “1” is set in four consecutive addresses of the insertion timing data memory circuit 16.
Is stored.

The insertion timing generation circuit 14 sequentially counts up an address counter (not shown) for generating a memory address of the insertion timing data memory circuit 16 with the transmission highway clock signal 113, and the insertion timing is determined by the memory address from this address counter. The insertion timing data is read from the data memory circuit 16.

If the insertion timing data read from the insertion timing data memory circuit 16 is "1", the insertion timing generation circuit 14 generates the insertion timing 122 and outputs it to the memory circuit 12 as the read timing.

Therefore, the continuous data A, B, C and D are read from the memory circuit 12 at the timing of the insertion timing 122, inserted into the transmission highway data 112 by the highway data transmission circuit 13 and transmitted.

At this time, in the highway data transmission circuit 13, the transmission highway data signal 113 is temporarily output for the time required for the insertion timing generation circuit 14 to read the insertion timing data from the insertion timing data memory circuit 16 and to generate the insertion timing 122. Retained.

On the other hand, the case where the data A, B, C and D to be extracted in the received highway data signal 110 are dispersed will be described. In this case, the extraction timing data memory circuit 15 stores the timing data of "1" at the addresses corresponding to the timings of the data A, B, C, D, and "0" at the addresses corresponding to the other timings.
The timing data of is stored. Therefore, the data A, B, C, and
“1” is stored in the address corresponding to the timing of D.

The extraction timing generating circuit 11 receives an address counter for generating a memory address of the extraction timing data memory circuit 15 and receives the highway clock signal 1
The count-up is sequentially performed at 11, and the extraction timing data is read from the extraction timing data memory circuit 15 by the memory address from this address counter.

If the pull-out timing data read out from the pull-out timing data memory circuit 15 is "1", the pull-out timing generating circuit 11 pulls-out timing 12
1 is generated and output to the memory circuit 12 as a write timing.

Therefore, the dispersed data A, B, C, D are continuously written in the memory circuit 12 at the extraction timing 121. At this time, the highway data receiving circuit 10 receives the reception highway data signal 11 by the time required for the extraction timing generation circuit 11 to read the extraction timing data from the extraction timing data memory circuit 15 and to generate the extraction timing 121.
0 is temporarily held.

Next, the case where the data A, B, C and D to be inserted into the transmission highway data signal 112 are dispersed will be described. In this case, the insertion timing data memory circuit 16 stores the timing data of "1" at the addresses corresponding to the timings of the data A, B, C, and D, and the timing data of "0" at the addresses corresponding to the other timings. Is stored. Therefore, "1" is stored in the address corresponding to the timing of the data A, B, C, D of the insertion timing data memory circuit 16.

The insertion timing generation circuit 14 sends an address counter for generating the memory address of the insertion timing data memory circuit 16 to the highway clock signal 113.
Then, the insertion timing data is read out from the insertion timing data memory circuit 16 by the memory address from this address counter.

If the insertion timing data read from the insertion timing data memory circuit 16 is "1", the insertion timing generation circuit 14 generates the insertion timing 122 and outputs it to the memory circuit 12 as the read timing.

Therefore, the continuous data A, B, C, D are read from the memory circuit 12 at the timing of the insertion timing 122, distributed by the highway data transmission circuit 13 to the transmission highway data 112 and transmitted. . In this case, the data A and B are continuously inserted, and then one channel is opened and the data C and D are continuously inserted.

At this time, the transmission highway data signal 113 is temporarily sent by the highway data transmission circuit 13 for the time required for the insertion timing generation circuit 14 to read the insertion timing data from the insertion timing data memory circuit 16 and generate the insertion timing 122. Retained.

In practice, the test results of the device under test 3 used by the measuring device 4 for the measurement processing are often sent in a distributed manner, and the test results are extracted in advance and then the signal speed is converted. Since the pulled-out test result is arranged at a desired position and sent to the measuring device 4, software for collecting the test result of the device under test 3 in the measuring device 4 is unnecessary.

In the above description, the four data A, B,
Although the extraction and insertion for C and D have been described, if the extraction data number and the insertion data number match,
It is possible to correspond to an arbitrary number of data, and the timings of extracting and inserting them can be set arbitrarily.

Further, in the above description, the signal rate is the bit rate 8.192 MHz and the bit rate 32.76.
Although the case of 8 MHz has been described, the present invention can be applied to any signal rate.

As described above, the pull-out timing data indicating the pull-out timing of the data signal on the data highway 101 transmitting the data signal at the constant bit rate is stored in the pull-out timing data memory circuit 15 in advance, and the constant bit rate is also stored. Data highway 1 that transmits data signals at a bit rate different from
02, the insertion timing data indicating the insertion timing for the data signal on the upper side of the data circuit is stored in advance in the insertion timing data memory circuit 16, and the data signal of the data highway 101 is stored in the memory circuit 1 based on the extraction timing data.
2 to read a data signal from the memory circuit 12 based on the insertion timing data and transmit it to the data highway 102, thereby converting from a high bit rate speed to a low bit rate speed and a low bit rate speed. The conversion to a high bit rate speed can be performed using the same circuit.

Extraction timing data indicating the extraction timing of the data signals sent from the device under test 3 in a predetermined order through the data highway 101 that transmits the data signals at a constant bit rate is extracted. The measurement device 4 is stored in the timing data memory circuit 15 in advance and in a predetermined order through the data highway 102 that transmits a data signal at a bit rate different from the constant bit rate.
The insertion timing data indicating the insertion timing with respect to the data signal to be transmitted to the memory circuit 12 is stored in the insertion timing data memory circuit 16, and the data signal on the data highway 101 is stored in the memory circuit 12 based on the extraction timing data.
The test result of the device under test 3 can be transmitted to the measuring device 4 in real time by reading the data signal onto the data highway 102 from the memory circuit 12 based on the insertion timing data. The test result of the device under test 3 can be immediately processed by the measuring device 4.

Further, by rewriting the timing data of the extraction timing data memory circuit 15 and the insertion timing data memory circuit 16 respectively, different test results can be easily obtained.

[0070]

As described above, according to the signal speed conversion circuit for the data highway of the present invention, the extraction timing of the data signal on the first time division multiplex transmission line for transmitting the data signal at the constant bit rate is set. The extraction timing data shown is stored in advance, and the insertion timing data showing the insertion timing with respect to the data signal on the second time division multiplex transmission line which transmits the data signal at a bit rate different from the constant bit rate is stored. Memorizing means stores the data signal on the first time division multiplex transmission line in the storage means based on the extraction timing data, and stores the data signal on the second time division multiplex transmission line based on the insertion timing data. By reading from
There is an effect that conversion from a high bit rate speed to a low bit rate speed and conversion from a low bit rate speed to a high bit rate speed can be performed using the same circuit.

According to another data rate converting circuit for data highway of the present invention, it is predetermined from the device under test via the first time division multiplex transmission line for transmitting the data signal at a constant bit rate. A second time division multiplex transmission in which extraction timing data indicating the extraction timing of the data signals sent in a predetermined order is stored in advance and the data signal is transmitted at a bit rate different from the constant bit rate. The insertion timing data indicating the insertion timing with respect to the data signal to be sent to the measuring device in a predetermined fixed order via the path is stored, and the data signal on the first time division multiplex transmission path is stored based on the extraction timing data. The data signal is stored in the storage means and is read from the storage means based on the insertion timing data on the second time division multiplex transmission line. The test result of the device under test can be transmitted to the measuring device in real time by performing, and the test result of the device under test can be immediately processed by the measuring device, and different test results can be easily obtained. There is an effect that can be.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a data highway signal speed conversion circuit of FIG.

FIG. 3 is a diagram showing a relationship between a reception operation and a transmission operation according to an embodiment of the present invention and contents held in a memory circuit.

FIG. 4 is a diagram showing a relationship between a reception operation and a transmission operation according to an embodiment of the present invention and a content held in a memory circuit.

FIG. 5 is a block diagram showing a configuration of a signal speed conversion circuit for converting a high bit rate speed to a low bit rate speed in a conventional example.

FIG. 6 is a block diagram showing a configuration of a signal speed conversion circuit for converting from a low bit rate speed to a high bit rate speed in a conventional example.

FIG. 7 is a diagram showing a frame configuration example of a conventional example.

[Explanation of symbols]

 1, 2 data highway signal speed conversion circuit 3 device under test 4 measuring device 10 highway data receiving circuit 11 extraction timing generation circuit 12 memory circuit 13 highway data transmission circuit 14 insertion timing generation circuit 15 extraction timing data memory circuit 16 insertion timing data Memory circuit 17 Transmit clock generation circuit

Claims (8)

[Claims] 1. A second time division transmitting a data signal on a first time division multiplex transmission line for transmitting a data signal at a constant bit rate, and a data signal transmitting at a rate of a bit rate different from the constant bit rate. A data speed conversion circuit for a data highway for converting and outputting to a data signal on a multiplex transmission line, comprising: a storage means for storing the data signal on the first time division multiplex transmission line, and the first time division multiplex First storage means for storing pull-out timing data indicating a pull-out timing of a data signal on a transmission path;
The first timing generating means for generating the storage timing of the data signal on the first time division multiplex transmission path in the storage means based on the contents of the storage means of the first storage means, and the data signal stored in the storage means. Second storage means for storing insertion timing data indicating insertion timing for a data signal on the second time division multiplex transmission line, and on the second time division multiplex transmission line based on the contents of the second storage means. And a second timing generation means for generating a read timing of the data signal to the storage means from the storage means. 2. The first timing generation means is configured to read the extraction timing data from the first storage means based on a reception clock signal accompanying the data signal on the first time division multiplex transmission line. The second timing generation means is configured to read the insertion timing data from the second storage means based on a transmission clock signal accompanying the data signal on the second time division multiplexing transmission line. The signal speed conversion circuit for a data highway according to claim 1. 3. A receiving means for receiving a data signal on the first time division multiplex transmission line and temporarily holding the data signal, and a holding means for temporarily holding the data signal read from the storing means and the data signal. 2. A transmission means for transmitting on a second time division multiplex transmission path.
The signal speed conversion circuit for data highway according to claim 2. 4. The first timing generation means includes means for generating a read address for the first storage means based on a reception clock signal accompanying the data signal on the first time division multiplex transmission line, The second timing generation means includes means for generating a read address for the second storage means based on a transmission clock signal accompanying the data signal on the second time division multiplex transmission line. The signal speed conversion circuit for a data highway according to any one of claims 1 to 3. 5. A data signal sent from a device under test via a first time division multiplex transmission line that transmits a data signal at a constant bit rate, at a bit rate different from the constant bit rate. Second for transmitting data signal
A data speed conversion circuit for a data highway for converting to a data signal to be sent to a measuring device through the time division multiplex transmission line and outputting the data signal, the storing means storing the data signal on the first time division multiplex transmission line. And first storage means for storing extraction timing data indicating the extraction timing of the data signals sent from the device under test in a predetermined sequence, and based on the contents of the first storage means, First timing generation means for generating a storage timing of the data signal on the first time division multiplex transmission path in the storage means, and the measurement device for the data signals stored in the storage means in a predetermined fixed order. Second storage means for storing the insertion timing data indicating the insertion timing for the data signal to be sent to the second storage means, and the second time based on the contents of the second storage means. Data highway signal rate converter, characterized in that a second timing generating means for generating a read timing from the storage means of the data signals to division multiplexing transmission path. 6. The first timing generation means is configured to read the extraction timing data from the first storage means based on a reception clock signal accompanying the data signal on the first time division multiplex transmission line. The second timing generation means is configured to read the insertion timing data from the second storage means based on a transmission clock signal accompanying the data signal on the second time division multiplexing transmission line. The signal speed conversion circuit for a data highway according to claim 5. 7. A receiving means for receiving a data signal on the first time division multiplex transmission line and temporarily holding the data signal, and a holding means for temporarily holding the data signal read from the storing means and the data signal 6. Transmission means for transmitting on the second time division multiplexing transmission path.
Alternatively, the signal speed conversion circuit for data highway according to claim 6. 8. The first timing generation means includes means for generating a read address for the first storage means based on a reception clock signal accompanying the data signal on the first time division multiplex transmission line, The second timing generation means includes means for generating a read address for the second storage means based on a transmission clock signal accompanying the data signal on the second time division multiplex transmission line. The signal speed conversion circuit for a data highway according to any one of claims 5 to 7.