JP3428238B2 - Data processing device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention, in digital data communication, absorbs the phase difference between the two when the timing of the received data received from the network and the timing of the data processing at the receiving terminal are different. The present invention relates to a data processing device that processes this received data.

[0002]

2. Description of the Related Art Conventionally, in digital data communication, a method of mapping data into a frame of a predetermined length and transferring the data in a network has been adopted. In this system, each terminal (for example, TV phone, TV conference system,
Etc.) separates the received frame, extracts necessary data (voice data, image data, code data for computer communication, etc.), and performs data processing as appropriate.

The format of a frame having a predetermined length used in such digital data communication is ITU-TU.
Recommendation H. The frame format 221 will be described as an example. 26 to 28 show this H.264. It is a figure which shows the frame format of 221. As shown in these figures, H.264. The frame 221 has an octet period (8K
Hz) as a basic, and is configured as one frame with a cycle of 80 octets. Further, this octet cycle is divided into 1 to 96 time slots (TS).
This time slot is 8 if the network is a 64 Kbps network.
7 if the network is composed of bit units and the network is 56 Kbps
It is composed in bit units.

Therefore, according to this H.264. The communication speed of communication using the frame 221 is represented by the following equation (1). Communication speed = n × m × 8 [Kbps] (1) where n is the number of time slots in the octet cycle and m is the number of bits constituting each time slot in the octet cycle. For example, when the number of time slots is n = 1, the communication speed is 64 Kbps in the case of the 64 Kbps network (m = 8) (see FIG. 26) and 56 Kbps in the case of the 56 Kbps network (m = 7) ( See FIG. 27). Also, the number of time slots n = 6 and 64 Kbp
In case of s network (m = 8), communication speed is 384 Kbps
(See FIG. 28).

[0005] Such H. When the communication is performed using the frame format of 221, the terminal on the data receiving side generates an octet timing signal of 8 KHz, and uses this octet timing signal to separate the frames.
And processing the read data. At this time, in the INS network which is a digital communication network of Japan, a framing bit (vibration) is framed at each head of an octet cycle in a frame (for example, I
NS64), the terminal on the data receiving side can generate an 8 KHz octet timing signal used in the lower layer based on this framing bit. Since the octet timing signal in this case is naturally synchronized with the octet cycle of the received frame, the rising edge of the octet timing signal coincides with the timing of the octet cycle of the received frame.

On the other hand, the X.
Data transmission / reception in general digital communication other than INS, such as 21 interface, is performed without synchronizing with the octet timing on the terminal side. That is, the frame received by the receiving terminal is not framed so that the octet period can be known. Therefore, the receiving terminal must generate an octet timing signal used for frame separation and data processing at an arbitrary phase by using the clock supplied from the network. Therefore, it is rare that the generated octet timing signal and the octet cycle of the received frame are synchronized, and a situation occurs in which the beginning of the octet cycle of the data frame exists in the middle of the cycle of the octet timing signal. However, H. By using the framing bits extracted from the frame synchronization signal (FAS) included in the frame format of 221, the head of the octet cycle of the received frame can be detected.

Therefore, in a general receiving terminal for conventional digital communication in the related art, the timing of frame separation is set by the extracted framing bit, and the audio data and the like separated by using the framing bit are delayed to generate an octet periodic signal. I was trying to synchronize. FIG. 29 shows a conventional X. 21 shows the structure of a reception terminal for 21.

Referring to FIG. 29, the octet timing generation circuit 100 has an X. 21. Received data by the interface 21 is received from the network, and the received received data is transferred to the data separation circuit 101. The octet timing generation circuit 100 receives the received data and the clock signal carrying the received data from the network. Therefore, this clock signal is frequency-divided to generate an octet timing signal (binary signal) of 8 KHz, and the octet timing signal of 8 KHz is supplied to each circuit in the subsequent stage that performs processing in the lower layer.

The data separation circuit 101 incorporates a frame synchronization detection circuit. This frame sync detection circuit
It has a buffer of 8 columns × 9 rows as shown in FIG.
Received data is sequentially written in this buffer. Then, the bit pattern of the column in which the new bit is written is searched, and it is checked whether or not this matches the predetermined frame synchronization pattern (8-bit frame synchronization signal (FAS), see FIGS. When it is determined that the 8th bit constituting the frame synchronization pattern has been written, a frame pulse is output. The data separation circuit 101 inputs this frame pulse to each of the memory control circuits 105, 106 and 107, and also the bit rate allocation signal (BAS) (of the service channel in which the frame synchronization pattern is written in the frame format of H.221). The received data is distributed to each of the memories 102, 103 and 104 according to a cycle determined by 8 bits from the 9th octet to the 16th octet. For example, 2 bits from the bit received after the generation of the frame pulse are input to the audio memory 102 as audio data, 2 bits from the next bit are input to the code data memory 104 as code data, and 3 from the next bit. Image memory with bits as image data 1
03, and the next bit is internally retained as a service channel (note that each memory 102, 103, 104 is always supplied with a dummy signal of L or H during a period in which received data is not input). .). This output pattern is repeated thereafter until a new frame pulse is generated.

Each memory control circuit 105, 106, 107
When receiving the frame pulse from the data separation circuit 101, outputs the control information instructing the memories 102, 106 and 107 to start writing, and then detects the rising edge of the octet timing signal from the octet timing generation circuit 100. Then, each memory 102, 10
The control information for instructing the start of reading is output to 6, 107.

Each of the memories 102, 106 and 107 outputs control information for instructing the start of writing to each memory control circuit 10.
When receiving from 5, 106 and 107, the data separation circuit 1
The data input from 01 is written from the start address position. Further, when the control information instructing the start of reading is received, the written data is read from the head address position. As a result, each data after separation is stored in each of the memories 102, 106, 10
7, the phase difference with the octet timing signal is absorbed, and each data processing circuit 108, 109, 110 is synchronized with the octet timing signal.
Is output to.

Each data processing circuit 108, 109, 110
Is in accordance with the octet timing signal from the octet timing generation circuit 100.
The data of the lower layer received from 6, 107 is decelerated, and various processes are performed on these data. For example, the audio data processing circuit 108 D / A converts the audio data received in a digital format and outputs it as analog audio data. In addition, the image data processing circuit 10
9 is the image data received in digital format D
/ A conversion, and output as analog image data.

[0013]

As described above, the conventional data processing device described above includes the data separation circuit 10
1 in H.I. After the 221 frame is separated into lower layer data such as voice data, the lower layer data is delayed and synchronized with the octet timing signal used for processing these data. Therefore,
When a frame contains a plurality of types of low-layer signals that require processing in accordance with such octet timing signals, the same number of memory control circuits and memories are required as the number of these types. Therefore, the number of circuit units in the entire apparatus has increased, and the circuit scale has become large.

In view of the above problems, the object of the present invention is to generate an arbitrary signal in the receiving terminal when a plurality of types of data to be processed according to a predetermined periodic signal are included in a frame of a predetermined length. It is an object of the present invention to provide a data processing device capable of synchronizing the plurality of types of data with the periodic signal having the phase of 1 by a circuit unit common to the plurality of types of data.

[0015]

In order to solve the above problems, a data processing apparatus according to the present invention, as shown in the principle diagram of FIG. 1, includes a data frame including a plurality of types of data to be processed by a signal of a predetermined cycle. In a data processing device that processes a signal with a signal of the above-mentioned predetermined cycle generated in an arbitrary phase inside the device, a data phase detection circuit (200) for detecting the phase of the data frame and the data phase detection circuit (200) A phase difference detection circuit (201) for detecting a phase difference of the phase of the data frame with respect to the phase of the signal of the predetermined cycle, and the same amount of the data as the phase difference detected by the phase difference detection circuit (201). Data delay circuit (2
02), a data separation circuit (203) for separating the data frame delayed by the data delay circuit (202) for each of the plurality of types of data, and the data separated by the data separation circuit (203). A data processing circuit (20) for processing according to the signal of the predetermined cycle
Characterized by comprising a 4) and.

The contents of the present invention will be described below. The data frame may include a synchronization signal indicating a specific position within the frame. In this case, the data phase detection circuit extracts the synchronization signal from the data frame and notifies the phase difference detection circuit, and the phase difference detection circuit synchronizes the data frame with the signal of the predetermined cycle. The difference between the timing of the synchronization signal and the timing of the synchronization signal notified from the data phase detection circuit in the case of being performed can be detected as the phase difference.

The data frame is ITU-T
Recommendation H. It can be a frame according to 221. In this case, the sync signal is the frame sync signal (F) written in the service channel of this data frame.
AS) can be used. Further, in this case, a binary signal having an octet period of 8 KHz is used as the signal having the predetermined period. Further, in this case, the plurality of types of data to be processed by the signal of the processing cycle include audio data, image data, code data, and the like. Further, in this case, the phase of the data frame means the phase of the octet period of the data frame. That is, in a 64 Kbit network, 8 × n (n is the number of time slots) bits make up one cycle, and in a 56 Kbit network, 7 × n bits make up one cycle. Further, in this case, the phase difference can be a time difference between the beginning of the octet cycle of the data frame and the rising time point or the falling time point of the binary signal (signal of a predetermined cycle).

When the frame is composed of one time slot, the phase difference detection circuit counts one bit for each cycle of the signal of the predetermined cycle and the phase detection circuit outputs the synchronization signal. And a bit counter that outputs a count value when the data frame is received, and a count value that is output from the bit counter can be output from the bit counter when the data frame is synchronized with the signal of the predetermined cycle. It can be configured by a phase difference calculation circuit that calculates a phase difference by subtracting from the reference count value. With this configuration, the phase difference can be grasped with a simple configuration.

As described above, the data frame is IT
U-TU Recommendation H.264. 221 according to 221
The data frame may be composed of a plurality of time slots, and the sync signal may be written in the first time slot of the data frame.
It In this case, it may be detected phase difference in the same way as for the one time slot as described above, but may be configured to phase difference detecting circuit as follows. That is, when the phase difference detection circuit divides the cycle of the signal of the predetermined cycle into the plurality of time slots, counts one bit for each time slot, and receives the synchronization signal from the data phase detection circuit. A bit counter that outputs a count value, a time slot counter that counts the time slot for each period of the signal of the predetermined period and outputs a count value when the synchronization signal is received from the data phase detection circuit, It consists a phase difference calculation circuit for calculating a phase difference based on a count value output counted value output from the bit counter from the time slot counter. By doing so, the counter that counts the output timing of the synchronization signal can be divided into two, so the counter value that each counter counts becomes a small value. Therefore, it is possible to avoid an increase in the number of digits of the counter.

The phase difference calculation in this case may be performed as follows. That is, the time slot counter is reset at the beginning of each cycle of the signal of the predetermined cycle, the first time slot after the reset is counted as 0, the next time slot is counted as i, and the time slot is thereafter counted. The count value is decremented each time. Then, the phase difference calculation circuit sets the counter value output from the bit counter to Pbitn and the counter value output from the time slot counter to Pts.
n, A is a reference count value that can be output from the bit counter when the data frame is synchronized with the signal of the predetermined cycle, and TS is the number of the time slots.
In the case of n, the phase difference D is expressed by the equation D = (Ptsn-
(TSn−1) 's complement to i) × 10 + (A−Pb
Itn). Then, when the number of bits included in one time slot in one cycle of the data frame is m, the data delay circuit causes the phase difference D
Is calculated as an m-ary number, the phase difference D is converted into a decimal number, and the data frame is delayed by the same amount as the converted number.

The data delay circuit is composed of a plurality of stages of shift registers and a selector circuit for selecting one of the input data and the significant output data of the shift register which has the same delay amount as the phase difference. it may be.
With this configuration, the delay amount of the data frame delayed by the data delay circuit can be changed with a simple configuration.

Further, the data separation circuit recognizes the position of the data frame by the frame synchronization signal, extracts the bit rate allocation signal written in the service channel of the data frame, and according to this bit rate allocation signal. it can be composed of the data frame so as to separate the plurality of types of data.
In this case, the data phase detection circuit extracts the frame synchronization signal from the data frame that has passed through the data delay circuit and inputs this synchronization signal to the data separation circuit, and the phase difference calculation means temporarily outputs the phase difference. the upon detecting the phase difference has disappeared after detecting may be configured to hold the phase difference detected immediately before. By doing so, it is not necessary for the data separation circuit to generate the frame synchronization signal necessary for performing the separation, so that the configuration of the data separation circuit can be simplified.

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

[0024]

[First Embodiment] FIG. 2 is a block diagram showing a schematic configuration of a data processing apparatus according to a first embodiment of the present invention.

In FIG. 2, the octet timing generation circuit 1 operates from the network (64 Kbps network, 56 Kbps network) to the X.X. 21. Receive data according to the interface.
This received data is H.264. Since the frame is formatted according to 221, the frame structure of the received data is continuous and periodic. The octet timing generation circuit 1 transfers the received data (data frame) to the frame synchronization detection circuit 2 and the data delay circuit 4.

Further, the octet timing generation circuit 1
Receives the received data as well as clock pulses for carrying the received data from the network. The bit timing of this clock pulse is shown in FIG. The octet timing generation circuit 1 divides this bit timing to autonomously generate an octet timing signal (a signal having a predetermined cycle) which is a binary signal of 8 KHz (see FIG. 4A). However, since the octet timing generation circuit 1 itself cannot know the phase of the octet cycle of each frame constituting the received data, the initial phase of the octet timing signal generated from the octet timing generation circuit 1 is arbitrary. The generated octet timing signal is input to the phase difference detection circuit 3, the data separation circuit 6, the audio data processing circuit 7, the image data processing circuit 8, and the code data processing circuit 9.

The frame synchronization detection circuit 2 as the data phase detection circuit is composed of 8 columns × 9 rows (56 Kb) as shown in FIG.
It has a buffer of 7 columns × 9 rows in the case of it network, and the received data is sequentially written in this buffer. Then, the bit pattern of the column in which the new bit is written is searched, and whether this matches the predetermined frame synchronization pattern (corresponding to an 8-bit frame synchronization signal (FAS), a synchronization signal indicating a specific position in the frame) It is checked whether or not the frame pulse is output when it is determined that the 8th bit constituting the predetermined frame synchronization pattern has been written (that is, the synchronization signal is extracted from the data frame and notified to the phase difference detection circuit 3). .). FIG. 3 shows a state in which it is detected that the frame synchronization pattern is written in the shaded portion. That is, the frame synchronization detection circuit 2 can output a frame pulse at the 8th bit from the beginning of the octet period of the frame in the case of a 64 Kbit network. Further, in the case of a 56 Kbit network, a frame pulse can be output at the 7th bit from the beginning of the octet period of the frame.

Now, in an ideal state where the beginning (rising edge) of the octet timing signal and the beginning of the octet cycle of the frame match, the frame synchronization pattern is 8 from the rising edge of the octet timing signal.
It is detected at the time of the bit (7th bit in the case of the 56 Kbit network) (see FIG. 4C), and at the same time, the frame pulse is output (see FIG. 4D). However,
As described above, since the octet timing signal is generated at an arbitrary initial phase, in reality, the 1st to 8th bits (56K) from the rising edge of the octet timing signal.
In the case of a bit network, the frame synchronization pattern is detected at any one of the 1st to 7th bits), and the frame pulse is output. FIGS. 4 (c ') and (d') show a state in which the frame synchronization pattern is detected and the frame pulse is output with a 6-bit lead phase difference with respect to the ideal states in FIGS. Show.

The phase difference detection circuit 3 uses the actual timing of the frame pulse input from the frame synchronization detection circuit 2 as a reference value (frame pulse output timing in an ideal state: in the case of a 64 Kbit network, from the rise of the octet timing signal). In the case of the 8th bit, 56 Kbit network, 7 from the rising edge of the octet timing signal.
Compared with the bit value), the advance phase difference of the frame pulse reception timing with respect to the reference value (the timing of the synchronization signal when the data frame is synchronized with the signal of the predetermined cycle and the data phase detection circuit notifies it) The difference with the timing of the sync signal is calculated.

That is, the phase difference detection circuit 3 allocates a time slot to the octet timing signal in synchronization with the time slot cycle of the received data frame from the rising edge of the octet timing signal. Then, the bit position within the time slot of the frame pulse reception timing is Pbitn, and the phase difference D is expressed by the following equation (2),
Calculated according to (3).

When the frame pulse is received during the first time slot from the rising edge of the octet timing signal D = A-Pbitn (2) The second or later time slot from the rising edge of the octet timing signal of the frame pulse When received during D = (Ptsn− (TSn−1) 's complement) × 10 + (A−Pbitn) (3) However, A is a reference value (8,56 for 64 Kbit network).
In case of Kbit network, 7) is shown. In addition, TSn (TSn
= 1 to 96) indicates the number of time slots included in one frame. Since the number of time slots TSn is constant with respect to the communication speed, it is set by the CPU or the like of the communication terminal each time the communication speed is determined. Also, Ptsn
Is a time slot number attached to each time slot, and 0 → i → (i
It is attached while being decremented, such as -1) → (i-2) → .... The “complement of (TSn−1)” is the complement of (TSn−1) with respect to i.

In the example of FIG. 4, when the number of time slots is 2 in the 64 Kbps network, that is, the communication speed is 128 Kbp.
The case of s is shown. Therefore, A = 8 and TSn = 2 are set. Further, as shown in FIG. 4 (d '), the frame bit is 1 from the rising edge of the octet timing.
Received during the th time slot and its bit position P
Bitn is assumed to be 2. As a result, the equation is applied, and the phase difference D is calculated as D = 8-6 = 2 (4).

The phase difference D thus calculated is notified to the data delay circuit 4. The data delay circuit 4 delays the reception data received from the octet timing generation circuit 1 by the same time as the phase difference notified from the phase difference detection circuit 3. However, at this time, the data delay circuit 4 sets the phase difference D notified from the phase difference detection circuit 3 in octal (56
In the case of the Kbit network, it is recognized as a numerical value of a 7-ary number, and this numerical value is converted into a decimal number to obtain the delay amount of the received data. As a result, the octet cycle of the received data frame delayed by the data delay circuit 4 is synchronized with the octet timing signal generated by the octet timing generation circuit 1. This data delay circuit 4
The received data delayed by is input to the data separation circuit 6.

The data separation circuit 6 incorporates a frame sync detection circuit having the same function as the frame sync detection circuit 2.
As described above, since the octet cycle of the received data frame is synchronized with the octet timing signal at the time of being input to the data separation circuit 6, the built-in frame synchronization detection circuit is always shown in FIG. The frame synchronization pattern is detected at the timing shown, and the frame pulse is output at the reference position shown in FIG. The data separation circuit 6 identifies the beginning of the frame according to this frame pulse, and extracts the bit rate allocation signal (BAS) contained in the 9th octet to the 16th octet of the service channel of the frame. Then, each time the rising edge of the octet timing signal is detected, the received data is distributed to the data processing circuits 7, 8 and 9 according to the cycle determined by the bit rate allocation signal (BAS). For example, 2 bits from the beginning of the octet cycle are input to the audio data processing circuit 7 as audio data, 2 bits from the next bit are input to the code data processing circuit 9 as code data, and 3 bits from the next bit are imaged. It is input as data to the image data processing circuit 8 and the next bit is retained internally as a service channel. Then, the distribution of the received data is repeated for the number of time slots.

Each of the data processing circuits 7, 8 and 9 decelerates the data respectively received from the data separation circuit 6 according to the octet timing from the octet timing generation circuit 1 and performs various processings on these data. For example, the audio data processing circuit 7 D / A converts the audio data received in the digital format and outputs it as analog audio data. Further, the image data processing circuit 8 converts the image data received in the digital format into D
/ A conversion, and output as analog image data.

According to the data processing apparatus of this embodiment, the received data frame is delayed before the data separation circuit 6 separates the frames, and the octet timing signal is generated autonomously by the octet timing generation circuit 1. Can be synchronized. Therefore, data that requires processing according to the octet timing is H.264. Even when a large number of types are included in 221 frames, only one each of the phase difference detection circuit 3 and the data delay circuit 4 is required. That is,
Even if there are a plurality of such data, it is not necessary to provide the phase difference detection circuit 3 and the data delay circuit 4 for each data. Therefore, the phase difference detection circuit 3 and the data delay circuit 4 can be efficiently used to reduce the scale of the entire circuit. Further, a series of operations from the calculation of the phase difference to the phase absorption of data (variable delay) is automatically performed by the hardware. That is, since it can be performed without intervention of a CPU or the like, high-speed processing can be realized.

More detailed structures of the data processing apparatus according to the first embodiment will be shown in the following examples.

[0038]

First Embodiment A first embodiment shows a data synchronizer compatible with a frame having a communication speed (n × (m × 8)) Kbps in a (m × 8) Kbps network (where n is 96 at the maximum). , M is 7 or 8). As shown in FIG. 6, the frame format in this case is composed of n time slots, and the number of bits in the octet period in each time slot is m. In this case, the ideal state is that the frame pulse is received at the m-th bit from the rising edge of the octet signal.

FIG. 5 is a block diagram of a data processing device according to the first embodiment. The bit counter 31 in FIG.
Time slot counter 32 and phase difference calculation circuit 33
Constitutes the phase difference detection circuit 3 shown in FIG. The shift register 41, the selector 42, and the conversion circuit 43 in FIG. 5 configure the data delay circuit 4 shown in FIG.
Then, the reception data received by the octet timing generation circuit 1 is input to the shift register 41 together with the frame synchronization detection circuit 2. The octet timing signal generated by the octet timing generation circuit 1 is input to the bit separator 31 and the time slot counter 32 as well as the data separation circuit 6 and the data processing circuits 7, 8 and 9.

The bit counter 31 is reset each time the rising edge of the octet timing signal from the octet timing generating circuit 1 is detected, counts each bit timing, and repeatedly generates a count value of 1 to m internally. Then, the bit counter 31 outputs the count value x at the time when the frame pulse is received from the frame synchronization detection circuit 2 as Pbitn. This P
The bitn is input to the phase difference calculation circuit 33.

The time slot counter 32 is reset each time the rising edge of the octet timing signal from the octet timing generation circuit 1 is detected, and the time slot number Ptsn is counted every m bits. That is, as described above, Ptsn = 0 is counted from the rising edge of the octet timing signal to 8 bits, Ptsn = i is counted during the subsequent 8-bit period, and Ptsn = (i− is counted during the subsequent 8-bit period.
1) and Ptsn = during the subsequent 8-bit period.
(I-2) is counted, and thereafter, Pt is counted every 8 bits until the rising edge of the next octet timing signal is detected.
Decrement sn. For example, when i = 95 is set, the time slot counter 32 displays 0 → 95.
→ 94 → ... → 1 → 0 → 95 → ... Then, the time slot counter 32 outputs the count value y at the time when the frame pulse is received from the frame synchronization detection circuit 2 as Ptsn. This Ptsn
Is input to the phase difference calculation circuit 33.

The phase difference calculating circuit 33 calculates the lead phase difference of the received data with respect to the octet timing signal based on these count values Pbitn and Ptsn. The phase difference calculation circuit 33 has a reference value A (=
m) and the number of time slots TSn (= n) are set. The calculation in the phase difference calculation circuit 33 is performed by the decimal system. Then, in the phase difference calculation circuit 33, the ones value b and the tens value a that compose the phase difference D.
Are calculated separately, and the values a + b are added and output as the phase difference D. That is, it is calculated as follows according to the equation (3).

D = (Ptsn- (TSn-1) 's complement) × 10 + (A-Pbitn) = (Ptsn- (n-1)' s complement) × 10 + (m-Pbitn) = (y- (n-1) ) × 10 + (mx) = a + b (5) However, the complement of (n-1) is the complement of (n-1) with respect to i.

The phase difference D calculated by the phase difference calculating circuit 33 in this way is not a decimal number representing the total number of bits of the phase difference, but the digit (a) of 10 represents the phase difference in time slot units. In addition, the digit of 1 (b) is a numerical value indicating the phase difference in bit units within the time slot.
The value of this phase difference D is input to the conversion circuit 43.

The conversion circuit 43 recognizes the input value of the phase difference D as a m-ary number and converts it into a decimal number, thereby expressing the total number of bits of the phase difference (delay). Amount). Specifically, the conversion circuit 4
3 stores the table for m = 8 shown in Table 1 and the table for m = 7 shown in Table 2, and outputs the value of the delay amount corresponding to the input value of the phase difference D. is there.

[0046]

[Table 1]

[0047]

[Table 2]

The delay amount thus obtained is input to the selector circuit 42 as a selection signal. On the other hand, the shift register 41 is composed of 767 stages of flip-flops, and transmits the reception data received from the octet timing generation circuit 1 to the next stage flip-flop while delaying it by 1 bit from the beginning. The input signal of the shift register 41 and the output signal of each stage flip-flop are transmitted to the respective next-stage flip-flops, taken out of the shift register 41 and inputted to the selector circuit 42. In this way, the received data with the delay amount of 0 bits to the received data with the delay amount of 767 bits are input to the selector circuit 42, respectively.

The selector circuit 42 is a shift register 41.
From among the received data having the respective delay amounts of 0 to 767 bits input from, those having the delay amount matching the delay amount indicated by the selection signal are selected. The delay amount of the selected reception data matches the lead phase difference of the reception data at the time of reception with respect to the octet timing signal. Therefore, the received data passing through the selector circuit 42 is synchronized with the octet timing signal from the octet timing generation circuit 1. Therefore, the data separation circuit 6 to which this received data is transferred
Can perform frame separation according to the octet timing signal. The audio data processing circuit 7, the image data processing circuit 8, and the code data processing circuit 9 are
Each separated data (voice data, image data, code data) can be processed by using an octet timing signal synchronized with this.

[0050]

[Embodiment 2] Embodiment 2 uses the apparatus of Embodiment 1 at 64 Kbp.
It shows an example corresponding to a frame having a communication speed of 64 Kbps in the s network. The frame format in this case is composed of one time slot as shown in FIG. 8, and the number of bits in the octet period is eight. In this case, it is ideal that the frame pulse is received at the 8th bit from the rising edge of the octet signal.

FIG. 7 is a block diagram of a data processing device according to the second embodiment. In this case, the reference value A = 8 is set. Further, since the maximum phase difference is 7 bits, only 7 flip-flops in the shift register 41 are used.
Further, since the number of time slots is 1, the time slot counter 32 is not used. In addition, the phase difference calculation circuit 3
3 calculates only the value b of one digit. In addition, the conversion circuit 4
3 outputs the input value of the phase difference D as it is. It is assumed that the octet timing generation circuit 1 receives the data frame and generates the octet timing signal in the phase shown in FIG. 9A in the state set as described above. Then, the bit counter 31 is reset each time the rising edge of the octet timing signal is detected, counting is performed at each bit timing shown in FIG. 9B, and as shown in FIG. The count value of is internally generated.

It is also assumed that the frame synchronization detection circuit 2 detects a frame synchronization pattern from the received data at the timing shown in FIG. 9D and outputs a frame pulse at the timing shown in FIG. 9E. Then bit counter 3
1 outputs / holds the counter value 6 at the time of receiving the frame pulse as the frame pulse position Pbitn.

The phase difference calculation circuit 33 uses this Pbitn =
6 is compared with the reference value A = 8 indicating the ideal state described above. This reference value A = 8 corresponds to the 8th bit from the rising edge of the octet timing signal, as shown in FIG. 9 (f). Therefore, the phase difference calculation circuit 33 calculates the lead phase difference D of the frame pulse position Pbitn = 6 with respect to the reference position A = 8 according to the equation (2) as follows.

D = A-Pbitn = 8-6 = 2 (6) This phase difference D is converted by the conversion circuit 43 into a selection signal indicating a 2-bit delay and supplied to the selector circuit 42.

The selector circuit 42 selects the received data having the delay amount of 2 bits according to this selection signal. The received data having the delay amount of 2 bits is, as shown in FIG.
It matches the received data in the ideal state and is synchronized with the octet timing signal from the octet timing generation circuit 1.

The received data is input to the data separation circuit 6, and the frame pulse is extracted by the data separation circuit 6. This extracted frame pulse is shown in FIG.
As shown in (h), it coincides with the reference position in FIG. 9 (f). Therefore, the data separation circuit 6 can separate the data based on the frame pulse and the octet timing signal.

The separated data (voice data, image data, code data) is synchronized with the voice data processing circuit 7, the image data processing circuit 8 or the code data processing circuit 9, respectively. It is processed using an octet timing signal.

[0058]

[Embodiment 3] Embodiment 3 uses the apparatus of Embodiment 1 at 64 Kbp.
It shows an example corresponding to a frame having a communication speed of 192 Kbps in the s network. The frame format in this case is composed of three time slots as shown in FIG. 11, and the number of bits in the octet period in each time slot is eight. In this case, it is ideal that the frame pulse is received at the 8th bit from the rising edge of the octet signal.

FIG. 10 is a block diagram of a data processing device according to the third embodiment. In this case, the reference value A = 8 and the number of time slots n = 3 are set. The maximum phase difference is 2
Since it is 3 bits, only 23 stages of flip-flops in the shift register 41 are used. Further, the time slot counter 32 counts the above i as 7. Further, the conversion circuit 43 uses the table 1 for the input phase difference D.
Apply the table of.

It is assumed that the octet timing generation circuit 1 receives the data frame and generates the octet timing signal in the phase shown in FIG. 12A in the state set as described above. Then, the bit counter 31
It is reset each time the rising edge of the octet timing signal is detected, counting is performed at each bit timing shown in FIG. 12B, and as shown in FIG.
The count values up to 8 are internally generated. The time slot counter 32 is reset each time the rising edge of the octet timing signal is detected.
As shown in (d), 0 → 7 → 6 → 0 → 7 every 8 bits
The count value is internally generated in the order of → 6 →.

It is also assumed that the frame synchronization detection circuit 2 detects a frame synchronization pattern from the received data at the timing shown in FIG. 12 (e) and outputs a frame pulse at the timing shown in FIG. 12 (f). Then, the bit counter 31 outputs and holds the counter value 2 at the time of receiving the frame pulse as the frame pulse position Pbitn. The time slot counter 32 outputs and holds the counter value 7 at the time of receiving the frame pulse as the time slot number Ptsn.

The phase difference calculation circuit 33 uses the count value P
Bitn = 2 and Ptsn = 7 are compared with the reference value A = 8 indicating the ideal state described above. This reference value A = 8 is shown in FIG.
As shown in 2 (g), it corresponds to the 8th bit from the rising edge of the next octet timing signal. Therefore, the phase difference calculating circuit 33 calculates the lead phase difference D of the frame pulse position (Pbitn = 2, Ptsn = 7) with respect to the reference position A = 8 according to the equation (3) as follows.

D = (Ptsn- (TSn-1) 's complement) × 10 + (A-Pbitn) = (7- (3-1)' s complement) × 10 + (8-2) = (7-2's complement) × 10 + 6 (7) Here, the “two's complement” is the complement of 2 for i = 7, that is, five. Therefore, D = (7-5) × 10 + 6 = 26 (8)

The phase difference D = 26 is recognized as an octal value in the conversion circuit 43 and converted into a decimal value. That is, from the table shown in Table 1, this phase difference D = 26
Is read out, and this value 22 is input to the selector circuit 42 as a selection signal indicating the delay amount (22 bits) of the received data with respect to the octet timing signal.

The selector circuit 42 selects the received data with the delay amount of 22 bits according to this selection signal. As shown in FIG. 12 (h), the received data with the delay amount of 22 bits matches the received data in the ideal state, and is synchronized with the octet timing signal from the octet timing generation circuit 1.

The received data is input to the data separation circuit 6, and the frame pulse is extracted by the data separation circuit 6. This extracted frame pulse is shown in FIG.
As shown in 2 (i), it coincides with the reference position in FIG. 12 (g). Therefore, the data separation circuit 6 can separate the data based on the frame pulse and the octet timing signal.

The separated data (voice data, image data, code data) are synchronized with the data in the voice data processing circuit 7, the image data processing circuit 8 or the code data processing circuit 9, respectively. It is processed using an octet timing signal.

[0068]

[Fourth Embodiment] In the fourth embodiment, the apparatus of the first embodiment is 56 Kbp.
It shows an example corresponding to a frame having a communication speed of 280 Kbps in the s network. In this case, the frame format is composed of 5 time slots as shown in FIG. 14, and the number of bits in the octet period in each time slot is 7. In this case, the ideal state is that the frame pulse is received at the 7th bit from the rising edge of the octet signal.

FIG. 13 is a block diagram of a data processing device according to the fourth embodiment. In this case, the reference value A = 7 and the number of time slots n = 5 are set. Also, the maximum phase difference is 3
Since it is 4 bits, only 34 stages of flip-flops in the shift register 41 are used. Further, the time slot counter 32 counts the above i as 7. Further, the conversion circuit 43 uses the table 2 for the input phase difference D.
Apply the table of.

In the state thus set, it is assumed that the octet timing generation circuit 1 receives the data frame and generates the octet timing signal in the phase shown in FIG. 15 (a). Then, the bit counter 31
It is reset each time the rising edge of the octet timing signal is detected, and counting is performed for each bit timing shown in FIG. 15B, and as shown in FIG.
The count values up to 8 are internally generated. The time slot counter 32 is reset each time the rising edge of the octet timing signal is detected, and the time slot counter 32 shown in FIG.
As shown in (d), 0 → 7 → 6 → 5 → 4 every 7 bits
The count value is internally generated in the order of → 0 → 7 → 6 → ....

It is also assumed that the frame synchronization detection circuit 2 detects a frame synchronization pattern from the received data at the timing shown in FIG. 15 (e) and outputs a frame pulse at the timing shown in FIG. 15 (f). Then, the bit counter 31 outputs / holds the counter value 6 at the time of receiving the frame pulse as the frame pulse position Pbitn. The time slot counter 32 outputs and holds the counter value 4 at the time of receiving the frame pulse as the time slot number Ptsn.

The phase difference calculation circuit 33 uses the count value P
Bitn = 6 and Ptsn = 4 are compared with the reference value A = 7 indicating the ideal state described above. This reference value A = 7 is shown in FIG.
As shown in FIG. 5 (g), it corresponds to the 7th bit from the rising edge of the next octet timing signal. Therefore, the phase difference calculating circuit 33 calculates the lead phase difference D of the frame pulse position (Pbitn = 6, Ptsn = 4) with respect to the reference position A = 7 according to the equation (3) as follows.

D = (Ptsn- (TSn-1) 's complement) × 10 + (A-Pbitn) = (4- (5-1)' s complement) × 10 + (7-6) = (4-4's complement) × 10 + 1 (9) Here, the “4's complement” is the complement of 4 for i = 7, that is, 3. Therefore, D = (4-3) × 10 + 1 = 11 (10)

This phase difference D = 11 is recognized in the conversion circuit 43 as a value in a 7-ary number and converted into a value in a decimal number. That is, from the table shown in Table 2, this phase difference D = 11
Value 8 corresponding to is read, and this value 8 is the delay amount (8 bits) of the received data with respect to the octet timing signal.
Is input to the selector circuit 42 as a selection signal indicating.

The selector circuit 42 selects the received data with the delay amount of 8 bits according to this selection signal. As shown in FIG. 15 (h), the received data with the delay amount of 8 bits matches the received data in the ideal state, and is synchronized with the octet timing signal from the octet timing generation circuit 1.

The received data is input to the data separation circuit 6, and the frame pulse is extracted by the data separation circuit 6. This extracted frame pulse is shown in FIG.
As shown in FIG. 5 (i), it coincides with the reference position in FIG. 15 (g). Therefore, the data separation circuit 6 can separate the data based on the frame pulse and the octet timing signal.

The separated data (voice data, image data, code data) is synchronized with the data in the voice data processing circuit 7, the image data processing circuit 8 or the code data processing circuit 9, respectively. It is processed using an octet timing signal.

[0078]

[Embodiment 5] Embodiment 5 uses the apparatus of Embodiment 1 at 64 Kbp.
It shows an example corresponding to a frame having a communication speed of 384 Kbps in the s network. The frame format in this case is composed of 6 time slots, and the number of bits in the octet period in each time slot is 8. In this case, it is ideal that the frame pulse is received at the 8th bit from the rising edge of the octet signal.

FIG. 16 is a block diagram of a data processing device according to the fifth embodiment. In this case, the reference value A = 8 and the number of time slots n = 6 are set. The maximum phase difference is 4
Since it is 7 bits, only 47 stages of flip-flops in the shift register 41 are used. The time slot counter 32 counts i as 95 described above.
Further, the conversion circuit 43 applies the table of Table 1 to the input phase difference D.

In the state set in this way, the data synchronizing circuit of the fifth embodiment performs the control as described in the first embodiment. That is, the phase difference calculation circuit 33 calculates the phase difference D between the octet timing signal generated by the octet timing generation circuit 1 and the received data, and the conversion circuit 43 reads the delay amount corresponding to this phase difference D. Then, the selector 42 selects one of the received data from the shift register 41, which has this delay amount. Other configurations and operations in this embodiment are the same as those described in the first embodiment, and thus the description thereof will be omitted.

[0081]

[Sixth Embodiment] In the sixth embodiment, the apparatus of the first embodiment is installed at 64 Kbp.
It shows an example corresponding to a frame having a communication speed of 320 Kbps in the s network. The frame format in this case is composed of five time slots, and the number of bits in the octet period in each time slot is eight. In this case, it is ideal that the frame pulse is received at the 8th bit from the rising edge of the octet signal.

FIG. 17 is a block diagram of a data processing device according to the sixth embodiment. In this case, the reference value A = 8 and the number of time slots n = 5 are set. Also, the maximum phase difference is 3
Since it is 9 bits, only 39 flip-flops in the shift register 41 are used. The time slot counter 32 counts i as 95 described above.
Further, the conversion circuit 43 applies the table of Table 1 to the input phase difference D.

In the state thus set, the data synchronizing circuit of the sixth embodiment performs the control as described in the first embodiment. That is, the phase difference calculation circuit 33 calculates the phase difference D between the octet timing signal generated by the octet timing generation circuit 1 and the received data, and the conversion circuit 43 reads the delay amount corresponding to this phase difference D. Then, the selector 42 selects one of the received data from the shift register 41, which has this delay amount. Other configurations and operations in this embodiment are the same as those described in the first embodiment, and thus the description thereof will be omitted.

[0084]

[Embodiment 7] In Embodiment 7, the apparatus of Embodiment 1 is installed at 64 Kbp.
It shows an example corresponding to a frame having a communication speed of 256 Kbps in the s network. The frame format in this case is composed of four time slots, and the number of bits in the octet period in each time slot is eight. In this case, it is ideal that the frame pulse is received at the 8th bit from the rising edge of the octet signal.

FIG. 18 is a block diagram of a data processing device according to the seventh embodiment. In this case, the reference value A = 8 and the number of time slots n = 4 are set. Also, the maximum phase difference is 3
Since it is 1 bit, only 31 stages of flip-flops in the shift register 41 are used. The time slot counter 31 counts i as 95 described above.
Further, the conversion circuit 43 applies the table of Table 1 to the input phase difference D.

In the state thus set, the data synchronizing circuit of the seventh embodiment performs the control as described in the first embodiment. That is, the phase difference calculation circuit 33 calculates the phase difference D between the octet timing signal generated by the octet timing generation circuit 1 and the received data, and the conversion circuit 43 reads the delay amount corresponding to this phase difference D. Then, the selector 42 selects one of the received data from the shift register 41, which has this delay amount. Other configurations and operations in this embodiment are the same as those described in the first embodiment, and thus the description thereof will be omitted.

[0087]

[Embodiment 8] Embodiment 8 uses the apparatus of Embodiment 1 at 64 Kbp.
It shows an example corresponding to a frame having a communication speed of 128 Kbps in the s network. The frame format in this case is composed of two time slots, and the number of bits in the octet period in each time slot is eight. In this case, it is ideal that the frame pulse is received at the 8th bit from the rising edge of the octet signal.

FIG. 19 is a block diagram of a data processing device according to the eighth embodiment. In this case, the reference value A = 8 and the number of time slots n = 2 are set. The maximum phase difference is 1
Since it is 5 bits, only 15 stages of flip-flops in the shift register 41 are used. The time slot counter 31 counts i as 95 described above.
Further, the conversion circuit 43 applies the table of Table 1 to the input phase difference D.

In the state thus set, the data synchronizing circuit of the eighth embodiment performs the control as described in the first embodiment. That is, the phase difference calculation circuit 33 calculates the phase difference D between the octet timing signal generated by the octet timing generation circuit 1 and the received data, and the conversion circuit 43 reads the delay amount corresponding to this phase difference D. Then, the selector 42 selects one of the received data from the shift register 41, which has this delay amount. Other configurations and operations in this embodiment are the same as those described in the first embodiment, and thus the description thereof will be omitted.

[0090]

[Embodiment 9] Embodiment 9 uses the apparatus of Embodiment 1 at 56 Kbp.
It shows an example corresponding to a frame having a communication speed of 336 Kbps in the s network. The frame format in this case is composed of 6 time slots, and the number of bits in the octet period in each time slot is 7. In this case, the ideal state is that the frame pulse is received at the 7th bit from the rising edge of the octet signal.

FIG. 20 is a block diagram of a data processing device according to the ninth embodiment. In this case, the reference value A = 7 and the number of time slots n = 6 are set. The maximum phase difference is 4
Since it is 1 bit, only 41 stages of flip-flops in the shift register 41 are used. The time slot counter 31 counts i as 95 described above.
Further, the conversion circuit 43 applies the table of Table 2 to the input phase difference D.

In the state thus set, the data synchronizing circuit of the ninth embodiment performs the control as described in the first embodiment. That is, the phase difference calculation circuit 33 calculates the phase difference D between the octet timing signal generated by the octet timing generation circuit 1 and the received data, and the conversion circuit 43 reads the delay amount corresponding to this phase difference D. Then, the selector 42 selects one of the received data from the shift register 41, which has this delay amount. Other configurations and operations in this embodiment are the same as those described in the first embodiment, and thus the description thereof will be omitted.

[0093]

[Embodiment 10] Embodiment 10 uses the apparatus of Embodiment 1 at 56K.
It shows an example corresponding to a frame having a communication speed of 224 Kbps in a bps network. The frame format in this case is composed of four time slots, and the number of bits in the octet period in each time slot is seven. In this case, the ideal state is that the frame pulse is received at the 7th bit from the rising edge of the octet signal.

FIG. 21 is a block diagram of a data processing device according to the tenth embodiment. In this case, the reference value A = 7 and the time slot number n = 4 are set. Since the maximum phase difference is 27 bits, only 27 flip-flops in the shift register 41 are used. The time slot counter 31 counts i as 95 described above. Further, the conversion circuit 43 applies the table of Table 2 to the input phase difference D.

In the state thus set, the data synchronizing circuit of the tenth embodiment carries out the control as described in the first embodiment. That is, the phase difference calculation circuit 33 calculates the phase difference D between the octet timing signal generated by the octet timing generation circuit 1 and the received data, and the conversion circuit 43 reads the delay amount corresponding to this phase difference D.
Then, the selector 42 selects one of the received data from the shift register 41, which has this delay amount.
Other configurations and operations in this embodiment are the same as those described in the first embodiment, and thus the description thereof will be omitted.

[0096]

[Embodiment 11] In the embodiment 11, the apparatus of the embodiment 1 is operated at 56K.
It shows an example corresponding to a frame having a communication speed of 168 Kbps in a bps network. The frame format in this case is composed of three time slots, and the number of bits in the octet period in each time slot is seven. In this case, the ideal state is that the frame pulse is received at the 7th bit from the rising edge of the octet signal.

FIG. 22 is a block diagram of a data processing device according to the eleventh embodiment. In this case, the reference value A = 7 and the time slot number n = 3 are set. Further, since the maximum phase difference is 20 bits, only 20 flip-flops in the shift register 41 are used. The time slot counter 31 counts i as 95 described above. Further, the conversion circuit 43 applies the table of Table 2 to the input phase difference D.

In the state thus set, the data synchronizing circuit of the eleventh embodiment performs the control as described in the first embodiment. That is, the phase difference calculation circuit 33 calculates the phase difference D between the octet timing signal generated by the octet timing generation circuit 1 and the received data, and the conversion circuit 43 reads the delay amount corresponding to this phase difference D.
Then, the selector 42 selects one of the received data from the shift register 41, which has this delay amount.
Other configurations and operations in this embodiment are the same as those described in the first embodiment, and thus the description thereof will be omitted.

[0099]

[Embodiment 12] Embodiment 12 uses the apparatus of Embodiment 1 at 56K.
It shows an example corresponding to a frame having a communication speed of 112 Kbps in a bps network. The frame format in this case is composed of two time slots, and the number of bits in the octet period in each time slot is 7. In this case, the ideal state is that the frame pulse is received at the 7th bit from the rising edge of the octet signal.

FIG. 23 is a block diagram of a data processing device according to the twelfth embodiment. In this case, the reference value A = 7 and the time slot number n = 2 are set. Since the maximum phase difference is 27 bits, only 27 flip-flops in the shift register 41 are used. The time slot counter 31 counts i as 95 described above. Further, the conversion circuit 43 applies the table of Table 2 to the input phase difference D.

In the state thus set, the data synchronizing circuit of the twelfth embodiment performs the control as described in the first embodiment. That is, the phase difference calculation circuit 33 calculates the phase difference D between the octet timing signal generated by the octet timing generation circuit 1 and the received data, and the conversion circuit 43 reads the delay amount corresponding to this phase difference D.
Then, the selector 42 selects one of the received data from the shift register 41, which has this delay amount.
Other configurations and operations in this embodiment are the same as those described in the first embodiment, and thus the description thereof will be omitted.

[0102]

[Embodiment 13] In the embodiment 13, the apparatus of the embodiment 1 is operated at 56K.
It shows an example corresponding to a frame having a communication speed of 56 Kbps in a bps network. The frame format in this case is composed of one time slot, and the number of bits in the octet period in each time slot is 7. In this case, the ideal state is that the frame pulse is received at the 7th bit from the rising edge of the octet signal.

FIG. 24 is a block diagram of a data processing device according to the thirteenth embodiment. In this case, the reference value A = 7 and the number of time slots n = 1 are set. Further, since the maximum phase difference is 6 bits, only 6 stages of flip-flops in the shift register 41 are used. The time slot counter 31 counts i as 95 described above. Further, the conversion circuit 43 uses the table 2 for the input phase difference D.
Apply the table of.

In the state set in this way, the data synchronizing circuit of the thirteenth embodiment performs the control as described in the first embodiment. That is, the phase difference calculation circuit 33 calculates the phase difference D between the octet timing signal generated by the octet timing generation circuit 1 and the received data, and the conversion circuit 43 reads the delay amount corresponding to this phase difference D.
Then, the selector 42 selects one of the received data from the shift register 41, which has this delay amount.
Other configurations and operations in this embodiment are the same as those described in the first embodiment, and thus the description thereof will be omitted.

[0105]

Second Embodiment FIG. 25 is a block diagram showing the structure of a data processing device according to a second embodiment of the present invention. The function of each circuit constituting this data processing device is the same as that of the first embodiment of the first embodiment shown in FIG. 5 except for the data separation circuit 6a. The second embodiment is different from the first embodiment in the first embodiment in that the frame synchronization detection circuit 2 has
The received data from the octet timing generation circuit 1 is not directly input, but the received data that has passed through the shift register 41 and the selector circuit 42 forming the data delay circuit 4 is input, and the frame output by the frame synchronization detection circuit 2. A feature is that the pulse is also input to the data separation circuit 6a.

That is, in the first embodiment, the data separation circuit 6 must include a frame synchronization detection circuit having the same configuration as the frame synchronization detection circuit 2, and these two circuits detect the frame synchronization pattern and the frame pulse, respectively. Had to output. In the second embodiment,
The present invention has been devised to eliminate the need for the frame synchronization detection circuit in the data separation circuit 6, further reduce the circuit scale, and reduce the processing load.

In FIG. 25, the selector circuit 42 selects the received data with the delay amount of 0 in the initial state (at the time of starting the data reception). As a result, the frame pulse output by the frame synchronization detection circuit 2 indicates the frame synchronization pattern position of the received data frame itself received by the octet timing generation circuit 1, as in the first embodiment. As a result, the phase difference detection circuit composed of the bit counter 31, the time slot counter 32, and the phase difference calculation circuit 33 detects the received data itself received by the octet timing generation circuit 1 as in the first embodiment. The phase difference with respect to the octet timing signal is detected and input to the conversion circuit 43.

The conversion circuit 43 converts the input phase difference into a selection signal indicating a delay amount for absorbing this phase difference. When the selector circuit 42 receives this selection signal, it selects one of the received data from the shift register 41 having the delay amount shown in the selection signal and inputs it to the frame synchronization detection circuit 2 and the data separation circuit 6a. To do. The selected received data is no longer synchronized with the octet timing signal as described above. Then, the frame synchronization detection circuit 2 generates a frame pulse at the reference position of the reception data synchronized with the octet timing signal, like the frame synchronization detection circuit in the data separation circuit 6 of the first embodiment. Like

The data separation circuit 6a receives this frame pulse, identifies the beginning of the frame in accordance with this frame pulse, and determines the bit rate allocation signal (BAS) contained in the 9th to 16th octets of the service channel of the frame. ) Is extracted. Then, every time the rising edge of the octet timing signal is detected,
The received data is distributed to each of the data processing circuits 7, 8 and 9 according to the cycle determined by the bit rate allocation signal (BAS).

When the phase difference calculating circuit 33 once calculates that the phase difference D is 0 or more and then calculates the phase difference D to be 0, the data delay circuit 4 (shift register 41, selector 42). ), It is determined that the synchronization is established, and the value (D> 0) calculated immediately before is locked.

As described above, according to the second embodiment, the frame pulse generated by the frame synchronization detection circuit 2 can be used for frame separation in the data separation circuit 6a. Therefore, the data separation circuit 6a
Does not need to include the frame synchronization detection circuit, and the circuit scale is further reduced than that of the first embodiment. Book second
Other configurations and operations in the embodiment are the same as those in Example 1 of the first embodiment, and therefore description thereof will be omitted.

[0112]

According to the data processing apparatus of the present invention configured as described above, the H.264 / AVC system can be used. When a plurality of types of data to be processed according to a predetermined periodic signal are included in a frame of a predetermined length according to 221 etc., the plurality of types of the periodic signals of the arbitrary phase generated in the receiving terminal are generated. Data synchronization can be performed by a circuit unit common to the above-mentioned plurality of types of data. As a result, the circuit scale of the entire device can be reduced.

[Brief description of drawings]

FIG. 1 is a principle diagram showing the principle of the present invention.

FIG. 2 is a block diagram showing a configuration of a data processing device according to the first embodiment of the present invention.

3 is a configuration diagram of a buffer incorporated in the frame synchronization detection circuit of FIG.

FIG. 4 is a time chart showing the operation of the apparatus of FIG.

5 is a block diagram showing a first embodiment of the data processing apparatus shown in FIG.

6 is a block diagram of a frame handled by the apparatus of FIG.

FIG. 7 is a block diagram showing a second embodiment of the data processing device shown in FIG.

8 is a block diagram of a frame handled by the apparatus of FIG.

9 is a time chart showing the operation of the apparatus of FIG.

FIG. 10 is a block diagram showing a third embodiment of the data processing device of FIG.

11 is a block diagram of a frame handled by the apparatus of FIG.

FIG. 12 is a time chart showing the operation of the apparatus of FIG.

13 is a block diagram showing a fourth embodiment of the data processing device shown in FIG.

14 is a block diagram of a frame handled by the device of FIG.

FIG. 15 is a time chart showing the operation of the apparatus of FIG.

16 is a block diagram showing a fifth embodiment of the data processing apparatus shown in FIG.

FIG. 17 is a block diagram showing a sixth embodiment of the data processing device of FIG.

FIG. 18 is a block diagram showing a seventh embodiment of the data processing device shown in FIG.

FIG. 19 is a block diagram showing an eighth embodiment of the data processing device shown in FIG.

20 is a block diagram showing a ninth embodiment of the data processing device shown in FIG.

FIG. 21 is a block diagram showing a tenth embodiment of the data processing device of FIG.

22 is a block diagram showing an eleventh embodiment of the data processing apparatus of FIG.

FIG. 23 is a block diagram showing a twelfth embodiment of the data processing apparatus of FIG.

FIG. 24 is a block diagram showing a thirteenth embodiment of the data processing device of FIG.

FIG. 25 is a block diagram showing the configuration of a data processing device according to a second embodiment of the present invention.

FIG. 26. 221 is a block diagram of a frame having a communication speed of 64 Kbits in a 64 Kbit network according to the standard 221.

FIG. 27. 221 is a block diagram of a frame with a communication speed of 56 Kbit in a 56 Kbit network according to 221.

FIG. 28. FIG. 22 is a block diagram of a frame with a communication speed of 384 Kbits in the 64 Kbit network according to 221.

FIG. 29 is a block diagram showing the configuration of a conventional data processing device.

[Explanation of symbols]

1-octet timing generator 2 frame sync detection circuit 3 Phase difference detection circuit 4 Data delay circuit 6 Data separation circuit 6a Data separation circuit 7 Audio data processing circuit 8 Image data processing circuit 9 Code data processing circuit 31-bit counter 32 time slot counter 33 Phase difference calculation circuit 41 shift register 42 Selector circuit 43 Conversion circuit

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H04J 3/04 H04J 3/06 H04L 7/00

Claims (5)

(57) [Claims] 1. A data processing apparatus for processing a data frame including a plurality of types of data to be processed by a signal of a predetermined cycle with the signal of the predetermined cycle generated in an arbitrary phase inside the apparatus, wherein the phase of the data frame is A data phase detection circuit for detecting, a phase difference detection circuit for detecting a phase difference between the phase of the data frame detected by the data phase detection circuit and the phase of the signal of the predetermined cycle, and the phase difference detection circuit for detecting the phase difference. A data delay circuit that delays the data frame by the same amount as the phase difference, a data separation circuit that separates the data frame delayed by the data delay circuit for each of the plurality of types of data, and a data separation circuit that separates the data frame. Processing for processing the processed data according to the signal of the predetermined cycle And a road, the phase difference detection circuit, for each cycle of the predetermined cycle of the signal
Counting bit by bit and the phase detection circuit
Outputs the count value when the synchronization signal is received from
Bit counter and the output from this bit counter
The count value is the data for the signal of the predetermined cycle
From the bit counter when the frames are in sync
Calculate the phase difference by subtracting from the reference count value that can be output
And a phase difference calculating circuit for outputting the data. 2. The phase difference detection circuit divides the period of the signal of the predetermined period into the plurality of time slots, counts one bit for each time slot, and outputs the synchronization signal from the data phase detection circuit. And a bit counter that outputs a count value when receiving, and counts the time slot for each cycle of the signal of the predetermined cycle, and outputs a count value when receiving the synchronization signal from the data phase detection circuit. a time slot counter, according to claim 1, characterized in that it consists of a phase difference calculation circuit for calculating a phase difference based on a count value output counted value output from the bit counter from the time slot counter Data processing equipment. 3. The time slot counter is reset at the beginning of each cycle of the signal of the predetermined cycle, the first time slot after reset is counted as 0, and the next time slot is counted as i, Thereafter, the count value is decremented for each time slot, and the phase difference calculation circuit sets the counter value output from the bit counter to Pbitn, the counter value output from the time slot counter to Ptsn, and the signal of the predetermined cycle. When the reference count value that can be output from the bit counter when the data frames are synchronized is A and the number of the time slots is TSn, the phase difference D is expressed by the equation D = (Ptsn- (TSn- 1)
Of i) × 10 + (A-Pbitn), and when the number of bits included in one time slot in one cycle of the data frame is m, the phase difference D 3. The data processing device according to claim 2, wherein the phase difference D is converted into a decimal number by grasping as a m-ary number, and the data frame is delayed by the same amount as the converted number. 4. The data frame is recommended by ITU-TU.
H. 221 is a frame according to 221 and the synchronization signal is
Written to the service channel of this data frame
It is a frame synchronization signal, the data separation circuit recognizes the position of the data frame by the frame synchronization signal, extracts the bit rate allocation signal written in the service channel of the data frame, and according to the bit rate allocation signal The data processing apparatus according to claim 1, wherein the plurality of types of data are separated from the data frame. 5. The data phase detection circuit extracts the frame synchronization signal from the data frame that has passed through the data delay circuit and inputs the synchronization signal to the data separation circuit, and the phase difference calculation means, 5. The data processing apparatus according to claim 4 , wherein when the phase difference is detected once and then the phase difference disappears, the phase difference detected immediately before is held.