JPH10173619A - Load frame generating device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To generate a high load frame for each time-division multiplex line, and to adjust line throughput by constituting an HDLC frame according to preliminarily set frame length, and inserting an idle flag into a frame according to variably set throughput. SOLUTION: Frame length set by a frame length setting register 1 and a timing LT for each line generated by a time-division multiple timing generating part 8 are applied to a frame length counter 5, and an FC data addition timing FDT and a flag pattern addition timing FPT are generated. An FCS data-adding part 6 adds FCS data, and the data are applied to a flag pattern adding part 7, and the flag pattern adding part 7 adds a flag pattern to the data from the FCS data adding part 6, by receiving the flag pattern addition timing FPT from the frame length counter 5. Then, the data outputted from the flag pattern adding part 7 are time-division multiplexed by a time-division multiplexing part 9.

Description

DETAILED DESCRIPTION OF THE INVENTION

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a load frame generator, and more particularly to an HDLC (High-level Data Link & Control).
ol procedures: high-level data link control procedure) The present invention relates to a load frame generator connected to a frame processing apparatus accommodating an interface in which frames are time-division multiplexed and performing a high load test on the frame processing apparatus.

FIG. 14 shows a plurality of frame processing devices connected to a network.
01 is connected to the n subscriber terminals 103 via the time division multiplexing device 102, and the HDLC frame from the terminal 103 is time division multiplexed by the time division multiplexing device 102 and sent to the frame processing device 102. Frame processing device 1
02 to the network.

In such a frame processing apparatus,
As the number of accommodated subscriber lines increases, the multiplexing of subscriber line frames progresses, and a higher frame transfer capability is required.

For this reason, one frame processing apparatus 101
In order to test / evaluate the frame transfer capability, a load frame generator 100 that generates a load frame is required as a pseudo terminal connection device.

[0004]

2. Description of the Related Art FIG. 15 shows a conventional example of the above load frame generator 100. In this load frame generator 100, a terminal 103 is connected via a time division multiplexer 102 as shown in FIG. Pseudo terminal 100a, an HDLC termination unit 100b for extracting user data from data output from each pseudo terminal 100a, and an HDL
A frame storage unit 100c for temporarily storing the HDLC frame output from the C terminal unit 100b, and a time-division multiplex processing unit for time-division multiplexing the HDLC frame from the frame storage unit 100c as a load frame and providing the load frame to the frame device under test 101 100d.

[0005]

However, in such a conventional example, the end of the frame, accumulation, and time division multiplexing are involved, so that the throughput is reduced by the load frame generator 100.
In addition, since a plurality of lines are processed by a common resource, the line throughput affects each other and the throughput of other lines.

Therefore, since it is impossible to generate a high load frame and to adjust the line throughput, there has been a problem that the accuracy of the frame transfer capability evaluation of the frame processing apparatus is not improved.

Accordingly, the present invention provides a load frame generator connected to a frame processing device accommodating an interface in which HDLC frames are time-division multiplexed and performing a high load test on the frame processing device. It is an object of the present invention to make it possible to generate a high-load frame and to adjust the line throughput in order to improve the accuracy of data transmission.

[0008]

[Means for Solving the Problems]

[1] In order to achieve the above object, the load frame generator according to the present invention synchronizes the user data of each line with each line timing with a frame length setting unit that presets the frame length for each line. A user data generator for converting and sending serial data, an FCS data generator for converting and sending FCS data for performing a frame check sequence of each line to serial data in synchronization with each line timing, and a flag for each line A flag pattern generation unit that converts and transmits a pattern into serial data in synchronization with each line timing, compares the frame length with a value obtained by counting each line timing, and adds the FCS data addition timing and the flag pattern addition timing And a FC for the user data.
An FCS data adding unit that adds the FCS data at the timing of adding the S data; a flag pattern adding unit that adds the flag pattern to the data output from the FCS data adding timing at the timing of adding the flag pattern; A time-division multiplexing timing generator for generating a line timing, which is a time-division multiplexing timing of each line, based on a clock; And a multiplexing unit.

That is, in the present invention, a frame length is set in advance by a frame length setting unit provided for each line.

The user data generation unit and the FCS
(Frame Check Sequence) The serial user data and FCS data respectively generated by the data generation unit are provided to the FCS data addition unit.

The frame length set by the frame length setting unit and the timing for each line generated by the time division multiplex timing generation unit are given to a frame length counter, and the FCS
Data addition timing and flag pattern addition timing are generated.

The FCS data adding unit adds FCS data to user data at the timing of adding FCS data. The data output from the FCS data adding unit is provided to the flag pattern adding unit together with the flag pattern from the flag pattern generating unit. The flag pattern addition unit receives the flag pattern addition timing from the frame length counter and adds the flag pattern to the data from the FCS data addition unit.

Such an operation is performed for each line, and the data output from the flag pattern adding unit for each line is time-division multiplexed by the time division multiplexing unit and sent to the frame processing apparatus under test.

Therefore, it is possible to transmit an HDLC frame having an arbitrary byte length for each line without a break.

[2] According to the present invention, in the above-mentioned present invention [1], a throughput setting unit in which the throughput of each line is set in advance, a value set in the throughput setting unit, the flag pattern addition timing, An idle flag insertion timing generation unit for generating an idle flag insertion timing based on the timing, and inserting the flag pattern into the data output from the flag pattern adding unit at the idle flag insertion timing to perform the time division And an idle flag insertion unit provided to the multiplexing unit.

That is, in the present invention, in addition to the configuration of the present invention [1], the throughput of each line is set in advance by the throughput setting unit. Then, based on the set throughput, each line timing, and the flag pattern addition timing from the frame length counter, the idle flag insertion timing generation unit generates an idle flag insertion timing and provides the idle flag insertion timing to the idle flag insertion unit.

The idle flag insertion unit inserts a flag pattern from the flag pattern generation unit as an idle flag into the data output from the flag pattern addition unit based on the idle flag insertion timing.

Therefore, H of an arbitrary frame length is provided for each line.
DLC frames can be transmitted at an arbitrary transmission interval.

[3] According to the present invention, in the above-mentioned present invention [2], a throughput variation cycle setting unit for presetting a variation cycle of the throughput of each line, and a value set in the throughput variation cycle setting unit and A throughput variation timing generation unit that generates the throughput variation timing based on the line timing, a throughput variation unit that varies the throughput based on the throughput variation timing and the flag pattern addition timing, and a throughput mode of each line. A throughput mode instructing unit to perform the idle flag insertion timing generation by selecting a value set in the throughput setting unit or a value output from the throughput changing unit based on a mode set in the throughput mode instructing unit. And a throughput selector It is characterized in that was.

That is, in the present invention, in addition to the configuration of the present invention [2], the throughput variation cycle setting unit sets the variation cycle of the throughput of each line in advance.

The throughput variation timing generator generates a throughput variation timing based on the set throughput variation cycle and each line timing, and supplies the timing to the throughput variation counter.

The throughput variation counter outputs a value obtained by varying the throughput based on the throughput variation timing and the flag pattern addition timing, and supplies the value to the throughput selector.

The throughput selection unit selects the throughput set in the throughput setting unit or the throughput output from the throughput variation counter based on the instruction from the throughput mode instruction unit, and gives the selected throughput to the idle flag insertion timing generation unit. I have to.

Thus, it is possible to change the throughput at a cycle of the throughput variation set for each line, that is, at an arbitrary cycle for each line.

[4] According to the present invention, in the above-mentioned present invention [3], the throughput variation timing output from the throughput variation timing generator instead of or in addition to the throughput variation unit is provided. It is characterized in that a throughput pattern generation unit that generates a throughput variation pattern based on the flag pattern addition timing and the flag pattern addition timing is used.

That is, in the present invention, a throughput pattern generating unit is provided instead of or in addition to the throughput changing unit in the present invention [3]. Then, a desired throughput variation pattern is extracted by the throughput pattern generation unit based on the throughput variation timing from the throughput variation timing generation unit and the flag pattern addition timing, and is provided to the throughput selection unit.

Thus, each throughput value is varied according to the pattern set in each throughput variation unit at the cycle set in the throughput variation cycle setting unit provided for each line. Therefore, it is possible to vary the frequency at an arbitrary cycle and an arbitrary throughput pattern for each line.

[5] In the present invention, in the above-mentioned present invention [3] or [4], a congestion state signal or a non-congestion state signal is received from the opposed frame processing apparatus, and the congestion state is determined by the flag pattern addition timing. A throughput variation control unit for lowering the throughput when the state signal is valid, increasing the throughput when the congestion-free state signal is valid, and maintaining the throughput of the previous state when both are invalid; It is characterized in that a value output from the fluctuation control unit is given to the throughput selection unit.

That is, in the present invention, in addition to the present invention [3] or [4], a throughput variation control unit is provided, and a congestion state signal or a non-congestion state signal from the opposed frame processing apparatus is added to the flag pattern. Each throughput value is taken in at a timing, and each throughput value is lowered, raised, and held by a congestion state signal and a congestion-free state signal for each line.

Accordingly, it is possible to automatically adjust the limit throughput value for each line in the opposite frame processing apparatus.

[6] In the present invention, the above-mentioned present invention [2]-
[5] In any one of [5], a register for setting a unit time of the frame number count, a unit time counter for counting the unit time of the frame number count by the highway clock, the flag pattern addition timing and the idle pattern insertion timing The counter counts the sum of the flag pattern addition timings when the idle flag insertion timing for each line is invalid, and holds the frame number counter reset for each unit time and the total number of frames at that time for each unit time. A latch register;
And a display unit for displaying the sum.

That is, in the present invention, in addition to the above-mentioned present inventions [1] to [5], the frame number counter sets the above-mentioned flag pattern addition timing while not receiving the above-mentioned idle flag insertion timing for each line. The count is performed per unit time, and the count value is displayed on the display unit.

Thus, the load applied to the frame processing device can be displayed as the total number of frames of each line per unit time.

[7] In the present invention, the above-mentioned present invention [1]-
[6] In any one of [6], a means for acquiring information of a load frame sent from the own device to the frame processing device,
Means for acquiring processing capability information of the frame processing device;
Based on such information, the processing capability of the frame processing device is determined, and the own device is instructed to increase the load when the processing capability has a margin, and the load is maintained as it is in a saturated state. , And means for instructing to reduce the load when the processing capacity is insufficient.

That is, according to the present invention, the load frame generator of the present invention [1] to [6] is connected to a load frame controller. The load frame controller is
The load frame information from the load frame generation device to the frame processing device and the processing capability information of the frame processing device are acquired, and the margin of the processing in the frame processing device is determined based on the information.

As described above, since the frame processing capability information of the opposing frame processing device is monitored and feedback is applied to the load frame generating device based on the information, the limit of the frame processing capability of the frame processing device is found. , It is possible to apply a limit load.

[0037]

FIG. 1 shows the configuration of an embodiment of a load frame generating apparatus according to the present invention [1]. As shown in FIG. Are provided with frame generation units FG (# 0 to # 59), and output data of these frame generation units FG (# 0 to # 59) are time-division multiplexed by the time-division multiplexing unit 9 and are subjected to a frame processing apparatus under test (FIG. (Not shown).

Each of the frame generation units FG (# 0 to # 59) has a register 1 as a frame length setting unit in which a frame length is set in advance for each line, and serial data by synchronizing user data with each line timing. User data generating unit 2 for performing P / S conversion and transmission, and FCS data generation unit 3 for performing P / S conversion and transmission of FCS data for performing a frame check sequence of each line into serial data in synchronization with each line timing A flag pattern generation unit 4 for synchronizing the flag pattern of each line with each line timing LT to perform P / S conversion and transmission to serial data, the frame length data and each line timing LT
And a frame length counter 5 that compares the value counted by the counter 5a with the value counted by the counter 5a to generate the FCS data addition timing FDT and the flag pattern addition timing FPT, and the FCS data at the FCS data addition timing FDT for the user data. And a flag for outputting to the time-division multiplexing unit 9 data obtained by adding the flag pattern to the data output from the FCS data adding unit 6 at the flag pattern addition timing FPT. And a selector 7 as a pattern adding unit.

The generators 2 to 4 and the counter 5
And a line timing LT (# 0 to # 59) which is a time division multiplex timing of each line given to the time division multiplexing unit 9.
Is generated by the time-division multiplex timing generator 8 based on the highway clock, as shown in FIG.

In this embodiment, the time division multiplexing interface of the HDLC frame in the time division
16 shows a load frame generator in the case where 16 bits per μs × 60 lines are multiplexed and the frame length setting value is 1 to 256 words.

Further, the frame length setting register 1 stores 8
The range of 1 to 256 words can be set, and the user data, FCS data, and flag pattern are configured by 16 bits, which is a multiplexing unit. The time division multiplex timing generator 8 includes a 10-bit counter 8a 8k clocks / 8
An M clock is input and multiplex timing for the multiplex interface is generated.

The frame length counter 5 is composed of an 8-bit counter, and counts up to the value set in the frame length setting register 1 so as to obtain the FCS data addition timing FDT and the flag pattern addition timing FP.
T is generated.

Each of the FCS data adding section 6 and the flag pattern adding section 7 is composed of a 2-1 selector.
S data and a flab pattern are inserted, and the time division multiplexing unit 9 is constituted by a 60-1 selector and each line timing L
Based on T (# 0 to # 59), 60 lines are multiplexed.

FIG. 2 is an operation time chart of the embodiment of the present invention, in which a load frame generator is used when the time division multiplexing interface is 16 bits × 125 lines multiplexing per 125 μs and the frame length setting value is 1 to 256 words. The operation of FIG.

The operation of the embodiment shown in FIG. 1 will be described below with reference to the time chart shown in FIG. First, the serial user data and the FCS data generated by the user data generation unit 2 and the FCS data
This is given to the S data adding unit 6.

The frame length set by the frame length setting register 1 and the timing LT for each line generated by the time division multiplex timing generator 8 are stored in the frame length counter 5.
And an FCS data addition timing FDT and a flag pattern addition timing FPT are generated.

The FCS data adding section 6 adds FCS data to user data at the FCS data addition timing FDT. The data output from the FCS data addition unit 6 is provided to the flag pattern addition unit 7 together with the flag pattern from the flag pattern generation unit 4. The flag pattern adding unit 7 receives the flag pattern adding timing FPT from the frame length counter 5 and adds a flag pattern to the data from the FCS data adding unit 6.

The above operation is performed for each line, and the data output from the flag pattern adding unit 7 for each line is time-division multiplexed by the time division multiplexing unit 9 to produce an L-word HDLC frame. Sent to

Therefore, it is possible to transmit the HDLC frame shown as the frame connection image in FIG. 2 without a break.

FIG. 3 is a diagram showing the configuration of an embodiment of the load frame generator according to the present invention [2]. In this embodiment, the settable value of the throughput is 1/16 to 16/16. .

In the figure, a throughput setting register 20 as a throughput setting unit is composed of a 4-bit register, and can set a throughput in a range of 1/16 to 16/16. Idle flag insertion timing generator 21
Is composed of a 4-bit counter 11a and a comparator 11b. The counter 11a counts from 1 to 16 based on the flag pattern addition timing FPT from the frame length counter 5, and the comparator 11b
At T, the count value is stored in the throughput setting register 20.
Is generated, the idle flag insertion timing IFT is generated and given to the idle flag insertion unit 22.

The idle flag insertion section 22 is composed of a 2-1 selector and has an idle flag insertion timing IFT.
And inserts the flag pattern from the flag pattern generator 4 as an idle flag, and is provided for 60 lines.

The register 20 and the timing generator 2
1 and the idle flag setting unit IFS1 (# 0 to # 0) of each line.
# 59). Other configurations are the same as those of the embodiment of FIG.

FIG. 4 is an operation time chart of the embodiment shown in FIG. 3. The data (L word frame) from the flag pattern adding section 7 is transmitted from the idle flag inserting section 22 by the idle flag inserting timing IFT. Is output as

As shown in the frame connection image in this case, the idle flag is inserted according to the set throughput. When the throughput is 1/16, the idle flag is inserted into 15 out of 16 frames, and Is 16/16, there will be no frames with the idle flag inserted.

FIG. 5 is a diagram showing the configuration of an embodiment of a load frame generator according to the present invention [3]. In this embodiment, the throughput variation period is set to 32 m in units of 32 ms.
s to 8 s, and the throughput is repeatedly changed from 1/16 to 16/16.

In the figure, a throughput variation cycle setting register 30 as a throughput variation cycle setting section is constituted by an 8-bit register, and is capable of setting 256 variation cycles. Throughput fluctuation timing generator 31
Is composed of a counter 31a and a comparator 31b, and the counter 31a counts when given a line timing LT. The counter 31a has a 12-bit configuration and compares the count value (upper 8 bits) with the value (8 bits) of the throughput variation period setting register 30 by the comparator 31a.
By comparing with b, the throughput variation timing can be generated in the range of 32 ms to 8 s.

The throughput variation counter 32 as a throughput variation section is composed of a 4-bit logic (AND) gate 32a and a counter 32b, and varies the throughput repeatedly from 1/16 to 16/16 at the flag pattern addition timing FPT. be able to.

The throughput variation instruction register 33 as a throughput variation instruction unit is composed of a 1-bit register, and can set the presence or absence of a throughput variation instruction.
The throughput selection unit 34 is constituted by a 2-1 selector, and selects a value output from the throughput variation counter 32 and outputs the value to the idle flag insertion timing generation unit 21 when there is a throughput variation instruction from the register 33. It is.

The register 30 and the timing generator 3
1, the register 20, the counter 32, the register 33, the selector 34, and the timing generator 21 constitute an idle flag setting unit IFS2 (# 0 to # 59) for each line.
Other configurations are the same as those of the embodiment of FIG.

FIG. 6 shows an operation time chart of the embodiment shown in FIG. 5. In this embodiment, the throughput repeatedly varies from 1/16 to 16/16 as shown in FIG. 7 (1). The case is taken as an example.

That is, the throughput variation counter 32
, The throughput value increases one by one in the 1st to 16th frames, and the throughput value is “1” in the 17th frame as in the first frame.
Will be returned.

FIG. 8 shows the configuration of an embodiment of the load frame generating apparatus according to the present invention [4]. In this embodiment, the throughput is 2 in the range of 1/16 to 16/16.
A throughput pattern within 56 words can be set.

In the figure, a throughput pattern generator 41
Is composed of a logic gate 41a, an address counter 41b, and a throughput setting memory 41c. The address counter 41b is composed of an 8-bit counter,
An address of 56 words is generated, and the memory 41c is a RAM of 4 bits × 256 words.

Now, as shown in FIG. 7 (2), a throughput pattern of 256 words can be set within the range of 1/16 to 16/16, and the memory 41c
Can be output to the throughput selection unit 34. Note that the memory 41c may be a ROM or a dual-port RAM.

The throughput pattern generation unit 4
1, instead of the throughput variation counter 32 in FIG.
Alternatively, it can be additionally provided.

The register 30 and the timing generator 3
1, the register 20, the throughput pattern generator 41, the register 33, the selector 34, and the timing generator 21, the idle flag setting units IFS3 (# 0 to # 5) for each line.
9). Other configurations are the same as those of the embodiment of FIG.

FIG. 9 shows the configuration of an embodiment of the load frame generator according to the present invention [5]. In this embodiment, the throughput is automatically adjusted between 1/16 and 16/16. You are going to.

In the figure, a throughput variation control unit 51 includes a logic gate 51 a and a 4-bit up / down counter 5.
1b, and an opposite frame processing device (not shown)
From 1/16 through the congestion state signal, no congestion state signal, and flag pattern addition timing FPT from
The data is automatically adjusted between 16/16 and output to the throughput selection unit 34.

Note that the throughput mode instruction register 52 in this embodiment comprises a register 20 and a counter 32.
And an instruction to select one of the generation unit 41 and the control unit 51.

The register 30 and the timing generator 3
1, the register 20, the counter 32, the throughput pattern generator 41, the throughput variation controller 51, the register 52, the selector 34, and the timing generator 21 constitute an idle flag setting unit IFS4 (# 0 to # 59) for each line. doing. Other configurations are the same as those of the embodiment of FIG.

FIG. 10 shows an operation time chart of the embodiment of FIG. 9, and the throughput is reduced by 1/16 as in this example.
If the automatic adjustment is performed between 16 and 16/16, the throughput output from the counter 51b of the throughput variation control unit 51 increases when the congestion-free state signal is present,
It is shown to decrease during the congestion state signal.

FIG. 11 shows the configuration of an embodiment of the load frame generating apparatus according to the present invention [6]. In this embodiment, the total number of frames per second is 0 to about 160.
Counting and display are performed within the range of 00 frames.

In the figure, a unit time register 60a is constituted by 3 bits and can set eight kinds of unit times, and a unit time counter 60b is constituted by a 16-bit counter.
The upper 3 bits and the value of the unit time register 60a are compared by the comparator 6
0c is compared, and a unit time timing is generated in the range of 1 to 8 s.

The frame number counter 60f is composed of a 14-bit counter. When the idle flag insertion timing IFT from the idle flag insertion timing generator 21 (# 0 to # 59) of each line is invalid, the frame length counter 1 ( The logical product of the flag pattern addition timings FPT from # 0 to # 59) is respectively AND gated 60d (#
0 to # 59), and the sum of those taken by the OR gate 60e is counted in the range of 0 to about 16,000.

The frame number counter 60f is reset at the unit time timing from the comparator 60c.
The 16-bit latch register 60g is also a comparator 60g.
frame number counter 60 at unit time timing from
The value of f is latched, and the display unit 60h formed of an LED displays the value of the latch register 60g.

FIG. 12 shows the configuration of an embodiment of the load frame generator according to the present invention [7]. In this embodiment, the throughput setting register information of the load frame generator 100 and the frame processor are shown. A limit point of the frame processing apparatus 101 is found out based on the free processing capacity information 101 and the frame discard information, and a load frame control apparatus 110 that generates a limit load is connected to the load frame generation apparatus 100.

The load frame control device 110 has the configuration shown in FIG.
As shown in the operation flowchart of FIG. 3, the value of the throughput setting register 20 in the load frame generator 100 is read (), and the buffer utilization information for each line in the frame processor 101 is stored in the memory 1 by the DMA 110 c.
10 (a), the margin of the frame processing is determined by the microprogram 110b (), and if there is free space in the reception buffer 110a, a value obtained by adding "1" to the value of the throughput setting register 20 is set (). If the reception buffer 110a has no free space (saturated state), nothing is performed (), and if the reception buffer 110a is not enough, the value of the throughput setting register 20 is set to a value obtained by subtracting 1 (). .

[0079]

As described above, according to the load frame generator according to the present invention, an HDLC frame is formed according to a preset frame length, or in addition to this, a preset throughput or variably set. By inserting an idle flag into the frame in accordance with the throughput, or making the throughput variable in accordance with the processing state of the facing frame processing apparatus, a high-load frame can be generated for each time-division multiplexing line. Outbreak,
This has the effect of making it possible to adjust the line throughput, and greatly contributes to improving the performance and accuracy of the load frame generation device and improving the frame transfer capability evaluation accuracy of the frame processing device.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a load frame generator according to the present invention [1].

FIG. 2 is a flowchart showing the operation of an embodiment of the load frame generator according to the present invention [1].

FIG. 3 is a block diagram showing a configuration of an embodiment of a load frame generator according to the present invention [2].

FIG. 4 is a flowchart showing the operation of an embodiment of the load frame generator according to the present invention [2].

FIG. 5 is a block diagram showing a configuration of an embodiment of a load frame generating device according to the present invention [3].

FIG. 6 is a flowchart showing the operation of an embodiment of the load frame generator according to the present invention [3].

FIG. 7 is a diagram illustrating the principle of a load frame generator according to the present inventions [3] and [4].

FIG. 8 is a block diagram showing a configuration of an embodiment of a load frame generator according to the present invention [4].

FIG. 9 is a block diagram showing a configuration of an embodiment of a load frame generator according to the present invention [5].

FIG. 10 is a flowchart showing the operation of an embodiment of the load frame generator according to the present invention [5].

FIG. 11 is a block diagram showing a configuration of an embodiment of a load frame generating device according to the present invention [6].

FIG. 12 is a block diagram showing a configuration of an embodiment of a load frame generating device according to the present invention [7].

FIG. 13 is an operation flowchart of the load frame control device connected to the load frame generation device according to the present invention [7].

FIG. 14 is a block diagram showing a position of a load frame generator according to the present invention and a conventional example in a network.

FIG. 15 is a block diagram showing one embodiment of a load frame generator according to a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Flow chart setting register 2 User data generation part 3 FCS data generation part 4 Flag pattern generation part 5 Frame length counter 6 FCS data addition part 7 Flag pattern addition part 7 8 Time division multiplex timing generation part 9 Time division multiplex part 20 Throughput setting register Reference Signs List 21 idle flag insertion timing generation unit 22 idle flag insertion unit 30 throughput fluctuation cycle setting register 31 throughput fluctuation timing generation unit 32 throughput fluctuation counter 33 throughput mode instruction register 34 throughput selection unit 41 throughput pattern generation unit 51 throughput fluctuation control unit 52 throughput mode Instruction register 60 Frame number counting unit 100 Load frame generator 101 Frame processor 110 Load frame controller LT Line timing FDT FCS data addition timing FPT flag pattern addition timing IFT idle flag insertion timing In the figures, the same symbols indicate the same or corresponding parts.

 ──────────────────────────────────────────────────の Continued on the front page (72) Inventor Mitsunari Takahashi 3-9-18 Shin-Yokohama, Kohoku-ku, Yokohama City, Kanagawa Prefecture Inside Fujitsu Communication Systems Limited

Claims (7)

[Claims] 1. A load frame generator connected to a frame processing device accommodating an interface in which an HDLC frame is time-division multiplexed and performing a high load test on the frame processing device, wherein a frame length is preset for each line. Length setting unit, a user data generation unit that synchronizes the user data of each line with each line timing and converts it to serial data, and an FC for performing a frame check sequence of each line
An FCS data generator for converting and sending S data to serial data in synchronization with each line timing, a flag pattern generator for converting and sending flag patterns of each line to serial data in synchronization with each line timing, A frame length counter for comparing the frame length with a value obtained by counting each line timing to generate FCS data addition timing and flag pattern addition timing; and FCS data for adding the FCS data to the user data at the FCS data addition timing. An adding unit; a flag pattern adding unit for adding the flag pattern to the data output from the FCS data adding unit at the flag pattern adding timing; and a line timing which is a time division multiplex timing of each line based on a highway clock. Time-division multiplexing to generate A timing generator, a load frame generating device by time-division multiplexing frame output from the flag pattern adding unit, characterized by comprising: a division multiplexing unit time to be supplied to the frame processor. 2. A throughput setting unit according to claim 1, wherein an idle flag is inserted based on a value set in said throughput setting unit, an addition timing of said flag pattern, and each line timing. An idle flag insertion timing generation unit for generating timing, and an idle flag insertion unit for inserting the flag pattern at the idle flag insertion timing into the data output from the flag pattern addition unit and giving the flag pattern to the time division multiplexing unit. A load frame generator further provided. 3. A throughput variation period setting unit for presetting a variation period of a throughput of each line, and a throughput variation timing based on a value set in the throughput variation period setting unit and each line timing. A throughput variation timing generation unit that generates the throughput, a throughput variation unit that varies the throughput based on the throughput variation timing and the flag pattern addition timing, a throughput mode instruction unit that sets a throughput mode of each line, A throughput selection unit that selects a value set in the throughput setting unit or a value output from the throughput variation unit based on the mode set in the mode instruction unit and gives the value to the idle flag insertion timing generation unit. Load flexure characterized by Boom generator. 4. The method according to claim 3, wherein the throughput variation timing output from the throughput variation timing generator and the flag pattern addition timing are output in place of or in addition to the throughput variation unit. A load frame generation device characterized by using a throughput pattern generation unit for generating a fluctuation pattern. 5. A congestion state signal or a non-congestion state signal from an opposing frame processing apparatus, and the throughput is reduced when the congestion state signal is valid according to the flag pattern addition timing. A throughput variation control unit that increases the throughput when the congestion-free state signal is valid, and retains the throughput of the previous state when both are invalid, and calculates the value output from the throughput variation control unit A load frame generator provided to a selector. 6. A register according to claim 2, wherein a register for setting a unit time for counting the number of frames is provided.
A unit time counter that counts a unit time of the frame number count by the highway clock; and a flag pattern addition timing when the idle flag insertion timing for each line is invalid by the flag pattern addition timing and the idle pattern insertion timing. A frame number counter that counts the sum and is reset for each unit time, a latch register that holds the sum of the number of frames at that time for each unit time, a display unit that displays the sum,
A load frame generator further comprising a frame number counting section having: 7. A method according to claim 1, further comprising: means for acquiring information of a load frame sent from the self apparatus to the frame processing apparatus; means for acquiring processing capability information of the frame processing apparatus; The processing capability of the frame processing device is determined based on the information of the frame processing device, and the own device is instructed to increase the load when the processing capability has a margin, and the load is maintained as it is in a saturated state. Means for instructing, and instructing to reduce the load when the processing capacity is insufficient, a load frame control device connected to the load frame control device.