KR0174504B1 - Receive data check bit string generator - Google Patents

Abstract

The present invention discloses an apparatus for generating received data check bit strings. The apparatus divides each byte by a generation polynomial of M bits to obtain a first received data check bit string, and includes first division and delay means for delaying and outputting the first received data check bit string for one period, and a first division. And second division and delay means for inputting the output of the delay means and dividing by the generated polynomial to obtain the second received data check bit string, and delaying and outputting the second received data check bit string for one period. Input the output of the means and divide by the generation polynomial to obtain the third, 4 .... or N-1 received data check bit string, and the third, 4 .... or N-1 received data check bit string 1 N-3 division and delay means for delaying the period and outputting to the next division and delay means, and the received data check bits of each byte selectively in response to the selection signal. With heat A received data check bit string selection means for outputting, wherein the selection signal selects the output of the N-th division and delay means when the byte is the most significant (Nth) byte, and any generated polynomial is used. In this system, the received data check bit string can be generated.

Description

Receive data check bit string generator

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error checking and correction (ECC) circuit, and in particular, an apparatus for generating a received data check bit string for generating a received data check bit string so as to check whether there is an error occurring during data transmission. It is about.

In general, Asyncronous Transmission Mode (ATM) transmits data in units of cells, which are 53 bytes, that is, 48 bytes of payload and 5 bytes of headers. Consists of One byte of the five byte header before transmission is made for CRC (cyclic redundancy check).

The conventional receiving data check bit string generating apparatus has a fixed generation polynomial [g (x)], i.e., fixed for a header of 5 bytes minus 48 bytes of valid data described above during transmission and reception.

g (x) = k ³ + k ² + k ¹ +1

Use to generate the received data check bit string. In order to determine whether there is an error of the data, the generated received data check bit string is checked and if it is 0, it is determined that there is no error in the data, otherwise it is determined that an error exists.

However, if the generation polynomial is changed in the future due to changes in the standard recommendation of the ATM system or other special reasons, the conventional received data check bit string generation circuit cannot be used.

SUMMARY OF THE INVENTION An object of the present invention is to provide an apparatus capable of generating a received data check bit string in a system using any generation polynomial in response to a change in the generation polynomial in order to solve the conventional problems as described above.

The present invention for achieving the above object, by inputting the header of the transmitted N (N is a positive integer) byte data in byte units to divide by the generation polynomial of M (M is a positive integer) bits, and divide the remainder A reception data check bit string generating device for outputting the received data check bit string of each byte, wherein each byte is divided by the generation polynomial of the M bits to obtain a first received data check bit string, and the first received data. First dividing and delaying means for delaying and outputting a check bit string for one period; and outputting the output of the first dividing and delaying means to divide by the generated polynomial to obtain a second received data check bit string. Second division and delay means for delaying and outputting the received data check bit string for one period, and dividing by the generation polynomial by inputting the output of the previous division and delay means; By obtaining the third, fourth ... or N-1 received data check bit string, and delays the third, fourth .... or N-1 received data check bit string for the one period N-3 division and delay means for outputting to the next division and delay means, and the outputs of the input N-1 division and delay means are selectively output as the received data check bit string of each byte in response to a selection signal. And receiving data check bit string selection means, and when said byte is the most significant (Nth) byte, it is preferable to select the output of said N-1 division and delay means.

1 is a block diagram of a reception data check bit string generating apparatus according to the present invention.

2 is a circuit diagram according to the present invention of each division and delay unit shown in FIG.

3 is a block diagram of a reception data check bit string selection unit shown in FIG.

4 is a circuit diagram according to the present invention of the received data check bit string selector shown in FIG.

5A to 7F are input / output timing diagrams of each division and delay unit shown in FIG.

Hereinafter, a configuration and an operation of a reception data check bit string generation apparatus according to the present invention will be described in detail with reference to the accompanying drawings.

For better understanding of the present invention, it is assumed that the generated polynomial is 9 bits and the header consists of 5 bytes.

1 is a block diagram of a reception data check bit string generating apparatus according to the present invention, and includes eight J / K flip-flops 10, 12, 14, 16, 18, 20, 22, and 24; 3 and 4 division and delay units 26, 28, 30, and 32, and a received data check bit string selector 34.

The flip-flops 10, 12, 14, 16, 18, 20, 22, and 24 shown in FIG. 1 input a 5-byte header byte by byte through the input terminal IN1. Input and buffer the least significant bit of each byte in order from the first flip-flop 10 to the eighth flip-flop 24, and output each buffered bit to the data bus in the same order.

The first division and delay unit 26 inputs each byte of the header to the terminal E through the data bus, divides the generated 9-bit polynomials into the terminal B through the input terminal IN2, and divides the remainder by the first division. Get the received data check bit string. Thereafter, the first received data check bit string is delayed for one period (T) and outputted through the terminal Q. Terminal A of each division and delay unit shown in FIG. 1 inputs a clock (CLK), C inputs an enable signal (EN), and a reset signal is input through D. do.

The second divider and delay unit 28 inputs the first received data check bit string output from the first divider and delay unit 26 to divide by the generated polynomial, and divides the remaining divided second received data check bit string. After obtaining, the second received data check bit string is delayed for one period (T) and output.

The third divider and delay unit 30 inputs the output from the second divider and delay unit 28 to divide by the generated polynomial, obtains the third received data check bit string that is the remainder, and then receives the third received data. The check bit string is delayed for one period (T) and output.

The fourth divider and delay unit 32 inputs the output from the third divider and delay unit 30 to divide by the generated polynomial, obtains the fourth received data check bit string that is the remainder, and then receives the fourth received data. The check bit string is delayed for one period (T) and output. The eight bits output from the flip-flop through the data bus are the fifth received data check bit strings.

FIG. 2 is a circuit diagram according to the present invention of each division and delay unit shown in FIG. 1, and is composed of a plurality of flip-flops and gates.

The division and delay unit shown in Article 2 inputs each byte of the header through the input terminal IN3, inputs a generation polynomial through the IN4, and outputs the delayed received data check bit string through the output terminal OUT2.

On the other hand, the received data check bit string selector 34 shown in FIG. 1 includes the first, second, and fourth outputs from the first, second, third, and fourth division and delay units 26, 28, 30, and 32. The 3, and 4 received data check bit strings are input, and the received 8 bit received data check bit strings are selectively output through the output terminal OUT1 in response to the selection signal SC.

FIG. 3 is a block diagram of the received data check bit string selector 34 shown in FIG. 1, and receives an 8-bit first received data check bit string through the input terminal IN5 and a second 8-bit received bit through IN6. Input the data check bit string, the 8-bit third received data check bit string through IN7, the 8-bit fourth received data check bit string through IN8, and the fifth received data check bit string through IN9, respectively. It selectively outputs in response to the selection signal SC.

FIG. 4 is a circuit diagram according to the present invention of the received data check bit string selector 34 shown in FIG. 3, and is composed of a plurality of gates.

Here, the reception data check bit strings output from each division and delay unit will be described as follows.

If the result of the received data check bit string, which is the remainder of the 5-byte header divided by the 9-bit generator polynomial, is '00000000', then there is no error in the data, otherwise an error exists. That is, the received data check bit string is expressed as in Equation (1) below.

Where v (x) indicates a 40-bit reception header, c (x) indicates a 40-bit transmission header, e (x) indicates a 40-bit transmission error, and c (x) indicates a transmission error. Is divided by g (x). That is, c (x) = a (x) g (x). As a result, the received data check bit string is the remainder of dividing e (x) by the generated polynomial g (x). At this time, the division for 40 bits of e (x) is converted into 8-bit calculations as shown in Equation (2).

Here, e1, e2, e3, e4, and e5 are eight bits, respectively, and '0' in [] represents eight '0' bits. That is, e1 represents S1 (t), e2 represents S2 (t), e3 represents S3 (t), e4 represents S4 (t), and e5 represents S5 (t).

Each division and delay unit shown in FIG. 1 has one period of receiving data check bit string Sn (t) at S4 (x) = S4 (t + T) = R _{g (x)} [S4 (t) X ⁸ ]. Delay to output the received data check bit string Sn (t + T). Therefore, S4 (t + T), which is the first received data check bit string, is output through the first division and delay unit 26, and S3 (t + 2T), which is the second received data check bit string, is obtained by the second division and S2 (t + 3T), which is output through the delay unit 28, and the third received data check bit string, is output through the third division and delay unit 30, and S1 (t, which is the fourth received data check bit string. + 4T) is output through the fourth division and delay unit 32.

5A-7F are input / output timing diagrams of each division and delay unit shown in FIG. 1, and FIGS. 5A, 6A, and 7A show clocks, 5B, 6B, and 7B show reset signals, and 5C, 6C, and 7C show The Able signal, the 5D, 6D, and 7D diagrams represent a signal input through the terminal E, the 5E, 6E, and 7E diagrams represent a generation polynomial, and the 5F, 6F, and 7F diagrams represent signals output through the terminal Q, respectively.

As described above, since the reception data check bit string generation circuit according to the present invention can generate the reception data check bit string by inputting the generation polynomial to an arbitrary value, unlike the conventional circuit fixed to a specific generation polynomial. The effect is that it can be used in any system that uses any generated polynomial.

Claims (1)

Input the header of N (N is a positive integer) byte data to be transmitted in byte units to divide M (M is a positive integer) bit into a polynomial, and divide the remainder into the received data check bit string of each byte. A receiving data check bit string generating apparatus, comprising: dividing each byte by the generation polynomial of the M bits to obtain a first receiving data check bit string, and outputting the first received data check bit string by delaying the first receiving data check bit string for one period. Inputting the first division and delay means and the output of the first division and delay means to divide by the generation polynomial to obtain a second received data check bit string, and delaying the second received data check bit string for one period. The second division and delay means for outputting and the output of the previous division and delay means to divide by the generated polynomial to generate the third, fourth, ..., or N-1 received data. N-3 division and delay means for obtaining a check bit string and delaying the third, fourth ..... or N-1 received data check bit string for one period and outputting the result to the next division and delay means. And receiving data check bit string selection means for selectively outputting the inputted outputs of the N-1 division and delay means as received data check bit strings of the respective bytes in response to a selection signal. And an output of the N-1 division and delay means when the byte is the most significant (Nth) byte.