JPS6273826A - Frame transmission and reception system - Google Patents

Abstract

PURPOSE:To improve the transmission error detection rate to a long packet and to improve the transmission efficiency to a short packet by transmitting and receiving a frame added with a CRC code having a length in matching with the packet length. CONSTITUTION:When a CRC generating circuit 14 receives transmission information outputted serially from a shift register 12, the circuit 14 generates a CRC code of the 1st length corresponding to the said information. On the other hand, a CRC generation circuit 15 generates a CRC code of the 2nd length shorter than the 1st length corresponding to the transmission information consituting a short packet. CRC calculation/check circuits 25, 26 receive a serial output data from the shift register 12 to calculate the CRC with different length and the result is compared with the received CRC to apply CRC check.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a frame transmission and reception method for transmitting and receiving variable length frames including CRC codes.

[Technical background of the invention and its problems 1 Generally, the length of a CRC code applied to data transmission using variable length frames is predetermined by the system and is a fixed length.

Now, the longer the length of the CRC code, the higher the detection rate of transmission errors can be.

On the other hand, when the length of the CRC code is increased, the transmission efficiency decreases.

However, in the past, a fixed-length CRC code was applied regardless of the packet length (frame length), so it was not possible to obtain a sufficient transmission error detection rate for long packets, and the transmission efficiency decreased for short packets. There was a problem.

[Purpose of the Invention] This invention was made in consideration of the above circumstances, and its purpose is to be able to transmit and receive frames to which a CRC code of a length commensurate with the packet length is added, and to detect transmission errors for long packets. It is an object of the present invention to provide a frame transmission/reception method that can improve transmission rate and improve transmission efficiency for short packets.

[Summary of the Invention] In this invention, the length of the CRC is determined according to the packet length. :1
A transmitting circuit that transmits a transmitting frame with a code added to it, and a transmitting circuit that receives a transmitting frame transmitted from this transmitting signal circuit and transmits a C.
A receiving circuit for performing an RC check is provided.

The transmission circuit includes transmission information generation means for generating transmission information that includes transmission user data and is subject to CRC addition;
A plurality of types of CRC generation means are provided. The CRC generation means is provided for each type of bucket 1, and receives the transmission information generated by the transmission information generation means and generates a CRC code having a length corresponding to a predetermined type of bucket 1. The transmission circuit further includes a first packet type determination means for determining the packet type based on at least the user data length of the transmission information, and a first packet type determination means for selecting one of the plurality of types of CRC generation means according to the determination result of the determination means. A transmission frame generating means is provided. This transmission frame generation means uses the CRC selected by the first selection means.
A transmission frame including the CRC code generated by the generation means and the above transmission information is generated.

On the other hand, the reception circuit includes a plurality of types of CRC total 1/check means, and a second packet type determination means that receives a transmission frame transmitted from the transmission circuit, counts the length of the frame, and determines the packet type. , a second selection means is provided for selecting one of the plurality of types of CRC calculation/checking means according to the determination result of the determination means. CRCi! The tII/check means is provided for each type of bucket, and receives the transmission frame and calculates a CRC code with a length corresponding to a predetermined packet type based on the transmission information in the frame. CRC check is performed using the CRC code.

[Embodiments of the invention] An embodiment of the present invention is shown in FIG. 1(a) below.

The explanation will be explained with reference to the block configuration diagram in (b) and the format diagram in FIG.

FIG. 1(a) shows the configuration of the transmitting circuit, in which 10 is a buffer memory for storing user data, 11 is a header (frame header) consisting of address A and control information C)
This is the header component that makes up the . Now, as shown in the format of FIG. 2, the frame applied in this embodiment has fields of flag F, address A, control information C1 data (user data) D, and CRC code.

The header configuration section 11 is connected to a shift register 12 as well as a buffer memory 10 . The frame I\tsuda(A+C) formed by the header configuration section 11 is input in parallel to the shift register 12 in units of predetermined bits (for example, 8 bits) from the beginning thereof, and then serially outputted from the shift register 12.

Next, user data to be transmitted from the buffer memory 10 (
D) is taken out in predetermined bit units and transferred to the shift register 12.
The signal is inputted in parallel to the shift register 12, and outputted serially from the same shift register 12.

Information (A,
The transmission information (consisting of C and D) is sent to a multiplexer (MPX) 13 with two inputs and one output connected to the same register 12.
one input, each human power d3 of CRC generation circuit 14゜15
and the input of the packet length counting circuit 16, respectively.

Good counting circuit 1G to bucket 1 is shift register 12h)
The length of the transmitted information that is serially output is counted.

The counting result of the packet length counting circuit 1G is supplied to a packet type determining circuit 17 connected to the same circuit 16.

The packet type determination circuit 17 includes a packet length counting circuit 16.
Depending on the transmission information length counting result, the packet type (here, long packet, short packet) is determined based on the difference in packet length.
The selection signal 31 (logical ``1'' for long packets, logical ``O'' for short packets) according to the determination result
”). The selection signal 31 output from the packet p4 individual determination circuit 17 is supplied to a multiplexer (MPX>18) connected to the circuit 17.

The CRC generation circuit 14 is configured to generate a CRC code of a first length in response to transmission information that constitutes a packet. That is, when the CRC generation circuit 14 receives the transmission information serially output from the shift register 12,
A CRC code of a first length corresponding to the information is generated. On the other hand, the CRC generation circuit 15 is configured to generate a CRC code of a second length, which is shorter than the CRC code of the first length, corresponding to the transmission information constituting the short packet. That is, upon receiving the transmission information serially output from the shift register 12, the CRC generation circuit 15 generates a CRC code of the second length corresponding to the same information.

The CRC generation operation of the CRC generation circuits 14 and 15 is performed in parallel with the counting operation of the packet length counting circuit 16.

The first length CR generated by the CRC generation circuit 14
The C code is fed to one input of a multiplexer 18 connected to the same circuit 14. Also, CRC generation circuit 1
The second length CRC code generated by 5 is fed to the other input of a multiplexer 18 connected to the same circuit 15. The multiplexer 18 receives the selection signal 3 output from the packet type determination circuit 17 as described above.
1 is also supplied.

The multiplexer 18 selects the selection signal 31 from the logic ti 1
In the case of u, the CRC code of the first length generated and output by the CRC generation circuit 14 is selected, and in the case of logic "0", the CRC code is selected.
Second length generated and output by the C generation circuit 15 7) CR
Select C code. The CRCi number selected by the multiplexer 18 is supplied to the other input of the multiplexer 13 connected to the multiplexer 18.

Now, one input of the multiplexer 13 is supplied with the transmission information (Δ10+D) serially outputted from the shift register 12 as described above. Multiplexer 13
First, under the control of a control section (not shown), the information supplied to one of the above inputs, that is, the transmission information from shift 1 to register 12 is selected. Next, the multiplexer 13 selects the information supplied to the other input, that is, the CRC code selectively output from the multiplexer 18. As a result, from the multiplexer 13, A, C, D, CRC (
Frame configuration information (excluding flag F) is output. The output of the multiplexer 13 is connected to a flag insertion circuit 19 via a zero insertion circuit (not shown). The flag insertion circuit 19 adds a flag F before and after the input information. As a result, a transmission frame having the format shown in FIG. 2 is generated.

Figure 1 (b) shows the configuration of the receiving circuit, and 21 is a shift register. The transmission frame transmitted from the transmitting circuit in Figure 1 (a) is serially input to this shift register 21. A synchronization establishment circuit 22 is connected to the shift register 21.The synchronization establishment circuit 22 detects a flag F in the frame input to the shift register 21, and uses the flag F to establish a synchronization with (the clock of) the receiving circuit. Synchronize.This enables the receiving circuit to perform receiving operations.
The field portion excluding flag F in the received frame is serially output from the shift register 21.

The output of the shift register 21 is connected to the inputs of another shift register 23, a packet length counting circuit 24, and CRC counter II/check circuits 25 and 26 prepared for each packet type. This allows shift register 2
Reception frame serially output from 1 (however, flag F
(not included) are a shift register 23, a packet length counting circuit 24, and a UCRCgt calculation/checking circuit 25.
．． 26.

The packet length counting circuit 24 counts the frame length (packet length) of the received frame serially output from the shift register 21. The counting result of the packet length counting circuit 24 is sent to the packet type determining circuit 2 connected to the same circuit 24.
7. The packet 1Φ classification circuit 27 determines the packet type based on the difference in packet length (in this case, a packet or a short packet) according to the counting result of the packet length counting circuit 24, and selects fg @ according to the determination result.
4' ((logic II i I+ for long packets, logic "'O" for short packets). The selection signal 41 output from the packet type determination circuit 27 is output from the multiplexer connected to the circuit 27. (MPX) 28.

The CRC calculation/check circuit 25 calculates a CRC code of a first length corresponding to the transmission information constituting the long packet, and performs a CRC check (error detection) using the calculation result and the CRC code added to the transmission information. ). On the other hand, the CRC meter II/check circuit 26 calculates a CRC code of a second length corresponding to the transmission information constituting the short packet, and performs a CRC check using the calculation result and the CRC code added to the transmission information. (error detection). That is, the CRC counting/checking circuits 25 and 26 receive the serial output data from the shift register 12 and perform 31 calculations of CRCs of different lengths at ['j], and compare them with the received CRC to determine the CRC.
A check is made. CRC calculation/check circuit 25
．． The CRC counter II/check operation of No. 26 is performed in parallel with the counting operation of the packet/length counting circuit 24.

The CRC check result of the CRC meter II/check circuit 25 is supplied to one input of the multiplexer 2B connected to the same circuit 25. The CRC check link of the CRC sieve/check circuit 26 is also supplied to the other input of a multiplexer 28 connected to the same circuit 2e.

The multiplexer 28 is also supplied with the selection signal 41 output from the packet type determination circuit 27 as described above. The multiplexer 28 has a selection signal 41 of logic "1".
”, the CRC check result of the CRC calculation/check circuit 25 is selected, and when the logic is “0”, the CRC calculation/check result is selected.
'Select the CRC check result of the check circuit 26.

The CRC check result selected by the multiplexer 28 is held in a status register 29 connected to the multiplexer 28.

On the other hand, in the shift register 23, a serial/parallel conversion operation is performed in parallel with the above operation 2, and the transmission information portion is outputted in parallel. The output information from the shift register 23 is sent to the reception buffer 3 connected to the same register 23.
Stored at 0.

Next, another embodiment of the present invention will be described with reference to FIG. FIG. 3 shows the configuration of the signal transmission circuit, and the same parts as in FIG. 1(a) are given the same reference numerals. In FIG. 3, 51 is a buffer management unit that manages the backup memory 10. The buffer management unit 51 has a well-known buffer management function for managing the data length, address, etc. of the user data stored in the buffer memory 10. The buffer management unit 51 includes a packet type determination circuit 52 that determines the packet type (here, long packet, short packet) based on the difference in packet length of the packet containing user data to be transmitted (transmission packet). .

The packet type determination circuit 52 determines the packet type based on the user data length by using the user data length management function of the buffer management unit 51. The packet type determination circuit 52 uses a bucket as shown in FIG.
Output.

That is, in this embodiment, by utilizing the user data length management function of the buffer management section 51, the packet length counting circuit 1G shown in FIG. 1(a) is made unnecessary. In this case, the selection signal 31 output from the packet type determination circuit 52 may enable one of the CRC generation circuits 14 and 15 to be in an operable state. This also eliminates the need for multiplexer 18.

In the above embodiment, the case where there are two types of packets, one long bucket and one short packet, has been described, but the present invention can also be applied to a case where there are three or more types.

[Effects of the Invention] As detailed above, according to the present invention, it is possible to transmit and receive frames to which a CRC code of a length commensurate with the packet length is added, thereby reducing the transmission error detection rate for long packets. It is possible to improve the transmission efficiency for short packets.

[Brief explanation of drawings]

FIG. 1 is a block configuration diagram showing one embodiment of this invention, FIG. 2 is a diagram showing a frame format applied in the same embodiment, and FIG. 3 is a block diagram showing another embodiment of this invention. It is. 13, 18.28...Multiplexer (MPX), 1
4゜15...CRC generation circuit, 1f3.24...Packet length counting circuit, 17.27.52...Packet type determination circuit, 25.26...CRC calculation/check circuit, 31.41. ...Selection signal. Applicant's agent Patent attorney Takehiko Suzue <a> (b) Figure 1

Claims (1)

[Claims] Transmission information generation means for generating transmission information that includes transmission user data and is subject to CRC addition; transmission information that is provided for each packet type based on a difference in packet length, and that is generated by the transmission information generation means; A plurality of types of C
RC generating means, first packet type determining means for determining the packet type based on at least the user data length of the transmission information, and selecting one of the plurality of types of CRC generating means according to the determination result of the first packet type determining means. and a transmission frame generation means for generating a transmission frame containing the transmission information and a CRC code generated by the CRC generation means selected by the first selection means, and a transmission circuit for each packet type. is provided in the transmission frame transmitted from the transmission circuit, calculates a CRC code with a length corresponding to a predetermined packet type based on the transmission information in the frame, and calculates the CRC code in the frame based on the transmission information in the frame.
Multiple types of CR that perform CRC check using RC code
C calculation/checking means, second packet type determining means for receiving a transmission frame transmitted from the transmitting circuit and counting the length of the frame to determine the packet type; and a determination result of the second packet type determining means. a receiving circuit comprising a second selection means for selecting one of the plurality of types of CRC calculation/checking means according to the packet length; A frame transmission/reception method characterized by the following: