JP2655489B2 - ATM cell signal format converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an ATM (Asynchronous T).
ransfer Mode) Regarding the cell signal format converter,
In particular, an SDH (Synchronous Digital Hierarchy) in which a stuff absorption area for absorbing transmission line fluctuation is set in advance.
ATM in ATM communication system using format
The present invention relates to a cell signal format converter.

[0002]

2. Description of the Related Art In ATM communication, a plurality of continuous input ATM cell signal formats to be transmitted to a transmission line are provided only in a payload portion of an SDH format.
It is necessary to convert the data into the SDH format in which the cell is inserted and send it out on the transmission path.
An ATM cell signal format converter for converting to the DH format is used.

The internal signal format of the input ATM cell signal has a structure as shown in FIG. That is, as shown in (A), the cell signal in the apparatus is composed of 54 bytes, and one cell is constituted by adding one redundant byte to the head of 53 bytes of valid data.

[0004] As shown in FIG.
720 cells are continuously arranged in a section of 5 μsec (8 KHz). In this case, there are 706 valid cells,
The number of redundant cells is 14, and the cell arrangement is such that 52 cells constitute one cell group and a redundant cell 1 is placed at the head of these cell groups.
Are arranged, and thereafter 51 effective cells are arranged successively. 13 cell groups are arranged,
The last 14 groups have 43 effective cells. The ATM cell signal format shown in FIG.
It exists repeatedly in Z cycles.

In order to transmit a device cell signal having such a format onto a transmission line, it is recommended that the ITU recommendation, G.A. 709
It is necessary to convert the data into the SDH format conforming to the standard and transmit it. In this SDH format, FIG.
As shown in the figure, each cell has a configuration of 53 bytes, and redundant signals are not included and all are valid signals.

The cell signal is accommodated in the SDH format. An example of the format is shown in FIG.
The STM (Synchronous Transfer Mode)
) 16 frame format. That is, one frame is composed of 9 rows, each of which has 4320 bytes, and has a capacity of 4320 bytes × 9 rows = 38880 bytes. However, the actual cell signal can be arranged only in the payload portion, and the payload portion is 4160 bytes per row. That is, 4160 bytes × 9 rows = 37440 bytes.

[0007] The remaining 1440 bytes are a section / path overhead (SOH / POH or SPOH) portion, and the first 160 bytes of each row are assigned this overhead portion.

FIG. 9 is a block diagram of a conventional ATM cell signal format converter.
This is to convert the cell signal having the byte structure into the cell signal having the 53-byte structure of the transmission path shown in FIG.

This apparatus includes a conversion memory 81 for performing format conversion, a write counter 85 for writing a 54-byte cell signal to the conversion memory 81,
A write counter control section 84 for controlling the write counter 85, a read counter 83 for reading a 53-byte cell signal to be transmitted from the conversion memory 81 to the transmission line, and a read counter 83 for controlling the read counter 83. A read counter control unit 82 and a write counter 85
And a phase comparison unit 81 that compares the phases of the read counter 83 and the read counter 83 and notifies the write counter control unit 84 when both phases approach each other.

A specific example of a write / read signal to / from the conversion memory 81 will be described with reference to FIGS. The write data is 706 cells excluding the redundant cells among the 720 cells in an 8 KHz cycle.

On the other hand, the read data is 706.41... Cells in the same 8 KHz cycle. Since a 53-byte cell signal is accommodated in the payload portion (37440 bytes) of FIG. 8B, 37440 bytes ÷ 53 = 706.41... Cells.

As described above, the relationship between the write signal rate to the conversion memory 81 and the read signal rate is such that the write signal rate <the read signal rate. And finally an error occurs in the read data.

Therefore, a phase comparator 86 is provided to compare the write phase and the read phase to control the write phase.

[0014]

As described above, the conventional AT
In the M-cell format converter, it is necessary to always compare the write phase with the read phase and control the write phase so that no underflow occurs in the conversion memory. A circuit for controlling the write phase must be provided in the control section 84, and there is a disadvantage that the circuit scale is increased.

The write counter 85, which is controlled by the write counter control unit 84 which has received the underflow notification from the phase comparison unit 86, generates a cell signal which is not originally written in the memory 81 in the internal format of FIG. Has to be written, and therefore, there is a disadvantage that it is necessary to control to arrange an effective cell signal to be transmitted to the transmission line in a cell signal portion where writing is not performed.

SUMMARY OF THE INVENTION An object of the present invention is to provide an ATM cell format converter having a simple structure which does not need to detect the underflow of the conversion memory and control the write phase.

According to the present invention, the redundant byte is stored in the first byte.
Consecutive multiple unit cells consisting of the specified byte included in the eye
And one redundant cell is provided at the head of
This cell group was further arranged continuously as one cell group
A plurality of continuous input ATs to be sent out to the transmission path
An ATM cell signal format converter which converts an M cell signal format into an SDH format having a positive stuff area in which these ATM cells are inserted only in a payload portion of the SDH format, and transmits the signal onto the transmission path. A conversion memory for temporarily storing the ATM cells for converting the input ATM cell signal format into the SDH format;
A cell having a period corresponding to the number of bytes of one TM cell
Means for generating a cell pulse and counting this cell pulse
Means for generating a redundant cell pulse synchronized with the redundant cell
And the cell pulse and the redundant cell pulse
Means for generating a write pulse for the conversion memory, and write control means for controlling writing of the ATM cell to the conversion memory at a predetermined cycle; and
At the time of cell reading, the reading of ATM cells in the positive stuff area in the payload section is prohibited in n frames out of a predetermined number m (m is a positive integer) of consecutive frames of the SDH format, and the remaining mn (N
(A positive integer) in the frame, and a read control means for controlling to read the ATM cell in the positive stuff area is obtained.

[0018]

In the SDH format, a stuff execution area is provided to absorb the speed fluctuation of the transmission path. Specifically, 48 bytes called H3 byte of the SPOH (overhead) portion on the fourth line and its H3 48 bytes inside the payload after the byte. By arranging a signal in the 48 bytes of the payload portion of the stuff area, a signal of 37440 + 48 = 37488 bytes can be accommodated.

In the present invention, the SDH format stuff area is used. For example, 11 frames out of 24 frames are prohibited from reading out the cell signal of the stuff area from the memory, and the remaining 13 frames are stuff areas. The cell signal is also arranged.

In this case, the amount of write signals to the memory is 706 cells × 53 bytes × 24 frames = 898032.
The read signal amount is 37392 bytes x 11 frames + 37440 bytes x
13 frames = 898032 bytes, which are identical.

[0021]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. In the figure, a conversion memory 11 is a buffer memory for converting the internal signal format shown in FIG. 7 to the SDH format shown in FIG. 8 to be transmitted to the transmission path. The write counter 15 controls the writing of the memory 11, and the write counter control unit 14 controls the write counter 1
5, and operates with a reference frame signal (8 KHz) in a cell signal format inside the device.

The read counter 13 controls reading of the memory 11, and the read counter control unit 12 controls the operation of the read counter 13 and operates as an SDH.
It operates based on the 8 KHz frame signal which is a format reference signal.

The in-device cell signal to the memory 11 is sequentially written by the write counter control unit 14 and the write counter 15. In this case, as shown in FIG. Of the redundant byte (1 byte), and also inhibits the writing of 14 redundant cells every 8 KHz cycle.

For this purpose, the write counter control section 14 has the configuration shown in FIG. 2, and a time chart showing the operation thereof is shown in FIG. Cell time slot counter 3 for counting clock CLK in synchronization with a reference frame signal (8 KHz) of a cell signal format inside the device.
One. This clock CLK is a clock pulse synchronized with each byte (each byte of 0 to 53) of the cell signal. The cell time slot counter 31 has a count value of "0", that is, the first byte (redundant byte) of each cell. To generate a cell pulse synchronized with. Therefore, the period of the cell pulse corresponds to the period (54
TS: time slot).

A 52-ary cell counter 32 for counting cell pulses in synchronization with the reference frame signal is provided. When the count value is "0", that is, the first cell (redundant cell) of the 52 cell group is provided. ) Is generated. Therefore, the period of the redundant cell pulse corresponds to the length of the 52 cell groups. When the 8 KHz frame signal arrives, the contents of the cell counter 32 are forcibly initialized to "0".

The gate 33 adds and outputs the cell pulse and the redundant cell pulse, so that the waveform shown in FIG. 3 is obtained as a write counter control signal. The write counter 15 operates to prohibit writing during the period of the write counter control signal (shown as low active in FIG. 7). Therefore, while the write counter control signal is low, the counter 15 The input of the clock CLK synchronized with this byte is prohibited, and the writing of redundant bytes and redundant cells to the memory 11 during that period is prohibited.

As a result, the cell signal in the device written in the memory 11 becomes (720 cells−14 cells) × 53 bytes = 37418 bytes in a period of 125 μsec (8 KHz).

Next, the read control of the memory 11 will be described. FIG. 4 is a block diagram of the reading of FIG.
Shows a time chart showing an operation example of each part.

The time slot counter 21 is a 4320-base counter for counting the clock CLK synchronized with the byte of the cell signal in synchronization with the 8 KHz frame signal. This counter 21 is a signal (160 bytes) indicating the period (160 bytes) of the overhead part (shown as SOH / POH or SPOH) of the SDH format shown in FIG.
And the overhead period (160 bytes)
And a signal notation 'indicating the length obtained by further adding the period (48 bytes) of the positive stuff area to the signal stuff.

The row counter 22 is a ninth decimal counter which counts up each time the time slot counter 21 becomes "0" in synchronization with the frame signal, and its value is "3".
(Showing the fourth row of the STM16 frame format of the SDH format) and generate a low-level pulse.

The SOH / POH generating unit 24 is provided in FIG.
As shown in FIG. 2, a switch SW is provided. In addition to outputting two pulses, 'generated by the time slot counter 21 while selectively switching the two pulses,', by the output of the row counter 22, outputting a pulse. It has the function of outputting as it is.

The switch SW selects a pulse having a length of 160 bytes (160 TS) while the output of the low counter 22 is at the high level, and 2 bits during the low level (the fourth row).
A pulse 'having a length of 08 bytes (208 TS) is selected and output to be a pulse.

The frame counter 23 is a 24-decimal counter that counts 8 KHz frame signals. As shown in an operation example of FIG. 5B, the frame counter 23 is at a low level when the counted value is between "0" and "12". In addition, a pulse which becomes high level is generated between "13" and "23".

The frame selector 25 selects and outputs one of the input pulses in accordance with the high and low levels of the pulse from the frame counter 23. In this example, in the first 13 frames of the 24 frames, a 160-byte (160 TS) -long pulse is selected and used as a read counter control signal. In the remaining 11 frames, a 208-byte (208 TS) -long pulse portion (4 rows) is selected. (Corresponding to the eyes) is selected and becomes a read counter control signal.

The read counter 13 operates to inhibit the reading of the read control signal during its existence period (shown as low active in FIG. 8). Therefore, the counter 13 operates while the read counter control signal is low. The input of the clock CLK synchronized with the byte of the cell signal is prohibited, so that the reading of the SOH / POH section is necessarily prohibited, and the reading of the stuff area is prohibited during 11 out of 24 frames, and the remaining 13
During a frame, the data is read as a normal SDH format.

The write and read signal amounts for the memory 11 based on the above operation are calculated. The write signal amount is 70
6 cells x 53 bytes x 24 frames = 898032 bytes, and the read signal amount is 37392 bytes x 11 frames + 37440 bytes x
13 frames = 898032 bytes, the signal rates of both become the same, and no underflow of the memory 11 occurs.

When a cell signal is inserted into this stuff area, a flag byte called an AU pointer of H1 or H2 in the overhead portion is set to a positive stuff state and transmitted to the opposite station. Reception processing can be performed without any problem.

FIG. 6 shows the H1 and H2 bytes of the AU pointer. The first two bytes of the fourth row of the STM frame format in FIG. 8 are H1 and H2 bytes.
Of these, the last 10 bits are the AU pointer. By inverting each bit (indicated by *) shown in FIG. 6 among these 10 bits and transmitting the inverted bit to the opposite station, the opposite station executes positive stuff by using these inverted bits.

In the above-mentioned embodiment, the ITU recommendation, G. STM of FIG. 8 conforming to 709
Although a 16-frame format has been described, any frame format defined by STM1 × N (N is an integer) and having a positive stuff area can be similarly applied.

In the above embodiment, N = 16 and STM1
Taking the case of 6 as an example, n = 11 out of m = 24 frames
Although reading of the positive stuff area of the frame is prohibited, the values of m and n are appropriately selected according to the value of N, that is, according to the frame format.

[0042]

As described above, according to the present invention, the SD
Since the insertion and non-insertion of the cell signal are controlled in the positive stuff area of the H format so that the respective rates of writing and reading to the conversion memory are matched, underflow of the memory is detected and detected. There is an effect that a circuit to be avoided becomes unnecessary. Further, in the device, there is an effect that the position of the redundant cell can be fixed and the cell signal can be processed periodically.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram of a write counter control unit 15 of the block in FIG.

FIG. 3 is a time chart showing the operation of the block shown in FIG. 2;

FIG. 4 is a block diagram of a read counter control unit 12 of the block shown in FIG. 1;

FIG. 5 is a time chart showing the operation of the block in FIG. 4;

FIG. 6 shows H1 and H2 in the STM16 frame format.
FIG. 4 is a diagram showing a byte AU pointer.

FIG. 7 is a diagram showing a format of an in-device cell signal.

FIG. 8 is a diagram showing an SDH format.

FIG. 9 is a block diagram of a conventional ATM cell signal format converter.

[Explanation of symbols]

 11 Format Conversion Memory 12 Read Counter Control Unit 13 Read Counter 14 Write Counter Control Unit 15 Write Counter 21 Time Slot Counter 22 Row Counter 23 Frame Counter 24 SOH / POH Generation Unit 25 Frame Selector 31 Cell Time Slot Counter 32 Cell Counter 33 Gate

Claims (3)

(57) [Claims] A predetermined buffer including a redundant byte in a first byte.
A plurality of unit cells consisting of
One redundant cell is provided at the head of the continuation cell to form one cell group.
Further, a plurality of continuous input ATM cell signal formats to be transmitted to the transmission line are constructed by continuously arranging the cell groups, and these ATM cells are inserted only into the payload portion of the SDH format, and the positive stuff area is provided. An ATM cell signal format conversion device which converts the input ATM cell signal format into the SDH format and converts the input ATM cell signal format into the SDH format. A memory and a cycle corresponding to the number of bytes of one ATM cell.
Means for generating a cell pulse to be measured, and counting the cell pulse.
To generate a redundant cell pulse synchronized with the redundant cell.
Means and these cell and redundant cell pulses
Means for generating a write pulse for the conversion memory.
And a write control means for writing control the ATM cell to the conversion memory in a predetermined period, upon reading of the ATM cell from the conversion memory, a predetermined number m of consecutive said SDH format (m is a positive integer) of In the n frames, reading of the ATM cells in the positive stuff area in the payload portion is prohibited, and in the remaining mn (n is a positive integer) frames, reading of the ATM cells in the positive stuff area is performed. An ATM cell signal format conversion device, comprising: 2. The SDH format is one frame.
Consists of multiple lines, and each line has an overhead
However, the area following it is the payload section, and the
A positive staff area of a certain length follows the
Wherein the read control means is provided for each line of the SDH format.
Period signal indicating a period corresponding to the overhead part of
Means for generating, the overhead and the positive
The second indicating the total period with the period corresponding to the staff area
Means for generating a period signal;
Existence period before Symbol second period signal of positive stuff area
Signal for the remaining period alternatively derives the first period signal
First selecting means, and the selecting means for the n frames.
Of the first period signal in the mn frame.
And a second selecting means for alternatively deriving the output of the conversion memory.
2. The ATM cell signal format conversion device according to claim 1, wherein the ATM cell signal format conversion device is configured to use an ATM cell signal format. 3. The SDH format is an STM16 format.
Frame format, where m is 24 and n is 1
AT of claim 1, wherein a is 1
M cell signal format converter.