JP3570967B2 - Dual AAL1 conversion device and synchronization method used therefor - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a dual AAL1 conversion apparatus and a synchronization method used for the same, and more particularly to an AAL1 (ATM Adaptation Layer) for converting STM (Synchronous Transfer Mode) data into ATM (Asynchronous Transfer Mode) cells. 1) The present invention relates to a method of synchronizing each device when a dual configuration of an act system (active system) and a standby system (standby system) is used as a conversion device.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, an STM / ATM conversion device that converts STM data into ATM cells has a dual configuration of an act system and a standby system, and a device operating as an act system and a device operating as a standby system are used. Switching is in progress.
[0003]
As a synchronizing device for this dual STM / ATM converter, when switching between a device operating as an act system and a device operating as a standby system, an instantaneous interruption such as loss or duplication of information is performed. Japanese Patent Application Laid-Open Nos. Hei 9-55752 and Hei 11-298495 disclose switches that can be switched so as not to cause the occurrence.
[0004]
In the duplex STM / ATM converter described in the above publication, an inter-system signal line for connecting between an act STM / ATM converter and a standby STM / ATM converter is provided in each system. An input STM frame pulse counter (for example, a 376-base counter) for counting input STM frame pulses, and an input of the input STM frame pulse counter at the start of cell assembly when the SN (sequence number) value of the AAL1 header becomes "0" By transmitting and receiving the information of the STM frame pulse count value and the opening / closing information of each channel for each channel, the synchronization between the act system and the standby system is realized.
[0005]
According to this method, the STM accumulation states of the cell assembly buffers of the act system and the standby system can be matched without causing an instantaneous interruption of the main signal, and the act system and the standby system can be exchanged without data loss or duplication. System switching can be performed.
[0006]
[Problems to be solved by the invention]
In the conventional synchronization method described above, in the case of the method described in the above-mentioned publication, since the timing information of channel opening / closing, cell generation, and SN value matching is transmitted and received from the act system to the standby system individually, the number of channels is large. As a result, there is a problem that the scale of the circuit for performing the synchronization processing and the processing load increase rapidly.
[0007]
Further, the method described in the above publication does not take measures against an instantaneous increase in traffic caused by overlapping of AAL1 cell generation timings of a plurality of channels within the same time.
[0008]
Therefore, an object of the present invention is to solve the above-mentioned problems, and to simplify the circuit scale and device configuration and software processing required for synchronization when performing system switching without cell loss, thereby reducing cost and software. An object of the present invention is to provide a dual AAL1 conversion device capable of reducing a processing load and a synchronization method used for the same.
[0009]
[Means for Solving the Problems]
The dual AAL1 conversion device according to the present invention has a dual configuration of an act system and a standby system for converting STM (Synchronous Transfer Mode) data into an ATM (Asynchronous Transfer Mode) cell, respectively, and each user connection of the STM network. When the speed of the cell is constant and the own system is the act system, the preset generation timing of a specific VC (Virtual Channel) cell is communicated to another system to synchronize the cell generation timings of the act system and the standby system. take duplex AAL1 (ATM Adaptation Layer Type 1) a converter, comprising a generating means for generating a constantly AAL1 cells fixed number and phase-locked to the frame pulse to the act system and the standby system, respectively That.
[0010]
The method for synchronizing a dual AAL1 conversion device according to the present invention employs a dual configuration of an active system and a standby system for converting STM (Synchronous Transfer Mode) data into ATM (Asynchronous Transfer Mode) cells, respectively , and an STM network. When the speed of each user connection is constant and the own system is the act system, the preset timing of generation of a specific VC (Virtual Channel) cell is communicated to another system to generate cells of the act system and the standby system. a synchronization method of duplexing AAL1 (ATM Adaptation Layer Type 1) converter to synchronize the timing, in the act system and the standby system, respectively, always fixed number and phase-locked to the 1-frame pulse AAL And so as to produce a cell.
[0011]
That is, the dual AAL1 conversion device of the present invention converts STM (Synchronous Transfer Mode) data into an ATM (Asynchronous Transfer Mode) cell, and has an AAL1 (ATM Adaptation Layer) having a redundant configuration of an active system and a standby system. 1) In the conversion device, when the speed of each user connection of the STM network is constant, the AAL1 cell generation unit is used for both system synchronization methods, and the representative VC (Virtual Channel) cell generation timing is changed from the active system to the standby system between the two systems. Communication is performed [eg: every 376FP (Frame Pulse) count], and in each system, the AAL1 cell generation timing is always a fixed number and the phase is fixed within 1FP, so that the AA of the duplex synchronization is performed by a simple circuit. It is characterized in that an L1 conversion device can be realized.
[0012]
Specifically, in the duplexed AAL1 converter of the present invention, the same clock, frame pulse, and data synchronized with the AAL1 converter of the act system and the standby system are supplied from the STM network, and this data is transmitted to the ATM cell. The AAL1 SAR (AAL1 Segmentation And Reassembly: cell division / assembly sublayer) in each AAL1 conversion device that converts the data into a cell starts STM data cellization regardless of the cellization start / stop request from each system control unit. Opening / closing control is performed by discarding the corresponding VC cell.
[0013]
At the time of cell generation, the act AAL1SAR has a fixed number of cells (provisionally n) for each FP in order from the AAL1 cell of the youngest channel for each FP counter (376 FP count when each channel is 64 Kbps) in its own apparatus. Insert AAL1 cells into ATM cell stream.
[0014]
Further, in order to synchronize the generation timing of the AAL1 cell of the youngest channel of the AAL1SAR of both systems, the 376FP count timing of the act system is notified to the AAL1SAR of the standby system via a signal line between the systems.
[0015]
When the AAL1SAR of the standby system receives the above timing from the act system via the signal line between the systems, the AAL1SAR resynchronizes the signal with its own FP and sequentially generates the AAL1 cells of the lowest-numbered channel at the same timing as the act system. Is started, the VC and the payload of each cell generated by the AAL1SAR of both systems are matched.
[0016]
As a result, regardless of the opening and closing of each user connection, the timing of starting AAL1 cell formation and the order of cell cell formation are fixed for a single representative connection, and the payloads of the cells of both systems are matched. Even when there are many systems, both systems can be easily synchronized, and when the systems are switched, there is no occurrence of data duplication / order inversion / loss. Further, since the maximum number of AAL1 cells generated within one FP time is controlled by hardware, an instantaneous increase in effective cell traffic does not occur.
[0017]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of an ATM (Asynchronous Transfer Mode) exchange according to an embodiment of the present invention. In FIG. 1, an ATM switch 1 comprises a system 0 (act system: working system) 2 and a system 1 (standby system: standby system) 3, and the system 0 2 and the system 1 3 are AAL1 (ATM Adaptation). Layer Type 1) The conversion device has a duplex configuration.
[0018]
The 0-system device 2 and the 1-system device 3 include AAL1 cell conversion units 21 and 31, system confounding units 22, 24, 32 and 34, ATM switch units (ATM-SW) 23 and 33, and an ATM line package ( PKG) units 25 and 35.
[0019]
STM (Synchronous Transfer Mode) network data 101 and 102 are data from an act STM device and a standby STM device (not shown), respectively. The clock, the frame pulse, and the data are supplied to the AAL1 cell converters 21 and 31, and the AAL1 cell converters 21 and 31 are synchronized on the STM network side. The AAL1 cell converters 21 and 31 convert STM network data into ATM cells.
[0020]
The data of the STM network in which a plurality of channels are time-division multiplexed in a time slot (TS) on a frame is transmitted to the system interlinking units 22 and 32 in the ATM switch 1 via the AAL1 cell converters 21 and 31.
[0021]
ATM switches 23 and 33, which are functional units subsequent to the system confounding units 22 and 32, system conversing units 24 and 34, ATM line package units 25 and 35, and 2 in the ATM network to which ATM network data 103 and 104 are transmitted. Synchronization in the multiplexing unit (non-instantaneous interruption switching) is realized by existing technology.
[0022]
Therefore, if both the AAL1 cells output from the AAL1 cell converters 21 and 31 are synchronized with each other, no data instantaneous interruption occurs in the system interlinking units 22 and 32 when switching between the act system and the standby system. Double synchronization of the conversion units 21 and 31 is realized.
[0023]
The AAL1 cell converters 21 and 31 assemble AAL1 cells as a SAR (Segmentation And Reassembly) function, and convert the STM network data 101 and 102 into ATM cells. There are two types of AAL1 cell payload formats depending on the presence / absence of pointer information. Here, a description will be given of a format composed of a 1-byte AAL1 cell header and 47-byte user data which is normally used when 1 channel = 64 Kbps is set. I do.
[0024]
FIG. 2 is a diagram showing a configuration example of the AAL1 cell format used in one embodiment of the present invention. FIG. 2 shows the format of an AAL1 cell used in an existing duplex ATM switch.
[0025]
The AAL1 cell header is composed of a 1-bit Convergence Sublayer Indication (CSI), a 3-bit SN (Sequence Number), and a 4-bit SNP (SN Protection).
[0026]
The CSI bit is a bit for distinguishing between two types of AAL1 cell formats, and the SN bit is a bit for counting cells from "0" to "7" and monitoring the occurrence of cell loss / duplication / order reversal. The SNP bit is obtained by performing a CRC (Cyclic Redundancy Check) operation on the SN bit. Since the content of AAL1SAR is not directly related to the present invention, a detailed description thereof will be omitted.
[0027]
The reason why 1 byte (byte) redundant data is added to the cell and the cell length is set to 54 bytes is to synchronize the cell head phase with the internal reference 8 kHz FP. This is a commonly used technology.
[0028]
For example, the cell interface of the system interlinking units 22 and 32 in the ATM exchange 1 shown in FIG. In the case where the line speed is 155.52 Mbps, 45 cells (valid cells + empty cells total) are always included in one FP (125 μs) of the reference 8 kHz signal. Has a cycle of 360 kHz, so that the cycle is synchronized with the reference 8 kHz so that the cell phases of both systems are matched.
[0029]
The input side specification of the ATM side interface of AAL1SAR is as described above. The STM side has 1024TS (time slot) data of 65.536 Mbps, the number of effective channels is 1024 (all time slots), and the AAL1 conversion is 64 Kbps (1TS = 1VC) for each channel. FIG. 3 shows the operation in the AAL1SAR in the case of (correspondence).
[0030]
FIG. 3 is a block diagram showing a configuration example of the duplex synchronization AAL1SAR function according to one embodiment of the present invention. FIG. 3 shows the dual synchronization AAL1 SAR function of the AAL1 cell converters 21 and 31 described above.
[0031]
In FIG. 3, the duplex synchronization AAL1SAR function 4 includes a frame storage buffer 41, an AAL1 cell payload read control unit 42, an AAL1 header addition unit 43, an ATM header addition unit 44, a specific VC cell discard unit 45, and 47. A frame counter 46, a synchronous confounding control unit 47 × 8 frame counter 47, a line Open / Close instructing unit 48, a scheduler setting unit 49, and an ACT (act) / SBY (standby) instruction / synchronous operation instructing unit 50 It is configured.
[0032]
FIG. 4 is a diagram illustrating a phase relationship of an AAL1SAR output cell according to an embodiment of the present invention. The system switching operation in one embodiment of the present invention will be described with reference to FIGS.
[0033]
Since the AAL1 cell payload of each VC is 47 bytes, the same VC cell can be generated for every 47 FP when each channel is 64 Kbps. Since the SN bit is a period counter from “0” to “7”, the generation interval of cells having the same VC and the same AAL1 header is 47 × 8 = 376FP.
[0034]
In addition, since it is necessary to generate 1024 AAL1 cells for all channels in 47 FP time while keeping the number of AAL1 cells generated in 1 FP time fixed, the dual synchronization AAL1 SAR function 4 must be generated in 1 FP time. The number (n) of AAL1 cells that must be
n ≧ 1024 ÷ 47 ≒ 21.8
It becomes.
[0035]
The number of cells that can be inserted into the ATM interface by the duplex synchronization AAL1SAR function 4 within one FP time is a maximum of 45 cells as described above.
22 ≦ n ≦ 45
Must be set in the range. If the value of n is small, the instantaneous increase in effective cell traffic can be suppressed, so here, a value of n = 22 is temporarily set by the above-described software processing.
[0036]
From the above setting parameters, the AAL1 cell payload read control unit 42, AAL1 header adding unit 43, and ATM header adding unit 44 in the duplex synchronization AAL1SAR function 4 generate 22 cells in one FP time. 22 × 47 = 1034 cells (1034 types of VCs) are generated, which is 10 channels more than the required total number of 1024 TSs on the STM side.
[0037]
However, for the redundant channel (VC), the line open / close instructing unit 48 instructs fixedly to block the ten channels (temporarily 1024 to 1033) from the oldest VC number by a soft instruction, and thereby a specific VC cell discarding unit. At 45, there is no problem because a countermeasure by discarding (empty cell replacement) is possible.
[0038]
The frame storage buffer 41 stores the STM data for each TS. In addition, since the read / write pointers of the frame storage buffer 41 need to be matched in both systems, the initialization of the pointers follows the counter value of the 47 frame counter 46.
[0039]
The AAL1 cell payload read control unit 42 sequentially reads the 22 types of TS data for each FP in a 47-byte sequence starting from the smallest number, and uses the read data as the payload information of the AAL1 cell. When a signal from the 47 frame counter 46 is received, the read pointer of the TS data is returned to the lowest TS.
[0040]
The AAL1 header adding unit 43 adds the same AAL1 header information to all cells within the 47 FP time. When a signal from the 47 frame counter 46 is received, the SN value is incremented by one in synchronization with the timing, and the SNP is calculated again. When a signal from the synchronous confounding control unit 47 × 8 frame counter 47 is received, the SN value is initialized to “0”.
[0041]
The ATM header adding unit 44 adds an ATM header. The VC value is set such that the cell after receiving the signal from the 47 frame counter 46 is the lowest VC, and the VC value is incremented by 1 from the beginning of the cell (45 cells) in the 1FP to the 22nd cell (AAL cell in FIG. 4). VC). Here, cell validity information is given to the above 22 cells, and cell invalidity (vacant cell) information is given to the latter 23 cells.
[0042]
The specific VC cell discarding unit 45 replaces an empty cell of the VC cell for which the blocking instruction is given from the control interface. Since the VC of the cell input to the specific VC cell discarding unit 45 is determined by the phase from the beginning of the 47 FP signal similarly to the ATM header adding unit 44, the 22 channels transmitted for each FP from the line Open / Close instructing unit 48 Empty cell replacement of valid cells is performed according to the minute Open / Close instruction signal.
[0043]
Also, as described above, 10 cells from the oldest VC number (VC numbers = 1024 to 1033) are unnecessary cells in which data that does not exist in the STM information is carried in the payload, so that the line Open / Close instructing unit 48 The block instruction of the corresponding channel is explicitly performed, and the specific VC cell discarding unit 45 replaces all empty cells.
[0044]
Further, as another method of discarding the cell, it is possible to retrieve the channel open / close information by searching the information of the line open / close instruction unit 48 from the VC information every time the cell arrives. There is a disadvantage that the access frequency to the unit 48 increases, and the processing becomes heavy for both hardware and software.
[0045]
The 47 frame counter 46 is a counter that counts 47 frames of an 8 kHz frame signal serving as a reference of the own system. The two systems of the counter 46 are synchronized.
[0046]
The synchronous confounding control unit 47 × 8 frame counter 47 is a 47 × 8 frame (376 frame) counter having a synchronous confounding control function between the AAL1 cell conversion units 21 and 31 of both systems. The signal for each 376FP generated in the own system is output to the AAL1 header adding unit 43 and the 47 frame counter 46 in the AAL1 cell converters 21 and 31 of the own system and the AAL1 cell converters 31 and 21 of the other system.
[0047]
In the synchronous confounding control unit 47 × 8 frame counter 47, if the instruction from the ACT / SBY instruction / synchronous operation instruction unit 50 of the own system is a standby and synchronous operation instruction, the AAL1 cell conversion units 31 and 21 of the other system. Are used as counter reset signals of the synchronous confounding control unit 47 × 8 frame counter 47 to perform slave synchronization.
[0048]
The line Open / Close instructing unit 48 has a control register (not shown), and holds opening / closing instruction information of each channel from the control interface. Further, as described above, it may be necessary to hold channel opening / closing information that is equal to or more than the number of TSs included in the STM data. In the above example, the line Open / Close instructing unit 48 needs to have information of 1034 channels (VC) for 1024 channels (TS) on the STM side.
[0049]
Further, the line Open / Close instructing unit 48 has a function of transmitting to the specific VC cell discarding unit 45 opening / closing information of channels corresponding to 22 types of VCs assigned by the ATM header assigning unit 44 for each FP.
[0050]
The scheduler setting unit 49 is a control register having setting information on how many AAL1 cells are generated every 1 FP time. The ACT / SBY instruction / synchronous operation instruction unit 50 is a control register having act / standby information of the AAL1 cell conversion units 21 and 31 of the own system and information indicating whether or not to perform the synchronous operation of both systems.
[0051]
FIG. 4 shows a phase relationship with respect to the reference 8 kHz (1 FP), a phase relationship with 47 FP, and a phase relationship with 376 FP of the cells before discarding the specific VC cell output from the ATM header adding unit 44.
[0052]
There are 45 cells (valid cells + empty cells) in the standard 8 kHz (1 FP), of which the first 22 cells are AAL1 cells having valid cell information, and the latter 23 cells are empty cells having an undefined value. is there. 22 types of VC cells are sequentially generated in one FP from the youngest, and 1034 types of VC cells are generated in 47 FP hours. An AAL1 header having an SN of the same value is fixedly provided to all cells in the meantime. In the next 47FP time, an AAL1 header obtained by adding 1 to SN and recalculating SNP is added.
[0053]
By such an operation, the phase of each VC cell from the beginning of the 376FP is fixed in each system, so that the representative VC (for example, VC = 0) generation interval between the AAL1 cell converters 21 and 31 of both systems is fixed. By using the synchronized 376FP as a synchronization confounding signal and synchronizing the 376FP with the AAL1 cell converters 21 and 31 of both systems, phase synchronization of both systems with respect to all VC cells can be established.
[0054]
Regarding the timing of channel opening / closing (cell discarding) in the specific VC cell discarding unit 45, 22 channels are opened / closed every 1 FP between the line Open / Close instructing unit 48 and the specific VC cell discarding unit 45. By providing a function of transmitting and receiving information, it is possible to synchronize both systems of the specific VC cell discarding unit 45. By adding the condition that "the line switching instruction is not changed before and after the switching time", it is possible to cope with the instantaneous interruption system switching, and this method reduces the circuit scale and the inter-system confounding signal. be able to.
[0055]
As described above, when converting the data of the STM network into the ATM cells, the synchronization of the AAL1 cell converters 21 and 31 of both systems is realized by the synchronous confounding signal of only the representative line, so that the circuit scale is very small. In addition, since there is little hardware processing content, it is possible to easily cope with a case where the number of channels needs to be increased.
[0056]
In addition, since the number of AAL1 cells generated is constant per unit time (1 FP), no bursty traffic occurs in the ATM cell flow, and since the control setting information of the AAL1 cell converters 21 and 31 is small, the load of software processing is reduced. Can be reduced, the hardware cost can be reduced and the software processing can be performed lightly.
[0057]
Therefore, cost reduction by reducing the circuit scale required for synchronizing the duplicated AAL1 cell converters 21 and 31 for converting STM data into ATM cells, reduction in software processing by adding a traffic control function by hardware, and burst Traffic generation can be avoided.
[0058]
【The invention's effect】
As described above, according to the present invention, in a dual AAL1 conversion apparatus having a dual configuration of an act system and a standby system for converting STM data into ATM cells, the STM network is used in each of the act system and the standby system. When the speed of each user connection is constant and the own system is the act system, the preset generation timing of the specific VC cell is communicated to the other system, and a fixed number and phase fixed AAL1 cell is always generated within one frame pulse. By doing so, it is possible to simplify the circuit scale, device configuration, and software processing required for synchronization when performing system switching without cell loss, thereby achieving cost reduction and software processing load reduction. effective.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of an ATM exchange according to an embodiment of the present invention.
FIG. 2 is a diagram showing a configuration example of an AAL1 cell format used in one embodiment of the present invention.
FIG. 3 is a block diagram illustrating a configuration example of a duplex synchronization AAL1SAR function according to an embodiment of the present invention.
FIG. 4 is a diagram illustrating a phase relationship of an AAL1SAR output cell according to an embodiment of the present invention.
[Explanation of symbols]
Reference Signs List 1 ATM switch 2 0 system device 3 1 system device 4 Duplex synchronization AAL1 SAR function 21, 31 AAL1 cell conversion unit 22, 24, 32, 34 System confounding unit 23, 33 ATM switch unit 25, 35 ATM line package unit 41 Frame Storage buffer 42 AAL1 cell payload reading control unit 43 AAL1 header adding unit 44 ATM header adding unit 45 Specific VC cell discarding unit 46 47 Frame counter 47 Synchronous confounding control unit 47 × 8 frame counter 48 Line Open / Close instructing unit 49 Scheduler setting unit 50 ACT / SBY instruction / synchronous operation instruction unit 101, 102 STM network data 103, 104 ATM network data

Claims (12)

Each of the STM (Synchronous Transfer Mode) data is converted into an ATM (Asynchronous Transfer Mode) cell by using an act system and a standby system, which are duplicated. In addition, the speed of each user connection of the STM network is constant and the own system is the act system. A redundant AAL1 (ATM Adaptation Layer Type 1) that synchronizes the cell generation timing of the act system and the standby system by communicating the generation timing of a specific VC (Virtual Channel) cell set in advance in the system to another system. ) a converter, always a fixed number and phase duplex AAL1 conversion device characterized by having a generating means for generating each said act system and the standby system the AAL1 cells fixed in 1 frame pulse An AAL1 SAR (AAL1 Segmentation Reassembly) that converts the data into the ATM cells based on the same synchronized clock, frame pulse, and data supplied from the STM network to the act system and the standby system, respectively, 2. The dual AAL1 conversion device according to claim 1, wherein the communication unit and the generation unit are included in the AAL1SAR in each of the system and the standby system. 3. The dual AAL1 conversion device according to claim 2, wherein said AAL1SAR starts cellization of said STM data regardless of a cellization start / stop request from outside. 4. The dual AAL1 conversion device according to claim 2, wherein the AAL1SAR performs opening / closing control of each channel by discarding a corresponding VC cell. The AAL1SAR is the number of cells per frame pulse in order from the AAL1 cell of the youngest channel for each predetermined count value of the frame pulse counter that counts the frame pulse when the own system is the act system when the ATM cell is generated. 5. The dual AAL1 conversion device according to claim 2, wherein AAL1 cells are inserted into said ATM cell stream in a fixed manner. The AAL1SAR according to any one of claims 2 to 5, wherein when the own system is the standby system, the own system is resynchronized based on the generation timing from the act system. Dual AAL1 converter. Each of the STM (Synchronous Transfer Mode) data is converted into an ATM (Asynchronous Transfer Mode) cell by using an act system and a standby system, which are duplicated. In addition, the speed of each user connection of the STM network is constant and the own system is the act system. A redundant AAL1 (ATM Adaptation Layer Type 1) that synchronizes the cell generation timing of the act system and the standby system by communicating the generation timing of a specific VC (Virtual Channel) cell set in advance in the system to another system. A) a method of synchronizing a conversion device, wherein each of the act system and the standby system always generates a fixed number and a fixed phase of AAL1 cells within one frame pulse. . AAL1SAR of each of the act system and the standby system for converting the data into the ATM cell based on the same synchronized clock, frame pulse and data supplied from the STM network to the act system and the standby system, respectively. 8. The synchronization according to claim 7, wherein in (AAL1 Segmentation And Reassembly), communication of the generation timing of the specific VC cell to another system and generation of the fixed number and phase-fixed AAL1 cell are performed. Method. 9. The synchronization method according to claim 8, wherein the AAL1SAR starts cellizing the STM data regardless of an external celling start / stop request. 10. The synchronization method according to claim 8, wherein the AAL1SAR performs switching control of each channel by discarding a corresponding VC cell. The AAL1SAR is the number of cells per frame pulse in order from the AAL1 cell of the youngest channel for each predetermined count value of the frame pulse counter that counts the frame pulse when the own system is the act system when generating the ATM cells. 11. The synchronization method according to claim 8, wherein an AAL1 cell is inserted into the ATM cell stream in a fixed manner. The AAL1SAR according to any one of claims 8 to 11, wherein the AAL1SAR resynchronizes the own system based on the generation timing from the act system when the own system is the standby system. Synchronization method.

Images