JP3060377B2 - ATM cell test signal generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ATM (Asyn)
The present invention relates to an ATM cell test signal generator that generates cell data into which a pseudo-random signal is inserted in order to evaluate the quality of a line in a cross transfer mode (cross transfer mode).

[0002]

2. Description of the Related Art When evaluating the quality of a transmission line in a digital communication network, a transmitter generally sends a pseudo-random signal (hereinafter, referred to as a PN signal) to a transmission line to be tested and transmits it to a receiver. , And compares it with a pattern of a reference PN signal generated inside the receiver to detect a bit error of the pattern.

In the case of ATM, which is one of the digital transmission systems, it is effective to evaluate a transmission line using this PN signal. Cell data including a 5-byte header section and a 48-byte information section is transmitted. ATM as one transmission unit
In the case of, it is necessary to divide a series of PN signals, insert the PN signals into the information section of each cell, and output them.

As one method of realizing this, a method is conceivable in which a plurality of cell data in which a PN signal is inserted into an information section are written in a memory in advance in an output order, and are read out in order.

However, in this method, at least the number of cells necessary to insert at least one cycle of the PN signal must be stored in the memory in advance, so that a large-capacity memory is required. The data writing time becomes longer.

[0006] In addition, ATM has a plurality of specifications indicated by AAL values with respect to the format of the information section of cell data. A cell data generator for testing an ATM line conforms to the plurality of specifications. Cell data must be generated.

[0007] That is, according to the AAL1 rules, the information section 1 to 1
Up to the second byte is specified as an area for inserting specific information (CSI, SN, etc.), and the third and subsequent bytes are specified as a transmission information area into which a PN signal can be inserted.

According to the AAL2 specification, a cell for transmitting the head of information to be actually transmitted (hereinafter referred to as transmission information) is designated by the first to fourth bytes of the information portion as an area into which specific information is inserted. And the fifth and subsequent bytes are P
N is specified as a transmission information area into which the N signal can be inserted, and the second byte of the information part is specified as an area into which specific information is to be inserted, and the PN signal after the third byte is specified for a cell for transmitting the middle part and the last part of the transmission information Is specified as a transmission information area in which a can be inserted.

In the AAL3 / 4 specification, the area for inserting the specific information is specified at the beginning and end of the information section, and the area between them is specified as the transmission information area where the PN signal can be inserted. The length of the area in which the specific information is inserted changes depending on the cell that sends the head of the transmission information, the cell that sends the middle part of the transmission information, and the cell that sends the tail of the transmission information.

[0010] In the AAL5 specification, a cell for transmitting a head portion or an intermediate portion of transmission information has 48 bits in the information portion.
The entire byte can be used as a transmission information area, and for a cell for transmitting the last part of the transmission information, at least 8 bytes at the end of the information part are designated as an area for inserting specific information.

In order to promptly output the cell data in which the PN signal is inserted in a format corresponding to the transmission line to be tested from among the plurality of types of specifications, the cell is stored in the memory for each of the above specifications. The data must be stored, the writing time is further increased, and the capacity of the memory is further increased.

In order to solve this problem, a test signal generator having a configuration in which a PN signal is inserted into cell data read from a memory and output as shown in FIG. 8 can be considered.

In this test signal generator, cell data in which only necessary information is preliminarily written in the header section is stored in advance in the cell generation memory 11 with a 1-byte width, for example. 53-bit timing data patterned so that the byte position where the PN signal is inserted is “1” and the position where the PN signal is not inserted is “0” is stored in the timing data memory 12 in advance. The cell data is read out from the generation memory 11 in 1-byte units, and the timing data is read out from the timing data memory 12 in 1-bit units.
The N signal generation circuit 14 generates a PN signal one byte at a time, and the PN signal insertion circuit 15 adds the PN signal generation circuit 14 to the cell data read from the cell generation memory 11.
And outputs the PN signal.

In the test signal generator configured as described above, for example, the PN signal is inserted according to the AAL1 specification in which the third and subsequent bytes of the cell information section are specified in the transmission information area into which the PN signal can be inserted. When only cell data is continuously generated, as shown in FIG. 9A, only one type of cell data Ds in which header information A1 to A5 is written is stored in the memory 11 for cell generation. The timing data Dt in which the first to seventh bits are “0” and the eighth to 53rd bits are “1” are written in the timing data memory 12. The data B1 to B48 in the information section of the cell data Ds are initial data of the memory.

Then, when the data reading circuit 13 starts reading data from the cell generation memory 11 and the timing data memory 12, (a) of FIG.
As shown in FIG. 10B, the cell data Ds and the timing data Dt are read out, and the PN signal generation circuit 14 sets the information part 3 of the cell data Ds of the cell generation memory 11 as shown in FIG. 4 since the byte was read
Until the 8th byte is read, 46 bytes in 1 byte width
The PN signal is output continuously from the third byte of each cell data Ds as shown in FIG.
It is inserted and output by the 8th byte.

When the cell data into which the PN signal is inserted is output with the cell data for dummy interposed therebetween, the cell generation memory 11 stores the dummy cell data in addition to the cell data for inserting the PN signal. In addition to writing data in advance, timing data of all bits "0" corresponding to the dummy cell data is written in the timing data memory 12, and the data reading circuit 13 outputs the PN signal insertion cell data and the timing. Data reading and reading of dummy cell data and their timing data may be switched and performed.

If another rule is specified, a plurality of patterns of timing data required for the rule are stored in the timing data memory 12, and the timing data is read in parallel with the reading of the cell data Ds. May be selectively read.

As described above, if the cell data into which the PN signal is inserted is generated by using the cell generation memory 11 and the timing data memory 12, for example, it is necessary to generate the plurality of prescribed cell data. The timing data of all patterns is stored in the timing data memory 12 in advance.
, The capacity of the two memories is very small as compared with the method of storing all the cell data in which the PN signal is inserted in advance in the memory.

[0019]

However, the test signal generator having the above configuration requires two independent RAMs, a memory for cell generation and a timing data memory, so that writing and reading of data to and from the memory is required. There is a problem that the scale of circuit mounting increases when necessary peripheral circuits are combined.

As shown by the dotted line in FIG. 8, if the specific information insertion circuit 16 attempts to insert specific information at the beginning or end of the information section of the cell data before inserting the PN signal, Due to the data delay by the insertion circuit 16, the phase of the cell data Ds output from the memory 11 for cell generation and the timing data Dt output from the timing data memory 12 become out of phase, and the timing data is delayed for this phase adjustment. More circuits are required, and the circuits become more and more complex.

According to the present invention, this problem can be solved, the circuit mounting scale can be reduced, and even if another data is inserted before the PN signal is inserted, it is not necessary to consider the phase shift between the PN signal and the cell data. An object of the present invention is to provide an ATM cell test signal generator.

[0022]

In order to achieve the above object, an ATM test signal generator according to the present invention comprises an ATM cell for inserting a pseudo-random signal at a desired position in cell data for each cell data and outputting the same. A test signal generator,
Cell data storage means (21) for storing cell data to which control data indicating the desired position by a numerical value is added in order to insert the pseudo random signal at a specified desired position; A cell data reading means (23) for reading stored cell data;
Control data extracting means (25) for extracting the control data from the cell data read by the cell data reading means; and receiving the extracted control data and receiving the desired control data based on a numerical value indicated by the control data. Control means for generating and outputting a timing signal corresponding to the position; pseudo-random signal generating means for generating a pseudo-random signal in response to the timing signal output from the control means; Pseudo random signal insertion means (28) for inserting a signal at a desired position of the cell data to which the control data has been added.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows A of an embodiment of the present invention.
2 shows a configuration of a TM cell test signal generator.

In FIG. 1, a memory 21 for cell generation includes
It has a plurality of storage areas that can store 54-byte data with 53-byte cell data and 1-byte control data Dc added in 2-byte width.

The data writing means 22 writes cell data necessary for the test in the cell generation memory 21 in advance.
The cell data includes not only cell data for inserting a PN signal required for error measurement but also a dummy cell. As shown in FIG. 2, the data writing unit 22 writes header information A1 to A5, such as destinations, into the header portion from the first byte to the fifth byte of each storage area of the memory 21 for cell generation.
Write 8-bit control data Dc to the byte. The data B1 to B48 in the information section are initial data in the memory.

As described above, by adding odd 1-byte control data to 53-byte cell data to form an even-numbered 54-byte structure, it is easy and inexpensive to obtain a 2-byte data width. A RAM memory can be used as the cell generation memory 21, and its area can be used without waste. Here, the control data Dc is 1 byte long so that the minimum bytes can correspond to the above-mentioned rules AAL1 and AAL5.
The control data Dc may be 2 to 3 bytes so as to correspond to AAL2 to AAL4.

The control data Dc added to the cell data indicates the types of cells used for the rules AAL1 and AAL5 and the insertion start position or insertion end position of the PN signal. For example, the 8-bit control data Dc is set to [b
7, b6,... B1, b0], the upper two bits [b7, b6] are set to [1, 0] in the case of a cell in which the PN signal is inserted from the middle to the end of the information part.
The head byte position of the transmission information area is designated by the value N (> 0) of the lower 6 bits [b5, b4,..., B1, b0].

In the case of a cell in which the entire 48-byte information part is a transmission information area into which a PN signal can be inserted, the upper two bits [b7, b6] are set to [0, 0], and the lower six bits [b5, b4,... b1, b0] may be any value other than “0”.

In the case where a cell is a transmission information area in which the PN signal can be inserted from the beginning to the middle of the information part, the upper two bits [b7, b6] are set to [0, 1], and the transmission information area is The last byte position is determined by the lower 6 bits [b5, b
4,... B1, b0].

In the case of a cell into which the PN signal is not inserted, the value N of the lower 6 bits [b5, b4,.
To “0” (all digits “0”), and the upper two bits [b7, b
6] is optional.

When the specified AAL1 is designated by a designation circuit (not shown) and the data writing circuit 23 is instructed to output the cell data into which the PN signal is inserted and the dummy cell data, the data writing circuit 23 shown in FIG. As shown in a) and (b),

Cell data Ds1 for dummy to which control data Dc1 of [00000000] is added;
The cell data Ds2 for inserting the PN signal to which the control data Dc2 of [10000011] is added is written into the cell generation memory 21.

Also, for example, the rule AAL5 is specified, and P
When it is instructed to output the cell data into which the N signal has been inserted and the dummy cell data, FIG.
As shown in (c), the dummy cell data Ds1 similar to the above and the control data Dc of [00000001] for inserting the head part and intermediate part of the PN signal.
The cell data Ds3 to which the No. 3 is added and the cell data Ds4 to which the control data Dc3 of [01100111] is added to insert the last part of the PN signal are written into the cell generation memory 21.

The above four types of cell data Ds1
To Ds4 may be stored in the cell generation memory 21 in advance.

When receiving a signal (not shown) for instructing the start of cell data output, cell data read circuit 23 outputs an address signal synchronized with clock signal CK to cell generation memory 21 to store the data for cell generation. Each cell data stored in the memory 21 is read out in a designated order.

That is, as described above, in the prescribed AAL1, P
When it is instructed to alternately output the cell data for inserting the N signal and the cell data for the dummy, the cell data Ds2 for inserting the PN signal after reading all the dummy cell data Ds1 from the memory 21 for cell generation. Is repeated.

When it is instructed to output the cell data for inserting the PN signal and the cell data for the dummy alternately in the specified AAL5, the reading of the cell data Ds1 and the cell data Ds2 is alternately performed a predetermined number of times. Do
Following the reading of the last dummy cell data Ds1,
Read all the cell data Ds2.

The cell data read circuit 23 outputs a cell top signal which is at a high level only during reading of data up to the sixth byte from the head of each cell data (ie, three cycles of the clock signal CK). .

The control data extracting circuit 25 extracts the lower 8 bits of the third 16-bit data counted from when the cell head signal goes high, as control data for this cell. Output to the control circuit 26.

The control circuit 26 is constituted by a programmable gate array capable of high-speed operation. Based on the extracted control data Dc, the byte designating signals S1 and S2 are used as timing signals indicating the timing for inserting a PN signal. And a gate signal G. Here, the gate signal G is a signal which is at a high level only during a period in which the PN signal is generated in units of 2 bytes, and the byte designation signal S1 is a PN signal in the upper 1 byte side of the cell data read out in units of 2 bytes from the cell generation memory 21. Signal for inserting upper one byte of signal, byte designation signal S
Reference numeral 2 denotes a signal for inserting the lower 1 byte of the PN signal into the lower 1 byte of the cell data. The gate signal G is equal to the longer one of the byte designating signals S1 and S2 (the logical sum output of the signals S1 and S2).

The control circuit 26 controls the control data Dc.
Is read at time t0, the time at which the next cell head signal is output is t1, and the lower 5 bits [b5, b4, b3, b
2, b1], the cycle of the clock signal CK is T, and the byte designation signals S1, S2 and the gate signal G shown in FIG. 5 are output according to the control data.

That is, when the upper two bits [b7, b6] of the control data Dc are [1, 0] and the least significant bit b0 is [1], the level becomes high after (m + 1) T time from time t0, and at time t1. It outputs byte designating signals S1, S2 and a gate signal G returning to low level.

The upper two bits [b7, b6] of the control data Dc are [1, 0] and the least significant bit b0 is

In the case of [0], a byte designating signal S1 which becomes high level after (m + 1) T time from time t0 and returns to low level at time t1 is output, and becomes high level after mT time from time t0 and returns to low level at time t1 Designation signal S2
And a gate signal G.

When the upper two bits [b7, b6] of the control data Dc are [0, 0], the byte designating signals S1, S2 and the gates which become high level after T time from time t0 and return to low level at time t1 are returned. The signal G is output.

The upper two bits [b7, b6] of the control data Dc are [0, 1] and the least significant bit b0
Is [1], the byte designating signal S1 and the gate signal G which become high level after T time from time t0 and return to low level after (m + 2) T time from time t0 are output, and become high level after T time from time t0. The byte designation signal S2 which returns to the low level after the time (m + 1) T from the time t0 is output.

The upper two bits [b7, b6] of the control data Dc are [0, 1] and the least significant bit b0
But

In the case of [0], the insertion byte signals S1, S2 and the gate signal G which become high level after T time from time t0 and return to low level after (m + 1) T time from time t0 are output.

When the value N of the lower 6 bits [b5, b4, b3, b2, b1, b0] of the control data Dc is "0", the control circuit 26 outputs at least the next cell head signal. Until then, the levels of the byte designating signals S1, S2 and the gate signal G are maintained at low level.

Gate signal G output from control circuit 26
Is input to the PN signal generation circuit 27. The PN signal generation circuit 27 generates a PN signal by two bytes each time the clock signal CK is input while the gate signal G is at the high level, and outputs the generated PN signal to the PN signal insertion circuit.

The PN signal insertion circuit 28 receives the cell data output from the cell generation memory 21 two bytes at a time and the PN signal output two bytes at a time from the PN signal generation circuit 27, and receives the byte data from the control circuit 26. Designation signals S1, S
In accordance with the level 2, the PN signal is inserted into the cell data and output.

That is, when the byte designating signals S1 and S2 are both at the low level, the 2-byte data output from the cell generation memory 21 is output as it is, and when the byte designating signals S1 and S2 are both at the high level, the PN signal is output. The 2-byte data output from the signal generation circuit 27 is output.

When the byte designating signal S1 is at a low level and S2 is at a high level, the upper 1 byte of the 2-byte data output from the cell generation memory 21 and the PN
It outputs 2-byte data composed of the lower 1 byte of the 2-byte PN signal output from the signal generation circuit 27.

When the byte designation signal S1 is at a high level and S2 is at a low level, the upper one byte of the two-byte data output from the PN signal generation circuit 27 and the two bytes output from the cell generation memory 21 2 bytes of data consisting of the lower 1 byte of the PN signal.

The cell data output from the PN signal insertion circuit 28 is converted to 1-byte data by a 2-to-1 demultiplexer 29 and output.

The control data elimination circuit 30 has an F which can store and read a plurality of 1-byte data, for example.
It has an IFO (First-IN First-OUT) memory inside, and is configured to read out cell data output from the demultiplexer 29 with a 1-byte width in the FIFO memory while writing the data in the FIFO memory. By skipping the reading of the data, the control data Dc added to the cell data is removed.

Next, the operation of the ATM cell test signal generator will be described. For example, if the AAL1 rule specifies that the cell data into which the PN signal is inserted and the dummy cell data are generated alternately, the cell data read circuit 2
3, the cell data Ds1 and Ds2 are alternately output from the cell generation memory 21 as shown in FIG. 6A, and the cell head signal and the clock signal CK are output as shown in FIG.
(B) and (c).

The cell data D to be read first
The control data Dc1 is extracted from s1 as shown in (d) of FIG. 6, but since the value N of the lower 6 bits is "0", the byte designation signals S1, S2 and the gate signal G are
It remains at the low level as shown in (e) to (g) of FIG. Therefore, the PN signal is not output from the PN signal generation circuit 27 (FIG. 6 (h)), and is output from the cell generation memory 21 as shown in FIG. 6 (i) from the PN signal insertion circuit 28. The output cell data Ds1 is output as it is.

Then, the cell data Ds1 is converted to a one-byte width, and the control data Dc1 is removed and output as shown in FIG. 6 (j).

The control data Dc2 of the cell data Ds2 to be extracted next is [10000011] (m = 1).
Therefore, the byte designation signals S1 and S2 and the gate signal G are 2 · T after the control data is read.
After a lapse of time, the signal goes to a high level and returns to a low level when the next cell head signal is input.

For this reason, the 2-byte PN signal is continuously output from the PN signal generating circuit 27 23 times as shown in FIG. 6H, and the PN signal is output as shown in FIG. 6I. It is inserted and output from the third byte to the 48th byte of the information section of the cell data Ds2.

Similarly, cell data Ds2 into which the PN signal is inserted and dummy cell data Ds1 are alternately output from the third byte to the 48th byte of the information section.

When the AAL5 rule is specified, the cell data read circuit 23 outputs the cell data Ds from the cell generation memory 21 as shown in FIG.
After Ds3 is alternately read out a predetermined number of times, cell data Ds4 is read out. FIG. 7B shows a cell head signal, and FIG. 7C shows a clock signal.

As described above, since the value N of the lower 6 bits of the control data Dc1 of the cell data Ds1 which is read first is "0", the byte designation signals S1, S2 and the gate signal G are shown in FIG. 7 (g), the PN signal is not output ((h) in FIG. 7), and the PN signal insertion circuit 28 outputs (i) in FIG.
As shown in FIG. 8, the cell data Ds1 read out from the cell generation memory 21 is output as it is, converted to a 1-byte width, and the control data Dc1 as shown in FIG.
Is removed and output.

Since the control data Dc3 of the next read cell data Ds3 is [00000001], the byte designating signals S1, S2 and the gate signal G are
It becomes high level T time after the control data Dc3 is read, and returns to low level when the next cell head signal is inputted.

Therefore, the PN signal having a 2-byte width is continuously output from the PN signal generation circuit 27 24 times as shown in FIG. 7H, and the PN signal is output as shown in FIG. 7I. It is inserted into the entire information section of the cell data Ds3 and output.

Similarly, the cell data Ds1 for dummy and the cell data Ds3 in which the PN signal is inserted in the entire information portion are alternately output.

When the cell data Ds4 is read following the dummy cell data Ds1, the control data Dc4 becomes [01100111] (m = 1
9) Therefore, as shown in (e) to (g) of FIG. 7, the byte designation signal S1 and the gate signal G become high level T time after the control data Dc4 is read, and become low after (19 + 2) T time. Returning to the level, the byte designation signal S2 becomes high level T time after the control data Dc4 is read, and returns to low level after (19 + 1) T time.

Therefore, the PN signal having a 2-byte width is output 20 times continuously from the PN signal generation circuit 27 as shown in FIG. 7 (h). The data Ds4 is inserted and output up to the 39th byte from the head of the information section.

As described above, in the ATM cell test signal generating apparatus of this embodiment, control data representing the insertion start position or the insertion end position of the PN signal is added to the cell data and stored in the memory. A timing signal for inserting a PN signal into the cell data is generated based on the control data read together with the cell data from the memory, and the PN signal generated by the timing signal is inserted into the cell data and output.

For this reason, a timing data memory independent of a memory for generating cells and peripheral circuits necessary for reading and writing the same are not required, and the circuit scale can be significantly reduced. Further, the control data to be added to each cell data is 2,
Since only three bytes are required, the capacity of the entire memory can be reduced as compared with the case where the timing data is generated from the memory.

Since the control data is added so as to be included in each cell data, the control data is specified in the information section of the cell data read from the cell generation memory 21 as shown by the dotted line in FIG. In the case where the specific information is inserted by the information insertion circuit 40, the control data added to the cell data is delayed with respect to the cell data even if the data is delayed by the specific information insertion circuit 40. Therefore, there is no need to adjust the PN signal insertion timing.

[0070]

[Other Embodiments] In the above embodiment, 1-byte control data is added between the header section and the information section. However, this does not limit the present invention. Control data may be added to the middle part. Further, if the control data is 2 bytes or more, for example, the insertion start position and the insertion end position of the PN signal can be arbitrarily specified for one cell data, and the above described AAL2 to AAL4 can be easily handled. be able to. Even in this case, by making the control data have an odd-byte length, it is possible to use an easily available and inexpensive 16-bit width memory.

In the above-described embodiment, the cell data with the control data added is stored in the cell generation memory 21 having the data width of 2 bytes. However, the control data is added to the memory having the data width of 1 byte. Cell data may be stored. In this case, PN
The signal generation circuit is also configured to output the PN signal in units of 1 byte, and the control circuit outputs only the gate signal G to the PN signal generation circuit and the PN signal insertion circuit, and outputs the cell data output in units of 1 byte. To insert a PN signal. In this case, the demultiplexer 29 can be omitted.

In the above embodiment, 1 byte of control data is added to 53 bytes of cell data to obtain 54 bytes of cell data.
After the PN signal was inserted and the control data was removed to return to the 53-byte configuration,
When using cell data having a region for inserting specific information at a position (header of a header portion or an information portion) before the region where the N signal is inserted, as the test signal, the cell data for inserting the specific information is used. Even if control data is inserted in the area, timing data is generated based on the control data extracted from the area, a PN signal is inserted, and specific information is overwritten in the area where the control data is inserted. Good. In this case, the cell data can be handled with the length of 53 bytes, and the control data removing circuit is not required. This method is particularly effective when inserting a PN signal generated with a 1-byte width into cell data read with a 1-byte width as described above.

[0073]

As described above, the ATM cell test signal generating apparatus of the present invention adds control data representing a desired position for inserting a PN signal to a cell data to a cell data and stores the control data in a memory. A timing signal for inserting a PN signal into the cell data is generated based on the control data read together with the cell data from the memory, and the PN signal generated by the timing signal is inserted into the cell data and output. ing.

Therefore, a timing data memory independent of a memory for generating cells and a peripheral circuit necessary for reading and writing the memory are not required, so that the circuit scale can be significantly reduced. As compared with, the capacity of the entire memory can be reduced.

When the specific information is inserted into the information section before the PN signal is inserted, the control data added to the cell data is not affected even if the data is delayed by the specific information insertion section. Since there is no delay for the cell data, there is no need to adjust the insertion timing of the PN signal.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing contents of data stored in a cell generation memory;

FIG. 3 is a diagram showing an example of control data added to cell data.

FIG. 4 is a diagram showing an example of control data added to cell data.

FIG. 5 is a diagram for explaining the operation of the main part of the embodiment;

FIG. 6 is a timing chart for explaining the operation of the embodiment;

FIG. 7 is a timing chart for explaining the operation of the embodiment;

FIG. 8 is a block diagram showing the configuration of a conventional device.

FIG. 9 is a diagram showing data in a memory of the conventional device of FIG. 8;

FIG. 10 is a timing chart for explaining the operation of the conventional device of FIG. 8;

[Explanation of symbols]

 Reference Signs List 21 memory for cell generation 22 data writing circuit 23 cell data reading circuit 25 control data extraction circuit 26 control circuit 27 PN signal generation circuit 28 PN signal insertion circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04L 12/28 H04L 12/26

Claims (1)

(57) [Claims] An ATM cell test signal generator for inserting and outputting a pseudo-random signal at a desired position in cell data for each cell data, for inserting a pseudo-random signal at a specified desired position. A cell data storage means (21) for storing cell data added with control data indicating the desired position by a numerical value; and a cell data reading means (23) for reading cell data stored in the cell data storage means. ), Control data extracting means (25) for extracting the control data from the cell data read by the cell data reading means, and receiving the extracted control data, based on a numerical value indicated by the control data, Control means (26) for generating and outputting a timing signal corresponding to the desired position
A pseudo-random signal generating means (27) for generating a pseudo-random signal in response to a timing signal output from the control means; and converting the pseudo-random signal to a desired one of the cell data to which the control data has been added. An ATM cell test signal generator comprising pseudo-random signal insertion means (28) inserted at a position.