JP3664932B2 - Register access system for ATM communication - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a register access system in ATM (Asynchronous Transfer Mode) communication, and more particularly to an access system for register test of a physical layer (PHY layer) device incorporated in an ATM switch.
[0002]
[Prior art]
In a conventional ATM exchange, when converting reception frame data to reception cell data or conversion of transmission cell data to transmission frame data, various layers (AAL, ATM, A PHY layer device that forms a lowermost layer among PHY layers) is used. At that time, in order to be able to connect to any of the external CPUs in order to transmit / receive data and control signals between the external CPU and the internal register of the device, that is, to perform register access, Two types of bus modes 1 and 0 determined by the form and type are defined (standardized) in the international forum ("The ATM Forum").
[0003]
FIG. 9 is a block diagram of an ATM PHY layer device for explaining an example of the prior art. As shown in FIG. 9, an ATM exchange for connecting lines and terminals (or between lines and terminals) or various devices mounted on the ATM exchange, for example, an ATM PHY layer device 30, is connected to an external CPU 31. A data bus D1, an address bus (hereinafter simply referred to as an address) AD1, and a control signal line (hereinafter simply referred to as a control signal) C1 for transferring a control signal to the device 30. Connected and writes data to a register in the device or reads data from this register.
[0004]
This device 30 shows a case where there is one part (port) 32 for processing received data and transmission data, and is an example mounted on a relatively small capacity ATM switch. Further, the device 30 includes interfaces (IF) 33 and 34 for connecting to lines and terminals, and an interface (IF) 35 for connecting to the external CPU 31, and the frame configuration and signal format are matched. It has a function. Further, as described above, the port 32 includes the reception data processing unit 36 for decomposing the reception frame data from the line side into reception ATM cell data, and the transmission ATM cell data from the terminal side as a transmission frame. A transmission data processing unit 37 to be assembled into data, and a register unit 38 for performing data access with the external CPU 31 using the external CPU interface 35, the data bus D2, and the control signal C2. The control signal C2 is normally formed from a read / write signal, a register selection signal, a data selection signal, and the like.
[0005]
FIG. 10 is a block diagram of an ATM PHY layer device for explaining another conventional example. The ATM PHY layer device 30 is basically the same as the device of FIG. 9 described above, but shows a case where there are four ports 32A to 32D and is an example mounted on a relatively large capacity ATM switch. is there. Each of these ports 32A to 32D is composed of a reception data processing unit 36, a transmission data processing unit 37, and a register unit 38, like the port 32 described in FIG. Data access is performed by the bus D2 and the control signal C2.
[0006]
In the following, the register access of the device 30 in FIGS. 9 and 10 will be described with reference to FIGS. 11 and 12 and write / read operations in bus modes 1 and 0. FIG.
[0007]
FIGS. 11A and 11B are timing diagrams for explaining the write access and read access operations in the bus mode 1 in FIGS. 9 and 10, respectively. First, as shown in FIG. 11A, in the write access in the bus mode 1, 8000 frames are transmitted per second (especially at an SDH (synchronous digital hierarchy) -based transmission rate). Therefore, the transfer time of one address signal AD1 transferred between the CPU 31 and the IF 35 is also determined to be minimum (min) 64 nsec. This transfer time of 64 nsec for the address signal AD1 is the order of the support frame such as support frame STS-1 (synchronous transfer signal-level 1) or STS-3 (three STS-1 bundles). Regardless, it is fixed as absolute time. For this reason, the data select signal Sel, the write signal Wr, and the read signal Rd that form the internal control signal C2 are also restricted so as to be within them. The write signal Wr in this write access is set to 50 nsec as a write time from the CPU 31 to the register unit 38, and 10 nsec and 4 nsec are provided as write guarantee times before and after that, respectively. Data Data is data written from the CPU 31 to the register unit 38.
[0008]
In such register access, writing / reading is determined using the logic of the signals Sel, Wr, and Rd. Finally, when the writing from the CPU 31 to the register unit 38 is completed, that is, when the write access is completed, a write end signal Rdy is returned from the register unit 38 to the CPU 31.
[0009]
As described above, the conventional register access is not performed continuously, but is performed at an arbitrary timing from the CPU. Therefore, about 1953 times (125 μsec / 64 nsec) are accessed in the transmission time of one frame of transmission / reception data. Is possible.
[0010]
Next, as shown in FIG. 11B, in the read access in the bus mode 1, the read signal Rd is also set to 50 nsec as the read time from the CPU 31 to the register unit 38, and read before and after that is guaranteed. 10 nsec and 4 nsec are provided as times, respectively, and a ready signal Rdy as a read access end signal is returned. Also in this case, the register access is determined by writing / reading using the logic of the signals Sel, Wr, and Rd, and about 1953 times of register access is possible in the transmission time of one frame like the write access.
[0011]
FIGS. 12A and 12B are timing charts for explaining the write access and read access operations in the bus mode 0 in FIGS. 9 and 10, respectively. As shown in FIGS. 12A and 12B, the write access and read access operations in the bus mode 0 are basically the same as those in FIGS. 11A and 11B. That is, DS is used only as a read signal and Dtack is used as a ready signal, and the same is true in that about 1953 register accesses are performed. Note that when writing / reading to / from the register unit 38 is determined, the logic of the signals Sel, DS, and R / W is used.
[0012]
In any case, the register access method from the external CPU in the conventional ATM PHY layer is defined in the bus forum 1 and bus mode 0 in the international forum, and the time required for one register access is The minimum is defined by AC characteristics of 64 nsec. Therefore, the access time is an absolute value, and the number of register accesses that can be performed in the processing unit time (125 μsec) is fixed.
[0013]
In the conventional register access test, the register access data is directly transmitted and received between the external CPU and the register in both FIG. 9 and FIG.
[0014]
[Problems to be solved by the invention]
The above-described conventional register access system can be used in a unit time even in a support frame having a lower order such as STS-1 or STS-3 or in a support frame having a higher order than STS-12. Since the number of accesses is fixed, when the number of registers and the number of ports increase, there is a disadvantage that the entire register access test time becomes long.
[0015]
That is, in the conventional register access method in a one-port device, when an access test for all registers is performed, the access test time for all registers is the number of test items (depending on the number of registers) × one minimum register access time Only needed. For this reason, in the case of a device having a plurality of ports, the access test time for all the registers requires the number of test items (depending on the number of registers) × one minimum register access time × the number of ports.
[0016]
As described above, a conventional ATM PHY layer device generally has one port or four ports, and in the case of a device having a plurality of ports, a communication path corresponding to the number of ports is formed. However, the number of registers increases accordingly.
[0017]
For this reason, when the number of registers and the number of ports increase as the support frame becomes higher, an increase in register access test time is unavoidable.
[0018]
Further, the conventional register access system has a drawback that the test method itself becomes complicated because the register unit is tested by transmitting / receiving data, address, and control signals to / from the CPU.
[0019]
An object of the present invention is to provide a register access system in ATM communication that can shorten the test time for register access in a higher-order support frame and can facilitate the test method.
[0020]
[Means for Solving the Problems]
A register access system in ATM communication of the present invention comprises a register unit, a reception data processing unit, and a transmission data processing unit, and a payload of received frame data in a physical layer device that converts frame data and cell data. A bus extraction control unit that extracts write / read access data from the area to the register unit, and stores address data from the bus extraction control unit and read data from the register unit based on access timing A bus insertion control unit that inserts into the transmission frame data unit from the transmission data processing unit, and the path between the external CPU and the register unit is routed by the test mode signal to the bus extraction control unit and the register Switch to the path to the register and write to the register at high speed Configured to perform reading.
[0021]
Further, the bus extraction control unit according to the present invention includes a register access control unit stored in a payload area of the reception frame data based on a plurality of timing signals corresponding to the reception clock transmitted from the reception data processing unit. Data is extracted, and at the time of write access, write data, data select signal, register select signal and write / read signal are created and transmitted from the register access data, and the bus insertion control is performed. The non-access result insertion timing signal is sent to the unit, while in the case of read access, a data select signal, a register select signal and a write / read signal for the register are created and sent from the register access data. And said Address data to the scan insertion control unit, are formed so as to deliver the read access results insertion timing signal.
[0022]
Further, the bus insertion control unit according to the present invention includes an address data from the bus extraction control unit, a read access result insertion timing signal and a non access result insertion timing signal, a reception overhead area signal from the reception data processing unit, In addition to inputting read data from the register unit, register access to the transmission frame data unit from the transmission data processing unit based on a plurality of timing signals and transmission overhead area signals from the transmission data processing unit By inserting the result data, it is configured to output as transmission frame data.
[0023]
The frame data according to the present invention is formed so as to store register access data including a read / write code area, an address area, and a data area in the payload area.
[0024]
The bus insertion control unit according to the present invention stores the address data from the bus extraction control unit and the read data read from the register unit based on the read access result insertion timing signal and the non access result insertion timing signal. An access result data storage block, a first overhead data storage buffer for storing the output of the read access result data storage block by a first buffer storage timing signal and a reception overhead area signal, and the first overhead data A data storage buffer for a second overhead storing the output of the data storage buffer by a second buffer storage timing signal and the reception overhead area signal, and outputs of the data storage buffers for the first and second overheads Register access result data insertion to be inserted based on the transmission overhead area signal, the first and second register access result data insertion timing signals, and the reception overhead area signal to the transmission frame data section from the reception data processing section Part.
[0025]
Furthermore, the bus insertion control unit according to the present invention forms the second overhead data storage buffer with the number of stages based on the order of the support frame.
[0026]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings.
[0027]
FIG. 1 is a circuit diagram of an ATM PHY layer device for explaining an embodiment of the present invention. As shown in FIG. 1, in this embodiment, for register test, high-speed write / read access to internal registers is performed using the payload (user information) area of the frame data of the ATM PHY layer. Is realized.
[0028]
First, as shown in FIG. 1, an ATM switch for connecting lines and terminals (or between lines and terminals) or each device mounted in the ATM switch, for example, a PHY layer device 1 for ATM is externally connected. Connected by the data bus D1, the address AD1, and the control signal C1 for transferring data to and from the CPU 2, the frame data is decomposed into cell data, and the cell data is assembled into frame data. Also, data is written to the register for setting inside the device, or data is read from the register to obtain device internal information.
[0029]
This device 1 shows a case where there is one part (port) 3 for processing received data and transmission data, and is an example mounted on a relatively small capacity ATM switch. The device 1 also includes interfaces (IF) 4 and 5 for connecting to lines and terminals, and an interface (IF) 6 for connecting to the external CPU 2, and the frame configuration and signal format are matched. It has a function. Further, as described above, the port 3 receives the received frame data from the line side or the like into the received ATM cell data, and receives the register access data from the received frame data from the IF 4. A reception block 7 having a bus extraction control unit 12 for extraction, a transmission data processing unit 14 for assembling transmission ATM cell data from the terminal side into transmission frame data, and registers for transmission data to the line side When sending output data of the bus insertion control unit 13 for inserting access data, the transmission data processing unit 14 and the bus insertion control unit 13 as frame data to the line side, it is based on a test mode (TM) signal. A transmission block 8 having a selector 15 for switching, an external CPU interface 6 and a reception block 7; The data and control signal transferred from the source extraction control unit 12 are switched based on the TM signal, and the data switched by the selector 9 are written, while the data is sent to the bus insertion control unit 13 or the selector 9 of the transmission block 8 And a register unit 10 to be read.
[0030]
Here, the data bus D2, the address AD1, and the control signal C from the external CPU 2 are converted by the external CPU interface 6 and transferred to the selector 9, the data bus D2, the data select signal DS1, the register select signal RS1, and the read. The / write signal RW1 is the same as that of the conventional example shown in FIGS.
[0031]
The bus extraction control unit 12 in the present embodiment receives a signal based on a code check timing signal T1, a register check timing signal T2, and a data check timing signal T3 which are timing signals from the reception data processing unit 11. Write data WD, data select signal DS2, register select signal RS2, and read / write signal RW2 as register access data are extracted from the payload area of the frame data. In addition, the bus extraction control unit 12 extracts address data from the received frame data and inserts it into the transmission frame data to the selector 15, so that the address data AD2, read access result insertion timing signal RAT, non-access The result insertion timing signal NAT is sent to the transmission block 8, and the reception overhead area signal T 4 is sent from the reception data processing unit 11 of the reception block 7 to the transmission block 8. Therefore, in the normal operation, the register unit 10 is written / read by the data select signal DS1, the register select signal RS1, the read / write signal RW1 and the data bus D2, but in the test mode, Writing is performed by the data select signal DS2, the register select signal RS2, the read / write signal RW2, and the write data WD, while the read data RD from the register 10 is read to the transmission block 8.
[0032]
On the other hand, the bus insertion control unit 13 includes first and second buffer storage timing signals T5 and T6 which are timing signals from the transmission data processing unit 14, and first and second register access result data insertion timing signals T7. And T8, a transmission overhead area signal T9, a reception overhead area signal T4 from the reception data processing section 11, and a read access result insertion timing signal RAT and a non access result insertion timing signal NAT from the bus control section 12. The address data AD2 and the read data RD from the bus extraction control unit 12 are inserted into the payload area of the transmission frame data (data before insertion of access result) SD. For this reason, in normal operation in the transmission block 8, transmission ATM cell data is transmitted as transmission frame data from the transmission data processing unit 14 to the line side via the selector 15, but in the test mode using the TM signal, In the write access, non-access data is sent to the line side, and in the read access, the read signal RD and address data AD2 read from the register unit 10 are inserted (mapped) into the transmission frame data SD before the access result is inserted, Sent to the line side.
[0033]
The selector 9 switches data and control signals during normal operation and test mode according to the TM signal. Similarly, the selector 15 uses the TM signal to output data during normal operation, that is, the output of the transmission data processing unit 14 that assembles transmission ATM cell data, and data during test mode, that is, register access data on the transmission side ( The frame data to which the read data) is mapped are switched.
[0034]
Note that the register unit 10 has the same configuration as the conventional one, and in normal operation, data and control signals are transferred to and from the selector 9 for both write / read access, but in the test mode, read data RD is inserted into the bus. The data is sent to the control unit 13.
[0035]
FIGS. 2A to 2C are a frame configuration diagram, an SPE configuration diagram, and a register access data configuration diagram in the case of STS-1 in the ATM frame data transmitted and received in FIG.
[0036]
First, as shown in FIG. 2A, this frame configuration is a transformer prepared for 3 bytes for displaying information (A1, A2,..., H1, H2, etc.) for network operation / management. The port overhead unit 20 and an STS-1 envelope area 21 prepared for 87 bytes for accommodating the contents of the cell are formed (90 bytes in the whole frame). Nine columns of the overhead section 20 and the envelope area 21 are provided, and in order to transmit or receive one frame data, a time of 125 μsec is required as described above.
[0037]
As shown in FIG. 2B, the synchronous payload envelope (SPE) 21a mapped to the envelope area 21 is a path overhead (POH) unit 22 representing a 1-byte path (J1) connection destination. And a payload area 23 for 84 bytes secured as user information and an FS unit 25. The payload area 23 has a payload capacity of 756 bytes [= (87-3) × 9 bytes] and contains normal cell data. In the present embodiment, the register access data described above is used here. (3 bytes) 24 is stored. The FS unit 25 is a fixed stuff area for speed adjustment, which is provided for one byte and is arranged between the payload areas 23, similarly to the POH unit 22.
[0038]
Further, as shown in FIG. 2C, the 3-byte register access data 24 includes an RW code area (2 bits) composed of code information such as writing and reading, and an address for designating the address of the register unit 10. An area (10 bits) and a data area (12 bits) for storing data in the register unit 10 or storing read data are formed. These 10 bits of address and 12 bits of data are expanded inside the PHY layer device 1, that is, inside the interface IF4 and port, and outside the interface IF4, that is, for the line, based on the line specifications. Converted to a bit.
[0039]
As described above, the frame data payload area 23 of the normal ATM PHY layer device 1 carries 53 bytes of ATM cell data consisting of a 5-byte header part and 48-byte information for transfer. In this embodiment, 3-byte register access data 24 is mapped here instead of such data.
[0040]
For example, '01' in the RW code area arranged in the MSB (D23, D22) of the register access data 24 (other than '01' if the value is different from the read code: write code, non code) Is specified, address data is specified in the address area (D21 to D12), and read data is specified in the data area (D11 to D0). Read access is performed to the target register of the register unit 10 using the address data. However, the value of the read data specified in the data area at this time is ignored. On the other hand, on the transmission side, that is, the transmission block 8, the result of the read access performed on the reception side is displayed.
[0041]
Also, '10' (write code: read code, other than '10' as long as the value is different) is specified in this RW code area, address / data is stored in the address area, and data area is also stored in the data area. When write data is specified when the write code is recognized on the receiving side, write access is performed to the target register of the register unit 10 using the address data in the address area. On the other hand, the write code is not output on the transmission side. In other words, considering access from the CPU, in the case of write access, the write code is not output even in such a register access system, just as there is no data returned to the CPU. However, since frame data is used, some data must be mapped and non-access data is output.
[0042]
Further, when “00” (non-code: read code, other than “00” is acceptable if the value is different from the write code) is specified in the RW code area (the address area and the data area are both ignored). When the non-code is recognized on the receiving side, it indicates that the register unit 10 is not accessed, and similarly, the transmitting side does not perform read or write access to the register unit 10.
[0043]
However, the data length in the above-described register access can be changed depending on the register address and the data amount.
[0044]
As described above, in the operation of the PHY layer device 1, the frame data in which the register access data 24 is mapped is input from the receiving side, and the register unit 10 is accessed. Further, for the read access of the register unit 10, the frame data in which the register access data 24 fetching the read access result RD is mapped is output from the transmission side.
[0045]
In the case of the support frame STS-1 (one port) in the PHY layer device 1 described above, the number of register accesses in one frame (125 μsec) is [{(1 × 87 bytes−3 bytes) × 9 columns} × 1. Port] ÷ 3 (bytes), so 252 times. In the case of 4 ports in STS-1, the number is 1008 times 4 times.
[0046]
Here, since one register access time is 3 bytes, the number of accesses within the same time (125 μsec) is smaller than the conventional number (1953), but the received frame data and clock Since the test can be performed simply by inputting, the test method is simplified.
[0047]
FIGS. 3A to 3C are a frame configuration diagram, an SPE configuration diagram, and a register access data configuration diagram in the case of STS-N in the ATM frame data transmitted and received in FIG.
[0048]
As shown in FIGS. 3A to 3C, the frame configuration of the STS-N (N = 3X X = 1, 2, 3,...) Is basically the same as that shown in FIGS. ). For example, STS-3 (three STS-1), STS-12 (four STS-3), STS-48 (four STS-12), STS-96 (two STS-48) In a typical higher-order frame configuration, the number of bytes in the transport overhead unit 20 and the STS-N envelope area 21 in FIG. The only difference between the STS-Ns is that in FIG. 3B, a (N / 3) -1 byte FS area 25 is added to a part of the SPE 21a. As shown in FIG. 3C, the register access data 24 is exactly the same.
[0049]
In the case of the above-described PHY support frame STS-3 (one port), the number of register accesses in one frame is obtained by determining the data amount (bytes) of the payload portion 23 in one port, multiplying the number of ports, Divide by register access time times to get the number of accesses. In other words, [{(3 × 87 bytes−3 / 3 bytes) × 9 columns} × 1 port] ÷ 3 (bytes) gives 780 times. In the case of 4 ports in STS-3, 4 times 3120 times.
[0050]
Further, the number of register accesses in one frame in the case of the support frame STS-12 (1 port) is [{(12 × 87 bytes−12 / 3 bytes) × 9 columns} × 1 port] ÷ 3 (bytes) Therefore, it is 3120 times, and in the case of 4 ports in STS-12, it is 12480 times, which is 4 times.
[0051]
Similarly, in the case of the support frame STS-48 (1 port), the number of register accesses in one frame is [{(48 × 87 bytes−48 / 3 bytes) × 9 columns} × 1 port] ÷ 3 (bytes). ), It is 12480 times, and in the case of 4 ports in STS-48, it is 49920 times 4 times. In the case of the support frame STS-96 (1 port), the number of register accesses in one frame is [{(96 × 87 bytes−96 / 3 bytes) × 9 columns} × 1 port] ÷ 3 (bytes). Thus, 24960 times, and in the case of 4 ports in STS-96, the number is 99840 times 4 times.
[0052]
In any case, the number of accesses when there are 4 ports or more in the support frame STS-3 or 1 port or more in the support frame STS-12 exceeds the conventional fixed 1953 times. This means that the number of items that can be tested within the same time increases, that is, the test time for one test is relatively shortened, and the higher the support frame STS-N is, the more marked it becomes. Become.
[0053]
FIG. 4 is a block diagram of the bus insertion control unit shown in FIG. As shown in FIG. 4, the bus insertion control unit 13 converts the 10-bit address data AD2 and the 12-bit read data RD from the register unit 10 into a 2-bit read access result insertion timing signal RAT or non-access. A read access result data storage block 26 to be stored in response to the result insertion timing signal NAT, and a 24-bit output of the data storage block 26 are input, and the first bit is stored based on the reception overhead area signal T4 and the first buffer storage timing signal T5. A data storage buffer 27 for the first overhead for storing data for one overhead, and a 24-bit output of the data storage buffer 27 is input in the same manner as this buffer 27, and a reception overhead area signal T4 and a second buffer are input. Storage timing The second overhead data storage buffer 28 for storing the second overhead data based on the signal T6 and the 24-bit outputs of the first and second overhead data storage buffers 27 and 28 are input. On the basis of the reception overhead area signal T4, the first and second register access result data insertion timing signals T7 and T8, and the transmission overhead area signal T9, the data is converted into the register access result data and the 8-bit register A register access result data insertion unit 29 for inserting the register access result data into the transmission frame data unit SD before the insertion of the access data, converting it to 8 bits and outputting it to the selector 15 is provided. Here, the reason why the data storage buffers 27 and 28 are provided in two stages is that the transmission side and the reception side in the ATM communication are communicated asynchronously. That is, in order to absorb a phase difference in transmission and reception, such a two-stage buffer configuration is adopted.
[0054]
With this configuration, the bus insertion control unit 13 of the transmission block 8 develops the address data AD2 transferred from the bus extraction control unit 12 of the reception block 7 and the read data RD from the register unit 10, and the transmission data processing unit 14 is inserted as overhead data in the transmission frame data portion SD received from 14, a transmission format similar to that of normal transmission frame data can be realized. As a result, the format of the frame data can be made the same in the normal operation and in the test mode, so that the test method can be simplified.
[0055]
When the read access result data storage block 26 of the bus insertion control unit 13 stores the address data AD2 and the read data RD, if the read access result insertion timing signal RAT is active, the read code is reversed. When the access result insertion timing signal NAT is active, the non code is stored in the MSB 2 bit of the RW code area.
[0056]
Further, the data storage buffer 28 corresponding to the second overhead of the bus insertion control unit 13 is shown here as one stage (in the case of STS-1), but is generally (α-1) stages. That is, α = 2 in the case of STS-1, and α = (N × 3 + N / 3) ÷ 3 in the case of STS-N (N = 3X X = 1, 2, 3,...). The quotient is [1 when the remainder is left].
[0057]
FIG. 5 is a timing chart of various data and signals for explaining the circuit operation of the bus insertion control unit shown in FIG. As shown in FIG. 5, at time t1, a low-active reset signal (the device is initialized when low and the device operates when high) is input, and the data storage buffer 27 and register access for the first overhead are input. When the result data insertion unit 29 is reset, the first buffer storage timing signal T5 becomes active and the first register access result data insertion timing signal T7 rises, and the register frame is transmitted as transmission frame data to the selector 15. Access data is output. In the case of a hard reset in which a reset signal is given from the outside via a device terminal, the test mode setting must be a terminal. The reason is that it is initialized by setting in the register. On the other hand, in the case of soft reset, it is necessary to configure so that the test mode setting in the register is not initialized.
[0058]
Next, when the reception overhead area signal T4 is transmitted from the reception data processing unit 11 of the reception block 7 to the data storage buffer 27 for the first overhead at time t2, the data storage buffer 27 for the first overhead A predetermined (t4-t2) storage stop period STP is set.
[0059]
Next, at time t3, when the transmission overhead area signal T9 to the register access result data insertion unit 29 becomes active for a predetermined period (t5-t3), overhead data as transmission frame data SD is input and 2 buffer storage timing signal T6 becomes active and the first register access result data insertion timing signal T7 falls. As a result, the register access result data insertion unit 29 outputs overhead data instead of the register access data. Note that during a predetermined (t3-t2) non-period, non-access data is output from the storage buffer 27 and output at the rising edge of the timing signal T5 when the timing signal T4 is high. At that time, the non-access data can be output from the register access result data insertion unit 29 at t3-t2.
[0060]
Thereafter, at time t5 after time t4, the transmission overhead area signal T9 falls, and when the overhead data as the transmission frame data SD stops, the second register access result data insertion timing signal T8 rises. The transmission frame data is output after switching from overhead data to register access data.
[0061]
Thereafter, the operation similar to the operation at time t2 to t5 described above is repeated also at time t6 to t9. However, at time t9, the second register / access result data insertion timing signal T8 is used instead of the first register / access result data insertion timing signal T7. As described above, this is due to absorbing the phase difference when the transmission side and the reception side of the ATM communication are communicated asynchronously.
[0062]
Here, the details of the bus insertion control unit 13 have been described. However, the bus extraction control unit 12 is basically required only to perform an operation reverse to the operation of the bus insertion control unit 13, and the received frame data The address data is extracted from the data and written into the register unit 10 or transferred to the bus insertion control unit 13 when reading from the register unit 10.
[0063]
Hereinafter, a write / read access and a non-access operation to the register unit 10 using the frame data will be described with reference to FIG. 1 and FIGS.
[0064]
First, the mode setting of the normal operation mode or the test operation mode is performed for the PHY layer device 1. In that case, there are two types of settings: setting from an external CPU and setting from an external input terminal. In the case of setting from the external CPU 2, when the write access of the mode release code is performed from the received frame data to the target register (bit), the write / read access mode from the external CPU 2 (default) Switch to In the case of setting from the external input terminal (TM signal input in FIG. 1), the mode setting is performed directly from the external input terminal. I need a pin. In short, the selection of these setting methods is to add a corresponding bit to the register or to sacrifice one terminal as a device, but the selection may be any.
[0065]
FIG. 6 is a timing diagram of write access by register access data mapped to the reception frame data in FIG. As shown in FIG. 6, in the write access, first, in the bus control extraction unit 12 of the reception block 7, the reception frame data payload area (see FIG. 2) 23 receives a period of three reception clocks. The register access data 24 as the corresponding write access data is extracted. At this time, the code check timing signal T1, the register check timing signal T2, and the data check timing signal T3 input to the bus control extraction unit 12 are sequentially activated according to the reception clock.
[0066]
Next, after the write code is recognized from the R / W code area (D23, D22) in the register access data 24 and the read / write signal RW2 is set to the high level, the address in the register access data 24 is set. The address is recognized from the areas (D21 to D12), and the register select signal RS2 of the target register unit 10 is set to the high level.
[0067]
Further, write data WD is extracted from the data area (D11 to D0) in the register access data 24, and the write data is put on the data bus and output. At the same time, the bus extraction control unit 12 sets the data select signal DS2 to the high level and outputs it so that the selector 9 performs the write access indicated by the dotted line to the register unit 10.
[0068]
As a result, the selector 9 writes data to the register unit 10 based on these signals, but the register unit 10 performs write access to the target register at the write access timing indicated by the dotted line.
[0069]
Here, in the write access, since the access result data to the register unit 10 is not output, only the non access result insertion timing signal NAT is set to the high level from the bus extraction control unit 12 to the bus insertion control unit 13. Output. That is, in the case of this write access, the address data AD2 and the read access result insertion timing signal RAT are not output from the bus extraction control unit 12 to the bus insertion control unit 13, but the non-access result insertion timing signal NAT is output. It is output on the line.
[0070]
In short, the write address data is written in the RW code of the register access data and the write data is written in the data area, and the read access data is written in the RW code. At the same time, read data is written in the data area, and the non-access data is also ignored in both the address and data areas while the non-code is written in the RW code.
[0071]
FIG. 7 is a timing chart of read access by the register access data mapped to the reception frame data in FIG. As shown in FIG. 7, in the read access, the bus control extraction unit 12 of the reception block 7 first receives the payload area (see FIG. 2) 23 of the reception frame data for a period of three reception clocks. The register access data 24 as corresponding read access data is extracted. At this time, the code check timing signal T1, the register check timing signal T2, and the data check timing signal T3 input to the bus control extraction unit 12 are sequentially activated according to the reception clock.
[0072]
Next, after the read code is recognized from the R / W code area (D23, D22) in the register access data 24 and the read / write signal RW2 is set to the low level, the address area in the register access data 24 is set. The address is recognized from (D21 to D12), and the register select signal RS2 of the target register unit 10 is set to the high level. However, in the case of read access, the data area (D11 to D0) in the register access data 24 is ignored. The RW2 and the register select signal RS2 are selected by the selector 9 and input to the register unit 10.
[0073]
On the other hand, the bus extraction control unit 12 outputs the read address / data AD 2 and the read access result insertion timing signal RAT to the bus insertion control unit 13.
[0074]
As a result, the register unit 10 performs read access to the target register at the read access timing indicated by the dotted line, and outputs read data RD.
[0075]
Here, the bus insertion control unit 13 of the transmission block 8 takes in the read result data RD based on the read access result insertion timing signal RAT, inserts it into the payload area of the transmission frame data, and connects to the line side via the selector 15. Output to.
[0076]
FIG. 8 is a timing diagram of non-access by register access data mapped to the reception frame data in FIG. As shown in FIG. 8, for non-access, first, the bus access control unit 12 of the reception block 7 extracts the register access data 24 from the payload area of the reception frame data. At this time, the code check timing signal T1, the register check timing signal T2, and the data check timing signal T3 input to the bus control extraction unit 12 are sequentially activated according to the reception clock.
[0077]
Next, the bus extraction control unit 12 recognizes the non code from the RW code area (D23, D22) of the register access data 24 and keeps the read / write signal RW2 for the selector 9 at the low level. Similarly, in the case of non-access, since the register select signal RS2 and the data select signal DS2 for the selector 9 are also kept at the low level, the register unit 10 is not accessed. Further, the non-access result insertion timing signal NAT is output from the bus extraction control unit 12 to the bus insertion control unit 13 at a high level.
[0078]
On the other hand, the bus insertion control unit 13 of the transmission block 8 inserts the non-access result data into the payload area of the transmission frame data at the non-access timing and outputs it to the outside via the selector 15.
[0079]
As described above, according to the present embodiment, the number of test items can be increased by significantly increasing the number of register accesses within a unit time as the support frame becomes higher. Since the register access test time can be relatively shortened and the register access test can be realized by the received frame data and the received clock without using an external CPU, the test method can be simplified.
[0080]
【The invention's effect】
As described above, the register access system in the ATM communication according to the present invention has the bus extraction control unit provided in the reception block, the bus insertion control unit provided in the transmission block, and the data from the CPU by the test mode signal. 1 frame (125 μsec) of reception frame data and transmission frame data by having a first selector for switching the frame to reception frame data, a bus insertion control unit, and a second selector for switching the output of the transmission data processing unit Since the number of register accesses within a unit time can be increased, the register access test time in higher-order frames such as STS-12 can be shortened. That is, since the amount of data to be packed within a certain time can be increased, the register access test time can be relatively shortened.
[0081]
In the present invention, a register access test can be performed by providing a bus insertion control unit and a second selector in a transmission block and using received frame data and a clock. Compared to the above, there is an effect that the test method can be simplified. Further, according to the present invention, when there are a plurality of ports, a plurality of ports can be tested at the same time, and by making the received frame data the same, the output result of the transmitted frame data becomes the same, and the test method is easy. Can be.
[0082]
Accordingly, in the present invention, when testing the registers in the PHY layer device, it is possible to realize a register test that is faster and easier than before.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of an ATM PHY layer device for explaining an embodiment of the present invention;
2 is a diagram showing a frame configuration, SPE, and register access data configuration in the case of STS-1 in ATM frame data transmitted and received in FIG. 1. FIG.
FIG. 3 is a diagram showing a frame configuration, SPE, and register access data configuration in the case of STS-N in ATM frame data transmitted and received in FIG. 1;
4 is a block configuration diagram of a bus insertion control unit shown in FIG. 1. FIG.
FIG. 5 is a timing chart of various data and signals for explaining the circuit operation of the bus insertion control unit shown in FIG. 4;
FIG. 6 is a timing diagram of write access by register access data mapped to the reception frame data in FIG. 1;
FIG. 7 is a timing diagram of read access by register access data mapped to the reception frame data in FIG. 1;
FIG. 8 is a timing chart of non-access by register access data mapped to the reception frame data in FIG. 1;
FIG. 9 is a block diagram of an ATM PHY layer device for explaining an example of the prior art.
FIG. 10 is a block diagram of an ATM PHY layer device for explaining another conventional example.
11 is a timing chart for explaining a write access and a read access operation in the bus mode 1 in FIGS. 9 and 10. FIG.
12 is a timing chart for explaining write access and read access operations in the bus mode 0 in FIGS. 9 and 10. FIG.
[Explanation of symbols]
1 Physical layer (PHY layer) device
2 CPU
3 ports
4-6 interface (IF)
7 Reception block
8 Transmission block
9 Selector
10 Register section
11 Received data processing section
12 Bus extraction control unit
13 Bus insertion controller
14 Transmission data processing section
15 selector
20 Transport overhead section
21 Envelope area
21a SPE (Synchronous Payload Envelope)
22 POH part (payload overhead part)
23 Payload area (user information area)
24 Register access data
25 FS Department
26 Read access result data storage block
27, 28 Overhead data storage buffer
29 Register access result data insertion part
D1, D2 data (bus)
AD1, AD2 address
C Control signal
DS1, DS2 Data select signal
RS1, RS2 register select signal
RW1, RW2 read / write signal
WD write data
RD read data
Transmission frame data before SD register access data insertion
RAT read access result insertion timing signal
NAT non access result insertion timing signal
T1 code check timing signal
T2 register check timing signal
T3 Data check timing signal
T4 reception overhead area signal
T5, T6 buffer storage timing signal
T7, T8 Register access result data insertion timing signal
T9 Transmission overhead area signal
TM signal Test mode signal

Claims (6)

Write / read access data from the payload area of received frame data to the register section in a physical layer device that includes a register section, a received data processing section, and a transmission data processing section and converts frame data and cell data A bus extraction control unit that extracts the address data from the bus extraction control unit and read data from the register unit based on access timing, and a transmission frame data unit from the transmission data processing unit And a bus insertion control unit for inserting the path between the external CPU and the register unit to a path between the bus extraction control unit and the register unit by a test mode signal. Cash register in ATM communication characterized by executing high-speed writing / reading Data access system. The bus extraction control unit extracts register access data stored in a payload area of the received frame data based on a plurality of timing signals corresponding to a reception clock transmitted from the reception data processing unit. At the time of write access, write data, a data select signal, a register select signal and a write / read signal are created and transmitted to the register from the register access data and sent to the bus insertion control unit. While a non-access result insertion timing signal is sent, in the case of read access, a data select signal, a register select signal, and a write / read signal for the register are created and sent from the register access data. In the bus insertion controller Register access system in ATM communication according to claim 1, wherein sending the address data, the read access results insertion timing signals. The bus insertion control unit includes an address / data from the bus extraction control unit, a read access result insertion timing signal and a non access result insertion timing signal, a reception overhead area signal from the reception data processing unit, and a register unit. Read data, and register access result data is inserted into the transmission frame data section from the transmission data processing section based on a plurality of timing signals and transmission overhead area signals from the transmission data processing section. The register access system in ATM communication according to claim 1, wherein the frame is output as transmission frame data. 2. The register access system in ATM communication according to claim 1, wherein the frame data stores register access data including a read / write code area, an address area, and a data area in the payload area. The bus insertion control unit stores the read access result data storing the address data from the bus extraction control unit and the read data read from the register unit based on the read access result insertion timing signal and the non access result insertion timing signal A first overhead data storage buffer for storing an output of the read access result data storage block by a first buffer storage timing signal and a reception overhead area signal; and a data storage buffer for the first overhead A second overhead data storage buffer for storing an output by a second buffer storage timing signal and the reception overhead area signal, and an output of the first and second overhead data storage buffer for the transmission data processing unit Are formed by a transmission overhead area signal, first and second register access result data insertion timing signals, and a register access result data insertion section inserted based on the reception overhead area signal. The register access system in ATM communication according to claim 1. 6. The register access system in ATM communication according to claim 5, wherein the bus insertion control unit forms the second overhead data storage buffer with the number of stages based on the order of the support frame.

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