KR100426666B1 - Method and Apparatus for Cell Transfer in Cell Unit Communication System - Google Patents

Abstract

The present invention relates to a cell delivery method and apparatus in a cell-by-cell communication system.

In the cell transfer apparatus of the conventional cell-based communication system, if the write address and the read address are not applied to the DPRAM at the same time, the data transfer is performed without data overlapping when performing data write and read on the DPRAM. When the write address and the read address are applied to the DPRAM at the same time and the address being written at the data input terminal is read at the data output terminal at the same time, the address overlap is not performed when performing data writing and reading on the DPRAM. Therefore, there is a problem in that data loss occurs during data transfer through the DPRAM.

In the present invention, when data is transferred through the DPRAM in units of cells, the write address is delayed and applied to the DPRAM at the same time that data write and read operations are performed at the same address, thereby preventing collision between write and read addresses for the DPRAM. The loss of cell data is prevented.

Description

Method and apparatus for cell transfer in cell-based communication system {Method and Apparatus for Cell Transfer in Cell Unit Communication System}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an Asynchronous Transfer Mode (ATM) switching system. In particular, when data is transferred cell-by-cell via DPRAM (Dual Port RAM), loss of cell data is prevented by preventing collision of write and read addresses to the DPRAM. The present invention relates to a cell delivery method and apparatus in a cell-by-cell communication system.

In general, in a cell-based communication system, a cell is asynchronously transferred through DPRAM. The DPRAM includes two ports, and when a cell is stored through one port, the corresponding port is stored through another port. Pass cells by reading them.

As shown in FIG. 1, the cell transfer device of the conventional cell-based communication system includes a data recording unit 1, a DPRAM 2, a data reading unit 3, a write address / control signal generating unit 4, and a reading unit. The address / control signal generator 5 is provided. The data recording unit 1 outputs the applied data to the DPRAM 2 side, and also outputs write control information such as a write address, a write enable signal, and a write clock to the write address / control signal generator 4 side. . The write address / control signal generator 4 generates a write clock WCLK, a write enable signal WREN, and a write address WADDR according to the write control information received from the data recording unit 1, and generates a DPRAM (2). ), The data write operation of the DPRAM 2 is controlled. On the other hand, the data reading section 3 outputs read control information such as an applied read address, read enable signal, and read clock to the read address / control signal generator 5 side, and reads from the DPRAM 2. Collect and forward the data. The read address / control signal generator 5 generates a read clock RCLK, a read enable signal RDEN, and a read address RADDR according to the read control information applied from the data read unit 3 to generate a DPRAM ( The data read operation to the DPRAM 2 is controlled by applying to 2). Then, the DPRAM 2 writes the data applied from the data recording unit 1 to the write clock WCLK, the write enable signal WREN, and the write address WADDR received from the write address / control signal generator 4. In accordance with the read clock RCLK, the read enable signal RDEN, and the read address RADDR received from the read address / control signal generator 5 Output to the side.

In the data recording unit 1, data of one cell is continuously recorded in DPRAM (2) by byte unit starting from address 0. When the recording of the corresponding one cell is finished, the next cell starts from address 0 and is in byte unit. The cell is repeatedly recorded in the DPRAM 2 in the manner of writing. In addition, the data reading unit 3 also reads data of one cell from the DPRAM 2 continuously in byte units starting from address 0, and when reading of the corresponding one cell is finished, the next cell starts from address 0. The cell is repeatedly read from the DPRAM 2 in the manner of reading in units of bytes.

In the cell transfer apparatus of the conventional cell unit communication system as described above, when the write address and the read address are unequally applied to the DPRAM 2 at the same time, data writing and reading to the DPRAM 2 is performed without address overlap. Therefore, there is no loss of data during data transfer through the DPRAM 2, but the write address and the read address are applied to the DPRAM 2 at the same time so that the address recorded at the data input terminal is read at the data output terminal at the same time. Since there is an address overlap in performing data writing and reading to the DPRAM 2, there is a problem in that data loss occurs during data transfer through the DPRAM 2.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and its object is to prevent cell data loss by preventing collision of write and read addresses to DPRAM when data is transferred cell by cell through DPRAM. A cell delivery method and apparatus in a cell-based communication system are provided.

1 is a block diagram of a cell transfer device in a conventional cell-based communication system.

2 is a block diagram of a cell delivery device of a cell-based communication system according to the present invention;

3 is a configuration diagram of a delay selector shown in FIG. 2;

4 is a write / read timing diagram for explaining the operation of the cell transfer apparatus according to the present invention;

5 is a flowchart illustrating a delay mode determination process in a delay selection unit.

Explanation of symbols on the main parts of the drawings

11: data recorder 12: DPRAM

13 data reading section 14 writing address / control signal generating section

15: read address / control signal generator 16: delay selector

17: record reference window generator 18: read reference window generator

19: comparison judgment unit

A characteristic feature of the present invention for achieving the above object is a data recording unit for applying data to a DPRAM and recording data, and transferring a write address, a write enable signal, and write control information including a write clock on an approved address map. A write address / control signal generator for generating a write address, a write enable signal, a write clock signal corresponding to the write clock, a write enable signal, and a write address to the DPRAM; A data reading unit for reading data from the DPRAM and transferring read control information including a read address, a read enable signal, and a read clock on an applied address map, a read address in the read control information, and a read enable signal; And generate a corresponding read clock, read enable signal, and read address according to the read clock. A cell transfer device in a cell unit communication system having a read address / control signal generation section for applying to the DPRAM, the write address in the write control information, the read address in the read control information, and an applied check clock. And a delay selector for determining whether or not to set a delay mode and outputting a delay signal to delay the output of the write address to the DPRAM by the write address / control signal generator; The delay selector may include a write reference window generator for generating and outputting a write reference window signal having a predetermined state according to the applied write address and check clock, and a read reference window having a predetermined state according to the applied read address and check clock. The read reference window generator for generating and outputting a signal and the write reference window signal and the read reference window signal are compared with each other according to a check clock, and a delay mode is set when the same state is set. It includes a comparison judgment output to the.

Another aspect of the present invention provides a cell transfer method in a cell-based communication system, comprising: generating a write reference window signal according to a write address for a DPRAM; Generating a read reference window signal in accordance with a read address for the DPRAM; Checking whether the read reference window signal is equally activated while the write reference window signal is activated; As a result of the checking, if it is determined that the write reference window signal and the read reference window signal are equally activated, a delay mode is set to delay and output the write address applied to the DPRAM.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

As shown in FIG. 2, the cell transfer device in the cell-based communication system according to the present invention includes a data recording unit 11, a DPRAM 12, a data reading unit 13, a write address / control signal generating unit 14, A read address / control signal generator 15 and a delay selector 16 are provided. The data recording unit 11 outputs the applied data to the DPRAM 12 side, and records write control information such as a write address wr_addr, a write enable signal wren, and a write clock wclk on the address map. The control signal generator 14 outputs the write address wr_addr to the delay selector 16. The delay selector 16 sets the delay mode according to the write address wr_addr applied from the data recorder 11, the read address rd_addr applied from the data readout 13, and the check clock applied. It is judged whether or not the delay signal DLS is applied to the write address / control signal generator 14 side. The write address / control signal generator 14 receives write control information such as a write address wr_addr, a write enable signal wren, and a write clock wclk from the data recorder 11, and corresponds to a write clock corresponding to the write clock. wclk), a write enable signal wren, and a write address waddr are generated and applied to the DPRAM 12 to control the data write operation of the DPRAM 12, but with a delay signal applied from the delay selector 16. In accordance with DLS, the write address waddr is delayed and applied to the DPRAM 12 side. On the other hand, the data reading unit 13 reads data from the DPRAM 12, and reads control information such as a read address rd_addr, a read enable signal rden, and a read clock rclk on the approved address map. It outputs to the read address / control signal generator 15 side and applies the read address rd_addr to the delay selector 16 side. The read address / control signal generator 15 reads corresponding to the read control information such as the read address rd_addr, the read enable signal rden, and the read clock rclk received from the data reader 13. The data read operation to the DPRAM 12 is controlled by generating a clock rclk, a read enable signal rden, and a read address raddr and applying it to the DPRAM 12. Then, the DPRAM 12 writes the data applied from the data recording unit 11 to the write clock wclk, the write enable signal wren, and the write address waddr received from the write address / control signal generator 14. Data stored in accordance with the read data (rclk), read enable signal (rden), and read address (raddr) received from the read address / control signal generator (15). Output to the side.

On the other hand, the delay selector 16 is provided with a write reference window generator 17, a read reference window generator 18, and a comparison determination unit 19 as shown in FIG. The write reference window 17 generates a write reference window signal in a '1' state (high level) according to the authorized write address wr_addr and check_clock and outputs the result to the comparison determination unit 19. The read reference window generator 18 generates a read reference window signal having a '1' state (high level) according to the read address (rd_addr) and the check clock (check_clock), and outputs the read reference window signal to the comparison determination unit 19. . The comparison determination unit 19 compares the write reference window signal applied from the write reference window generator 17 with the read reference window signal applied from the read reference window generator 18 according to a check clock (check_clock) to delay the mode. When the write reference window signal and the read reference window signal are equally applied to the '1' state (high level), the delay mode DLS is set to the delay address DLS. By outputting to the (14) side, the write address / control signal generator 14 applies the write address waddr to the DPRAM 12 at a delayed timing so that the same write and read addresses are simultaneously applied to the DPRAM 12. Do not become.

That is, the process of determining the delay mode by the delay selector 16 will be described with reference to the flowchart of FIG. 5.

First, the comparison determination unit 19 of the delay selecting unit 16 sets the delay mode to the off state (step ST1), and the recording reference window signal applied from the recording reference window generating unit 17 is '1'. If it is confirmed that the state is a 'state (high level) (step ST2), and it is confirmed that the write reference window signal is in the' 1 'state, the corresponding write reference window signal and read reference window signal applied from the read reference window generator 18 The comparison is made in accordance with the check clock (check_clock) (step ST3). At this time, when the comparison determination unit 19 of the delay selection unit 16 confirms that both the write reference window signal and the read reference window signal are in the '1' state (high level) (step ST4), the delay mode is turned on. It sets to a state and outputs the delay signal DLS (step ST5).

An operation process of the cell transfer apparatus according to the present invention configured to have the above function will be described with reference to the timing diagram of FIG. 4.

Referring to the timing chart related to writing to the DPRAM 12 in Fig. 4, data is written to the DPRAM 12 at the falling edge of the write clock wclk, and the data writing time is recorded data and the write address. It is a stable midpoint of (waddr). Here, the DPRAM 12 checks whether or not both the write reference window signal and the read reference window signal are in the '1' state according to the input timing of the check clock (check_clock), which is a clock multiplied by the write clock wclk. At the same time, it is determined whether or not recording and reading are performed at the same address. In this case, the reason for using the check clock multiplied by 2 times is that when the clock having the same period as the data is used, if the time of comparison changes, the value of the comparison target is changed and the judgment is impossible. This is because, when the comparison is made by the timing of the check clock multiplied by 2 times, even when the value of the comparison target is changed once, the value of the stable comparison target can be compared at the next comparison point.

Referring to the read clock rclk for the case of reading data for the DPRAM 12 at time point 3 in FIG. 4, data read timings of case 1, case 2, case 3 or other data may be obtained. The relationship of the data read timing to the write timing is relative. In reality, while the data reading timing of the data reading section 13 is fixed, the data writing timing of the data recording section 11 is related to the timing from the outside, and thus the data writing timing and the data reading timing have such a relative timing relationship.

That is, in the cell data transfer apparatus of the present invention, the delay selector 16 has a relative relationship between the data writing timing of the data recording unit 11 and the data reading timing of the data reading unit 13 to determine whether the two timings overlap. The comparison determining unit 19 of the delay selection unit 16 may generate a write reference window signal generated by the write reference window generator 17 and a read reference window signal generated by the read reference window generator 18. In comparison, by determining whether or not to set the delay mode, the write address output of the write address / control signal generator 14 is delayed to prevent writing and reading data at the same address to the DPRAM 12 simultaneously.

At this time, the delay selector 16 operates as shown in Fig. 5 to determine the delay mode. First, the comparison determination unit 19 of the delay selecting unit 16 sets the delay mode to the off state (step ST1), and the recording reference window signal applied from the recording reference window generating unit 17 is '1'. If it is confirmed that the state is' state (high level) (step ST2) and the record reference window signal is found to be in the state of '1', the corresponding record reference window signal and the read reference window signal applied from the read reference window generator 18 The comparison is made in accordance with the check clock (check_clock) (step ST3). Accordingly, when the comparison determination unit 19 of the delay selection unit 16 confirms that both the write reference window signal and the read reference window signal are in the '1' state (high level) (step ST4), the delay mode is turned on. Set to the state to output the delay signal (DLS).

In this way, when the comparison determination unit 19 of the delay selection unit 16 applies the delay signal DLS to the write address / control signal generator 14 side, the write address / control signal generator 14 causes the write address ( waddr is delayed by two or more clocks and output to the DPRAM 12, whereby data is recorded in the DPRAM 12 as much as two clocks. Therefore, at the timing of writing and reading data to the same address at the same time with respect to the DPRAM 12, the write address is delayed by two or more clocks to be applied to the DPRAM 12 to prevent writing and reading to the same address at the same time. If it is not the timing of writing and reading data at the same address at the same time, the write address is applied to the DPRAM 12 as it is without delay.

As described above, the present invention provides a write and read address for a DPRAM by applying a write address to the DPRAM by delaying a write address at a timing at which data write and read operations are performed at the same time when data is transferred in units of cells through the DPRAM. This prevents the collision of the cell data and thus the loss of cell data.

Claims (6)

A data recording unit which applies data to the DPRAM and records the data, and transfers write control information including a write address, a write enable signal, and a write clock on the received address map; A write address / control signal generator for generating a write address, a write enable signal, a write clock signal corresponding to the write clock, a write enable signal, and a write address to the DPRAM; A data reading unit reading data from the DPRAM and transferring read control information including a read address, a read enable signal, and a read clock on an approved address map; A cell unit including a read address, a read enable signal in the read control information, a read clock corresponding to the read clock, a read enable signal, and a read address / control signal generator for generating a read address and applying the read address to the DPRAM; A cell transfer device in a communication system, According to the write address in the write control information, the read address in the read control information, and whether or not the delay mode is set, the delay signal is outputted to the DPRAM by the write address / control signal generator. A delay selector for delaying the write address output; The delay selector, A record reference window generator for generating and outputting a record reference window signal in a predetermined state according to the authorized write address and check clock; A read reference window generator for generating and outputting a read reference window signal having a predetermined state according to the read address and the check clock received; And a comparison determining unit for comparing the write reference window signal with the read reference window signal according to a check clock and setting a delay mode to output a delay signal to the write address / control signal generator. Cell transfer device in unit communication system. delete The method of claim 1, And the check clock multiplies the recording clock by a predetermined multiple. In a cell delivery method in a cell-based communication system, Generating a write reference window signal in accordance with a write address for the DPRAM; Generating a read reference window signal in accordance with a read address for the DPRAM; Checking whether the read reference window signal is equally activated while the write reference window signal is activated; And if it is determined that the write reference window signal and the read reference window signal are equally activated, setting the delay mode to delay and output the write address applied to the DPRAM. Cell delivery method in the system. The cell transfer of claim 4, wherein the write reference window signal and the read reference window signal are generated in synchronization with a check clock generated by multiplying the write clock by a predetermined multiple. Way. The cell unit communication method according to claim 4, wherein when the recording reference window signal and the reading reference window signal are identified to be equally activated, the unit-by-cell communication is performed in synchronization with a check clock generated by multiplying the recording clock by a predetermined multiple. Cell delivery method in the system.