JP3183956B2 - Buffer memory circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a buffer memory circuit, and more particularly to a buffer for inserting a dummy cell in order to preserve a signal length when a cell is lost during transmission when a signal is divided into cells and transmitted. It relates to a memory circuit. The technique of dividing a signal into cells for transmission is widely used in, for example, packet switching and ATM transmission.

[0002]

2. Description of the Related Art Conventionally, there is a buffer memory circuit of this kind shown in FIG. FIG. 2 is a block diagram of a conventional example. The buffer memory 21 receives the input data signal 101 and writes it according to the instruction of the write counter 23.
Further in accordance with an instruction read by the counter 24, it reads the data with write time and a predetermined delay time, and outputs an output data signal 102.

When it is determined that n cells have been discarded during transmission of the cells constituting the input data signal 101, it is necessary to insert the n dummy cells into the data signal.
For this purpose, the dummy cell insertion signal 103 is input to the write counter 23, and the write counter is advanced by n cells. For example, if the information byte in one cell is composed of 5 bytes, the write counter is advanced by 5 × n bytes. Then, n cells are equivalently inserted in the buffer memory.

[0004]

However, the conventional method has the following problems. Since incrementing the write counter is performed instantaneously, the inserted cell is equivalent to being instantly written into the buffer memory. On the other hand, if the writing phase and the reading phase of the buffer memory are not separated to some extent, a memory slip occurs. If the write counter advances instantaneously, the write phase and the read phase that have been separated from each other suddenly approach, and a memory slip may occur. Memory slip is a practical problem because it causes data errors.

[0005]

A buffer memory circuit according to the present invention comprises a first buffer for writing a data signal formed by dividing a signal into cells and a second buffer for writing a read signal from the first buffer. A buffer, a first write counter for the first buffer instructing insertion of a dummy cell by a dummy cell insertion signal from the outside, a first read counter for the first buffer, and a second read counter for the second buffer. And a second read counter for the second buffer.

[0006]

Next, an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram of the present embodiment. This buffer memory circuit is composed of a write counter 2,5 and read out counter 4,6 respectively corresponding to the buffer memories 1 and 2 of the two positions.

The information contained in the cell is stored in the buffer memory 2.
Is written to the buffer memory 1 before being written to the buffer memory 1.
In the buffer memory 1, dummy cells are inserted by advancing the write counter as in the conventional method. However, in the buffer memory 1, the reading need not be performed continuously, but may be performed only when data to be read remains.

That is, the conditions for the memory slip in the buffer memory 1 are relaxed, and there is no problem even if the write counter of the buffer memory 1 suddenly advances. Considering the writing of the buffer memory 2, the dummy cells are also written in order for each cell. Therefore, the writing counter of the buffer memory 3 does not instantaneously advance, and the memory slip is suppressed.

[0009]

As described above, the buffer memory circuit of the present invention uses two buffer memories connected in series, and the buffer memory at the stage before the dummy cell is inserted has a constant write and read timing delay. Since it is not necessary to keep the value, there is an effect that occurrence of memory slip is suppressed and no error occurs in output data.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a block diagram of a conventional buffer memory circuit.

[Explanation of symbols]

 1, 2 Buffer memory 3, 5 Write counter 4, 6 Read counter 101 Input data signal 102 Output data signal 103 Dummy cell insertion signal

Continuation of the front page (72) Inventor Hiromi Ueda 1-6-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Japan Telegraph and Telephone Corporation (56) References Tournament B-719 (58) Fields surveyed (Int. Cl. ⁷ , DB name) H04L 12/56 H04L 12/28 H04L 13/08

Claims (2)

(57) [Claims] 1. A data signal obtained by dividing a signal into cells.
A first buffer for writing, and reading the first buffer.
A second buffer for writing the output signal and a dummy from the outside.
The second cell instructing insertion of a dummy cell by a cell insertion signal.
A first write counter for one buffer;
A first read counter for one buffer;
A second write counter for the second buffer;
And a second read counter for the second buffer.
e, When data remains in the first buffer memory,
Buffer memory, including means for reading the data
circuit. 2. The reading of the second buffer is continuously performed.
2. The buffer memory circuit according to claim 1 , further comprising means for performing .