AU6519399A - Method and apparatus for de-jittering asynchronous data transfer delay - Google Patents

Method and apparatus for de-jittering asynchronous data transfer delay

Info

Publication number
AU6519399A
AU6519399A AU65193/99A AU6519399A AU6519399A AU 6519399 A AU6519399 A AU 6519399A AU 65193/99 A AU65193/99 A AU 65193/99A AU 6519399 A AU6519399 A AU 6519399A AU 6519399 A AU6519399 A AU 6519399A
Authority
AU
Australia
Prior art keywords
jittering
data transfer
asynchronous data
transfer delay
delay
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU65193/99A
Inventor
Chi-Ping Nee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tiernan Communications Inc
Original Assignee
Tiernan Communications Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tiernan Communications Inc filed Critical Tiernan Communications Inc
Publication of AU6519399A publication Critical patent/AU6519399A/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
    • H04J3/0632—Synchronisation of packets and cells, e.g. transmission of voice via a packet network, circuit emulation service [CES]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
    • H04Q11/0478—Provisions for broadband connections
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5638—Services, e.g. multimedia, GOS, QOS
    • H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
    • H04L2012/5652—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5672—Multiplexing, e.g. coding, scrambling
    • H04L2012/5674—Synchronisation, timing recovery or alignment
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
    • H04L2012/5681—Buffer or queue management
    • H04L2012/5682—Threshold; Watermark
AU65193/99A 1998-10-21 1999-10-19 Method and apparatus for de-jittering asynchronous data transfer delay Abandoned AU6519399A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10508398P 1998-10-21 1998-10-21
US60105083 1998-10-21
PCT/US1999/024277 WO2000024144A1 (en) 1998-10-21 1999-10-19 Method and apparatus for de-jittering asynchronous data transfer delay

Publications (1)

Publication Number Publication Date
AU6519399A true AU6519399A (en) 2000-05-08

Family

ID=22303952

Family Applications (1)

Application Number Title Priority Date Filing Date
AU65193/99A Abandoned AU6519399A (en) 1998-10-21 1999-10-19 Method and apparatus for de-jittering asynchronous data transfer delay

Country Status (2)

Country Link
AU (1) AU6519399A (en)
WO (1) WO2000024144A1 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101048813B (en) * 2004-08-30 2012-08-29 高通股份有限公司 Adaptive de-jitter buffer for voice IP transmission
CN100387078C (en) * 2005-03-23 2008-05-07 华为技术有限公司 Method for realizing data transmitting-receiving processing of BTS
US8260285B2 (en) 2005-06-14 2012-09-04 St-Ericsson Sa Performing diagnostics in a wireless system
US7512157B2 (en) * 2005-06-15 2009-03-31 St Wireless Sa Synchronizing a modem and vocoder of a mobile station

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3183956B2 (en) * 1992-07-23 2001-07-09 日本電気株式会社 Buffer memory circuit
JPH07221761A (en) * 1994-02-04 1995-08-18 Fujitsu Ltd Cell delay absorption circuit
DE4417286A1 (en) * 1994-05-13 1995-11-23 Deutsche Bundespost Telekom ATM buffer circuit data read-out method
US5623483A (en) * 1995-05-11 1997-04-22 Lucent Technologies Inc. Synchronization system for networked multimedia streams
EP0876016B1 (en) * 1997-05-02 2006-03-22 Lsi Logic Corporation Adaptive digital clock recovery

Also Published As

Publication number Publication date
WO2000024144A1 (en) 2000-04-27

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase