JPH0583235A - Data error prevention system at speed conversion - Google Patents

Abstract

PURPOSE:To attain speed conversion of a CLK without causing a data error by implementing read control of a dual port RAM. CONSTITUTION:A line interface of a transmitter provided with a dual port RAM 101, a write control section 102 and a read control section 103 is employed for the system. Then an address monitor section 104 detects a phase difference between a write address generated by the write control section 102 and a read address generated by the read control section 103. When the phase difference reaches a prescribed value or below, the read of data from the dual port RAM 101 is stopped by the read control section 103 till the phase difference reaches a prescribed value or over.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention, in a transmission device connected to a line, interfaces with the line and CL of the line.
Used for the line interface of the transmission device that needs speed conversion from K (clock signal) to CLK in the local device.
The present invention relates to a data error prevention method during speed conversion.

[0002]

2. Description of the Related Art With the recent diversification of networks, transmission devices are required to be connected to many networks, and in order to communicate data between each network and its own station,
Speed conversion must be performed from the CLK of the line to the CLK of the own station device. However, in this case, since CLK is asynchronous, a data error occurs due to the CLK phase, but it is necessary to perform speed conversion of CLK without causing such a data error.

In the conventional transmission apparatus, the line CLK
When performing speed conversion from CLK to the CLK of the local device, RA
The CLK speed conversion is performed by switching each surface by the two-surface configuration of M. That is, two RAMs are prepared, and the CLK speed conversion is performed by switching those RAMs.

[0004]

However, when the CLK phases are close to each other, the planes are automatically switched to change the CLK
When the CLK phase is adjusted by shifting the phase by π / 2, data can be normally communicated only after a momentary data error.

Therefore, even if the surface switching is completed in an instant and the data can be normally communicated, a data error occurs for a moment when the surface switching is performed.

The present invention has been made in consideration of such a situation. Even if the CLK phases are close to each other, the surface switching is not performed and the read control of the dual port RAM is performed, so that the data error is not generated. It is intended to provide a data error prevention method at the time of speed conversion capable of performing the speed conversion of CLK.

[0007]

FIG. 1 is a circuit block diagram showing a line interface of a transmission apparatus to which the present invention is applied. The present invention will be described with reference to this figure. The dual port RAM 101 and the write address, write enable, and write clock signals are generated from the clock signal of the line, and the data from the line is supplied to the dual port RAM 10 according to the generated signals.
1, a write control unit 102 for writing to 1 and a read control for generating a read address, a read enable, and a read clock signal from a clock signal in the local station device and reading data from the dual port RAM 101 into the local station device according to the generated signals. An address monitoring unit 104 is provided in the line interface of the transmission device including the unit 103, and the address monitoring unit 104 causes the write control unit 1 to operate.
When the phase difference between the write address generated in 02 and the read address generated in the read control unit 103 is detected and the phase difference becomes a certain value or less, the phase difference is read until it becomes a certain value or more. This is a data error prevention method at the time of speed conversion, which consists of stopping the reading of data from the dual port RAM 101 by the control unit 103.

[0008]

According to the present invention, as shown in FIG. 1, the write address (A0 to AN) of the dual port RAM 101 is used.
And a read address (B0 to BN) are detected, and when the phase difference becomes a certain value or less, a read stop signal (RSTOP) is sent from the address monitoring unit 104 to the read control unit 103. In the read control unit 103,
Dual port RAM 101 by read stop signal
The output of the read address, the read enable, and the read clock signal to is stopped, and empty data is inserted.

Therefore, when the phases of the clock signals are close to each other, read control is applied to the dual port RAM 101 to enable data speed conversion without causing a data error.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below based on the embodiments shown in the drawings. The present invention is not limited to this.

FIG. 2 is a circuit block diagram showing a line interface of a transmission device to which the data error prevention method at the time of speed conversion of the present invention is applied. In the figure, 1 is a dual port RAM for speed conversion (hereinafter referred to as DP-RAM), 2 is a write controller, and this write controller 2
Generates a write address counter 2a that generates a write address signal (A0 to AN) from a line clock signal (LCLK), a write enable generator 2b that generates a write enable signal (WE), and a write clock signal (WCLK). It is composed of a frequency divider 2c for performing data from the line (RD0) according to these signals.
To the dual port RAM1.

Reference numeral 3 denotes a read control unit. This read control unit 3 generates a read address signal (B0 to BN) from a clock signal (SCLK) in the local station device, and a read enable signal ( The read enable generator 3b for generating the RE) and the frequency divider 3c for generating the read clock signal (RCLK).
The data (RD1) is read from M1 into the own station device.

Reference numeral 4 denotes an address monitoring unit. This address monitoring unit 4 is a counter 4a for monitoring the buffer capacity of the DP-RAM 1, a write address generated by the write control unit 2 and a read address generated by the read control unit 3. When the phase difference between the write address and the read address is less than a certain value, the read control section 4b is configured to detect the phase difference between the write address and the read address. The read stop signal (RSTOP) is sent to the signal No. 3. The read control unit 3 stops the output of the read address, the read enable, and the read clock signal to the DP-RAM 1 by the read stop signal, and inserts the empty data. As a result, the read control unit 3 stops reading data from the DP-RAM 1.

FIG. 3 is a timing chart showing the timing of signals in the embodiment, and shows the implementation timing of the circuit shown in FIG. In FIG. 3, the names of signals are shown in FIG.
The same symbols as the signals shown in are shown.

In the figure, indicates the timing at which the write controller 2 generates the write address (A0 to AN) of the DP-RAM 1 based on LCLK. Is from LCLK to WE
Is generated and the line data RD0 is written in the DP-RAM1. Is read control unit 3 SCLK
Based on the read address of DP-RAM1 (B0 to BN)
It shows the timing to generate. Indicates a position where RE is generated from SCLK and line data written in DP-RAM1 is read out in synchronization with CLK in the device of the own station.

The position indicated by means a case where the address difference 4 is detected by the address monitoring unit 4, and when this is used as the write / read threshold value,
The next N + 5 address is not read and the address difference is 2
Until the above, read address, read enable,
And the DP-RA so that the read clock signal is not output.
Apply read control of M1. At this time, the data of the address N + 4 is output as the data of RD1 (see the read stop section in the figure). After that, when the difference between the write / read addresses becomes 1 or more, the reading is started again from the DP-RAM 1 (in the figure: read start, see).

As described above, the DP / RAM 1 write /
The difference between the read addresses is detected, a certain fixed value is set as the threshold value, and when it reaches that value, DP-RA
By performing control such that the reading from M1 is stopped and the reading is restarted when the threshold value is exceeded, the speed conversion can be performed without causing a data error.

[0018]

As described above, according to the present invention, speed conversion can be performed without causing a data error in speed conversion between the line and the local station. Therefore, it greatly contributes to the speed conversion method of the transmission device that interfaces with the line.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing a line interface of a transmission device to which the present invention is applied.

FIG. 2 is a circuit block diagram showing an embodiment of a line interface of a transmission device to which the present invention is applied.

FIG. 3 is a timing chart showing the timing of signals in the embodiment.

[Explanation of symbols]

 1 Dual Port RAM 2 Write Controller 2a Write Address Counter 2b Write Enable Generator 2c Write Divider 3 Read Controller 3a Read Address Counter 3b Read Enable Generator 3c Read Divider 4 Address Monitor 4a Counter 4b Difference Detector

Claims (1)

[Claims] 1. A dual port RAM for speed conversion (1
01), and generate the write address, write enable, and write clock signals from the line clock signal,
Write controller (102) for writing data from the line to the dual port RAM (101) according to the generated signal
And generate a read address, a read enable, and a read clock signal from the clock signal in the own station device,
Dual port RAM (101) according to the generated signal
Read control unit (10) that reads data from the
3) is provided in the line interface of the transmission device including the address monitoring unit (104), and the address monitoring unit (104) causes the write address generated by the write control unit (102) and the read control unit (103). When the phase difference from the generated read address is detected and the phase difference becomes a certain value or less, the dual port RAM (101) by the read control unit (103) until the phase difference becomes a certain value or more. A data error prevention method at the time of speed conversion, which consists of stopping the reading of data from.