JPH03265239A - Clock transfer circuit - Google Patents

Abstract

PURPOSE:To eliminate the need for a memory for clock transfer by storing a reception data into a memory storing the result of retrieval of synchronization information and reading the reception data with a delay of an optional time. CONSTITUTION:A synchronization information retrieval circuit 4 receives a clock and a data to detect synchronization information and the bit of the information is compared with a check bit in a dual port RAM 1 through an A port. When the result of comparison tells OK, a succeeding check bit is used and when succeeding synchronization information is detected, it is compared with a check bit replaced and stored and when OK, a succeeding check bit is selected, and when a frame pattern is detected, the synchronization information is sent to a receiver. When not OK, it is discriminated to be a data bit and written in the RAM 1. An address generator 2 uses a write control signal to write a received data to an A port of the RAM 1 synchronously with the reception clock and an address generator 3 receives a read control signal of the equipment side and a clock and outputs the received data from a B port of the RAM 1 synchronously with the clock after an optional time. One memory is enough for the purpose and the cost is reduced.

Description

[Detailed Description of the Invention] [Summary] Regarding a transmission line interface that synchronizes data received from a transmission line using memory and synchronizes it with a clock on the receiving device side, two memories are provided: one for synchronization and one for clock switching. A dual port RAM that simultaneously stores synchronization information search results and received data, a first address generator that generates a write address for the GL RAM, and a first address generator that generates a read address for the RAM. The dual port RAM has two ports, an A port and a B port, and an A port and a B port. Writing and reading of synchronous search results and writing of received data are performed, and the B port is configured to only read received data.

[Industrial Application Field] The present invention relates to a transmission line interface that synchronizes data received from a transmission line using a memory and synchronizes it with a clock on a receiving device side.

FIG. 5 shows an example of a frame structure of data received from a digital transmission path. One frame is 1 b of flag bit F.
It consists of 192 bits of data and 1 frame in 24 frames.
It composes a multi-frame. Flag bits F that constitute one multiframe are 12 bits of data bits D.
, 6 bits of check bit C, and 6 bits of frame pattern bit FP, for a total of 24 bits.Data bit D, check bit C3 data bit D1, frame pattern bit FP, and data bit D are alternately repeated to form one multiframe. He is in charge. Data bit D determines the data format, check bit C checks data errors, and frame pattern bit FP detects frame synchronization.

By searching the frame pattern P1-FP, which is repeatedly received every four flag bits, on the receiving device side, the synchronization information of the frame pattern can be confirmed. For example, FP is “00101” in l multiframe.
If 6 bits of 1'' are detected, they are sent to the receiving device as synchronization information, and in the case of other bit strings, they are not accepted as synchronization information to monitor frame synchronization.

[Conventional technology]

A block diagram of a conventional receiving side device is shown in FIG. In the figure, 21 is a single port RAM, 22 is a dual port RAM, and 23 is a synchronization detection circuit.

The single-port RAM 21 is a synchronization detection memory and is a writable random access memory that reads and writes synchronization signals from the synchronization detection circuit 23. The dual-port RAM 22 is a two-port memory that writes received data from a transmission line in synchronization with a reception clock and reads data in synchronization with a clock on the receiving device side, and may also be a FIFO memory. The synchronization detection circuit 23 compares the synchronization information distributed and inserted at specific positions of the received data with the past synchronization information search results for the focus position read from the RAM 21, determines whether the synchronization information is synchronization information, and detects the result. is output to the receiving device side as synchronization information, and the synchronization information search result is updated and written to the RAM 21. In the RAM 22, received data is written in synchronization with the reception clock, the data is read out in synchronization with the device clock after an arbitrary time delay, and the data is output to the receiving device side.

FIG. 7 shows an operation timing chart of the conventional example. figure(
Figure a) shows the synchronization detection operation, and Figure (b) shows the clock transfer operation.

In FIG. 7(a), when the synchronization detection circuit 23 detects synchronization signals dispersedly inserted at specific positions of the transmission line received data, the check bits stored in the RAM 21 are read out, and if OK, the next This check bit becomes the check bit when the next check bit is detected by the synchronization detection circuit 23. When a frame pattern of check bits is detected by repeating these read and write operations, synchronization information bits are sent from the synchronization detection circuit 23 to the receiving device side and a processing operation is performed. Note that if the check bits stored in the RAM 21 are read out and are not OK, the node waits at its own node or moves to another node.

In Figure (b), the RAM 22 stores received data D, , D, , D in synchronization with the rising edge of the receiving clock.

The received data is written sequentially as D3. , D z, D 3- ・--
−−−−・− are output sequentially. Therefore, the received data can be transmitted by transferring the synchronization from the transmitter's clock to the receiver's clock.

[Problems to be Solved by the Invention] Conventional devices require separate memories for the RAM 21 for synchronization information detection and the RAM 22 for clock switching.

The present invention aims to eliminate the need for a memory for clock switching by storing received data in a memory that stores synchronization information search results and reading the received data after an arbitrary time delay. .

[Means to solve the problem]

FIG. 1 shows the principle configuration diagram of the present invention. In the figure, ■ is a dual-port RAM that simultaneously stores synchronization information search results and received data, 2 is a first address generator that generates a write address for the RAM, and 3 is a second address generator that generates a read address for the RAM. Address generator 4 indicates a synchronization information search circuit that determines synchronization information bits inserted in received data.

The dual port) RAMI has two ports, A boat and B boat.
The port A is configured to write and read synchronous search results and write received data, and the B port is configured to only read received data.

[Effect]

The synchronization information search circuit 4 receives the reception clock and reception data from the transmission path, detects the synchronization information distributed and inserted in specific positions of the reception data, and checks the check bits stored in the dual port RAM 1 by the A port. If it is OK, replace it with the next check bit, and when the next synchronization information is detected, compare it with the replaced and accumulated check bit, and if it is OK, replace it with the next check bit. If a frame pattern is repeatedly detected, synchronization information is sent to the receiving device.

Furthermore, the synchronization information is detected and compared with the check bit stored in the RAML (dual port) via the A port.
If it is not K, it is determined to be a data bit and written to RAM1.

The address generator 2 writes the received data to the A port of the RAMI in synchronization with the reception clock using the write control signal, and the address generator 3 receives the continuous output control signal and clock signal from the device side, and then writes the received data to the A port of the RAMI in synchronization with the reception clock. Later, the received data stored in RAMI is synchronized with the device clock and sent to RA.
Output data from MI B boat.

FIG. 2 shows an operation timing chart of the present invention. In the figure, received data D+1. D,,D2. D3-. is written to RAM1 in synchronization with the rising edge of the reception clock,
If the received data D0 is synchronous information, the check bit in the memory is read, and if it is OK, the next check bit is written and replaced, and is used as the check bit when the next synchronous information is received.

At the same time, the received data D0 is written to the RAMI address set by the address generator 2, and the data DI,
D z and D s '--.-- are written in the same way.

Data D+, Dz, D3' of the same address stored in the RAMI is synchronized with the rise of the device clock by the read control signal of the device side of the address generator 3.
-... are output one after another, and after an arbitrary time, data is sent from the B port.

〔Example〕

A block diagram of an embodiment of the present invention is shown in FIG. In the figure, 11 is a dual port RAM, 1213 is an address generator, and 14 is a synchronization information search circuit. AA is the write control signal from the address generator 12 and the received CLK signal, WEA is the write signal caused by the rising edge of the received CLK,
iA is the received data OA and synchronization information search circuit 14 to RA
A human input signal to M11, oA is an output signal from RAMII to the synchronization information search circuit 14, oB is a data output from RAM1l, AB is a read control signal and device CLK signal from the address generator 13 to RAMII, and SD is synchronization information. It shows synchronization information bits sent out from the search circuit 14.

iA sent from the synchronization information search circuit 14 to RAMII
is a combination signal of 1 bit of received data DA and 4 bits of synchronization information search bit. 1 bit of received data is stored as data in the memory 11, and if it is a synchronization information search bit, it is synchronized by the synchronization information search circuit 14. Read 4 check bits from the memory 11, and if the check result of the synchronous check bit is OK, replace it with the next check bit, and if it is not OK, read it into the RAM as a data pin.
Write to II.

An embodiment of the synchronization information search focus of the synchronization information search circuit 14 is shown in FIG. In the figure, the synchronization frame search pattern is a 6-bit pattern of "001011", the first check pin "0" is "0000", the next check bit "0" is "ooio", and the next check bit "1m" is "0100". ”, next check bit “0” is “l010”
”, the next check bit “1” is “1011”, and the final check focus “1” is “1111”, and if the final check bit is OK, “l” is sent to the receiving side as synchronization information. If the position of the first check bit is 1, "0001" is written to the memory and stored as data without being treated as synchronization information. Similarly, if the next check bit is "1", "0011" is written into the memory as data and is not treated as synchronization information.

Become. Furthermore, by increasing the memory capacity, it is no longer necessary to worry about the proximity of the reading side and writing side due to positional fluctuations. Furthermore, data strings can be easily replaced.

[Brief explanation of drawings]

FIG. 1 is a principle configuration diagram of the present invention, FIG. 2 is an operation timing chart of the present invention, and FIG. 3 is a block configuration diagram of an embodiment.
FIG. 4 shows an example of a synchronization information search bit, FIG. 5 shows an example of a frame structure of received data, FIG. 6 shows a block diagram of a conventional example, and FIG. 7 shows an operation timing chart of a conventional example. In the figure, 1, LL 21.22 are RAM, 2,
3.12 and 13 are address generators, and 4.14.23 is a synchronization information search circuit. [Effects of the Invention] The present invention requires only one memory instead of the conventional two, which reduces costs, improves reliability, and downsizes the device, making it easy to implement LSI with built-in memory (a) Synchronous detection operation (b) Clock transfer operation Conventional operation timing chart Fig. 7

Claims (1)

[Claims] In a transmission line interface that synchronizes data received from a transmission line using a memory and synchronizes it with a clock on the receiving device side, a dual port RAM (RAM) that simultaneously stores synchronization information search results and received data. 1), a first address generator (2) that generates a write address for the RAM, and a second address generator (3) that generates a read address for the RAM.
) and a synchronization information search circuit (4) that determines the synchronization information bit inserted in the received data, the dual port RAM (1) has two ports, an A port and a B port, A clock switching circuit characterized in that the port writes and reads synchronous search results and writes received data, and the B port only reads received data.