KR100350465B1 - Apparatus and method for synchronizing serial lines using fifo memory - Google Patents

Abstract

The present invention relates to an apparatus and a method for synchronizing data received from a plurality of serial lines that are not synchronized in a digital switching system, the serial matching unit, the serial matching unit to be matched to a plurality of serial lines for transmitting serial data The serial data is converted into parallel and stored in a first-in first-out memory of a plurality of first-in first-out memories corresponding to one serial line, respectively. A plurality of counters counting the start and end points of the serial data, a plurality of end point searchers searching for an end point of the serial data in response to a counting result of each counter, and a synchronization point in response to an end point search result of the end point searchers A synchronization counter for determining a value of the determined It characterized in that it comprises in parallel matching unit time period for outputting the output data at the same time from the plurality of first-in-first-out memory in parallel.

As a result, the present invention can increase communication capacity by synchronizing data received through a plurality of unsynchronized serial lines and converting the data into parallel data.

Description

Synchronization apparatus and method using first-in, first-out memory {APPARATUS AND METHOD FOR SYNCHRONIZING SERIAL LINES USING FIFO MEMORY}

The present invention relates to a digital switching system, and more particularly, to an apparatus and a method for synchronizing data received from a plurality of serial lines which are not synchronized.

The digital exchange system performs various functions such as information transfer function including a switching function, a service providing function, a signal (call) processing function for using a communication function of a communication network, and a control function for controlling a communication network. In particular, the digital exchange system that supports Asynchronous Transfer Mode (ATM) technology, such as the ACE-2000 exchange, is a core exchange of the high-speed information communication network that enables high-speed, high-capacity information transfer. It provides the function of matching between switching system and existing communication network.

In digital switching systems that process large amounts of information, it is essential that the processor support parallel data processing. Processors that support parallel communication have the ability to process multiple bits of information data simultaneously and are matched to a serial line through a serial matching device.

1 shows an example of a parallel / serial matching structure in a digital switching system according to the prior art. Referring to FIG. 1, the serial matching processor 10 may process and transmit 16 bit parallel data through a 16 bit bus, and the parallel data may be transmitted through a serial matching device 11 performing 16 bit parallel / serial conversion. It can be connected by one serial line.

In the digital switching system configured as described above, the serial matching processor can process 16-bit parallel data. When the serial matching device can support only 8 bits, two serial matching devices are used.

2 shows another example of a parallel / serial matching structure in a digital switching system according to the prior art. Referring to FIG. 2, the serial matching processor 10 supporting parallel communication may process and transmit 16 bits of parallel data, and the first serial matching device 13 may serially order the upper 8 bits of the 16 bits of parallel data in series. The second serial matching device 15 converts the lower 8 bits of the 16-bit parallel data into serial and connects them to the second serial line. As a result, the serial matching processor 10 is connected to two independent serial lines.

In this case, since the first serial matching device 13 and the second serial matching device 15 process each line communication separately, the synchronization between the two lines on the receiving side does not match. The conventional digital switching system did not provide a technique for synchronizing data generated from the same source and transmitted to different serial lines, so each serial line had to be processed separately, which made it difficult to maintain the same data. . In addition, there was a problem that communication capacity was reduced because only direct communication through each serial line had to be performed.

Accordingly, an object of the present invention, which was devised to solve the problems of the prior art operating as described above, is to provide an apparatus and method for synchronizing synchronization of a plurality of serial lines.

It is another object of the present invention to provide an apparatus and method for synchronizing serial data received over a plurality of unsynchronized serial lines using a first-in first-out memory.

An embodiment of the present invention, which was created to achieve the above object, in a synchronization device using a first-in first-out memory,

A serial matching unit matched to a plurality of serial lines for transmitting serial data;

A plurality of serial / parallel converters for converting serial data received through the serial matching unit into parallel and storing the serial data in a first-in first-out memory among a plurality of first-in first-out memories corresponding to one serial line;

A plurality of counters that count start and end points of serial data corresponding to the serial / parallel converters;

A plurality of endpoint searchers for searching for endpoints of corresponding serial data in response to a counting result of each of the counters;

A synchronization counter for determining a synchronization point in response to an endpoint search result of the endpoint searchers;

And a parallel matching unit for outputting data simultaneously output from the plurality of first-in first-out memories at the determined synchronization time point in parallel.

Another embodiment of the present invention is a synchronization device using a first-in first-out memory,

A plurality of serial / parallel matching units for receiving serial data from a plurality of serial lines which are not synchronized with each other and converting them in parallel;

A plurality of first-in first-out memories each corresponding to one serial line and receiving and storing the converted parallel data;

A synchronization counter for determining a synchronization point by searching and comparing end points of serial data received through the plurality of serial lines;

And a parallel matching unit which simultaneously reads data stored in the plurality of first-in first-out memories at the determined synchronization point and outputs the data as parallel data.

Another embodiment of the present invention is a synchronization method using a first-in first-out memory,

Receiving serial data from a plurality of serial lines which are not synchronized with each other, and storing the serial data in a corresponding first-in first-out memory among a plurality of first-in first-out memories corresponding to one serial line, respectively;

Determining a synchronization time point of serial data received through the plurality of serial lines;

And simultaneously reading data stored in the plurality of first-in first-out memories at the determined synchronization time point and outputting the data as parallel data.

1 is a diagram showing a parallel / serial matching structure in a digital switching system according to the prior art.

2 illustrates another example of a parallel / serial matching structure in a digital switching system according to the prior art.

3 is a connection configuration diagram of a synchronization device according to the present invention.

4 is a detailed configuration diagram of the synchronization device of FIG. 3.

5 is a timing diagram of a synchronization device according to the present invention;

Hereinafter, with reference to the accompanying drawings will be described in detail the operating principle of the preferred embodiment of the present invention. Like reference numerals are used to designate like elements even though they are shown in different drawings, and detailed descriptions of related well-known functions or configurations are not required to describe the present invention. If it is determined that it can be blurred, the detailed description will be omitted. Terms to be described later are terms defined in consideration of functions in the present invention, and may be changed according to intentions or customs of users or operators. Therefore, the definition should be made based on the contents throughout the specification.

3 shows a connection configuration diagram of a synchronization device according to the present invention. 4 illustrates a detailed configuration diagram of the synchronization device 100 of FIG. 3, as shown in FIG. 3, a series matching unit 110 and first and second serial / parallel conversion units 120, 125, and first and first units. 2 first-in, first-out memory 130, 135, first and second counter 140, first and second end point searcher 150, 155, synchronization counter 160, write control logic ( 170, read control logic 175, and parallel matching unit 180. 5 shows a timing diagram of the present invention.

Referring to Figures 3 to 5 will be described in detail with respect to the synchronization operation example of the present invention.

The serial matching processor 10 processes and transmits and receives 16-bit parallel data, and the parallel data is connected to the synchronization device 100 through a 16-bit bus. The data to be transmitted is transmitted to the first and second serial lines through a 16 bit serial matching device or two 8 bit serial matching devices. Serial data received from the first serial line and the second serial line are converted in parallel and synchronized by the synchronization device 100 and then provided to the serial matching processor 10.

The first serial line carries the first serial data in synchronization with the first serial clock and inputs it to the serial matching unit 110 of the synchronization device 100, and the second serial line is synchronized with the second serial clock to synchronize the second serial data. Carrying and inputting the serial matching unit 110 of the synchronization device (100). The serial matcher 110 transfers the first and second serial data to the first serial / parallel converter 120 and the second serial / parallel converter 125. The first counter 140 is interlocked with the first serial / parallel converter 120 to count a start point and an end point of the first serial data and display a duration of the first serial data. Outputs 1 count signal. Similarly, the second counter 145 outputs a second count signal indicating the duration of the second serial data. Examples of the first count signal and the second count signal are as shown in FIG.

The write control logic 170 receives the first count signal and the second count signal and provides a write signal to the first first-in first-out memory 130 and the second first-in first-out memory 135, thereby providing a first serial / parallel converter. Serial data passing through the 120 and the second serial / parallel conversion unit 125 are respectively written in the first-in first-out memory 130 and the second first-in first-out memory 135. That is, the first serial / parallel converter 120 stores the first serial data received in synchronization with the first serial clock in parallel with the first first-in first-out memory 130 and the second serial / parallel converter 125. Stores second serial data received in synchronization with the second serial clock in the second first-in first-out memory 135 in parallel. At this time, as shown in the timing diagram of FIG. 5, since the first serial clock and the second serial clock operate independently, the first serial data and the second serial data are also asynchronously inputted by the interval between ① and ②.

Meanwhile, the first endpoint searcher 150 searches for a first count signal, finds an endpoint of the first serial data, and generates and outputs a signal indicating the first serial signal, that is, a first endpoint signal. Similarly, the second endpoint searcher 155 generates and outputs a second endpoint signal, which is a signal indicating an endpoint of the second serial data. Referring to Fig. 5, the first and second end point signals? And? Include pulses indicating the end points of the first and second serial data, respectively. The first and second endpoint signals are provided to the synchronization counter 160.

The synchronization counter 160 generates signals ⑤ and ⑥ having pulses starting from the first and second end points and lasting for a predetermined time (ie margin). The section ⑨, which is a common area between the signals ⑤ and ⑥, is the time point at which the first data arrives among the two serial data and the time point at which the data recorded in the first-in first-out memories are synchronized. That is, the synchronization counter 160 counts a signal that arrives first among the first endpoint signal and the second endpoint signal (the first endpoint signal in FIG. 5) to secure a margin, and generates a signal by matching the signal that arrives later. This signal is defined as a synchronization signal that determines the timing of synchronization and is provided to read control logic 175. The margin is set such that the signals ⑤ and ⑥ can overlap sufficiently. If the margin is set too short, signals ⑤ and ⑥ will not overlap and interval ⑨ will not occur.

The read control logic 175 provides the first and second first-in first-out memory 130 by providing a read signal to the first and second first-in first-out memory 130 and 135 in synchronization with the synchronization signal provided from the synchronization counter 160. Data is simultaneously output from 135. That is, the first and second first-in, first-out memory 130 and 135 start outputting data at the same time at the synchronization point determined by the synchronization counter 160. At this time, the read control logic 175 maintains the read signal for a time enough to output the written serial data according to the counting result of the first and second counters 140 and 145. The parallel matching unit 180 combines 8-bit parallel data output from the first and second first-in first-out memory 130 and outputs the 16-bit parallel data. The 16 bit parallel data output from the parallel matching unit 180 is provided to the serial matching processor 10.

Briefly describing the operation of the present invention, the first and second serial data are written to the first and second first-in first-out memory 130, 135 without synchronization, respectively, but the serial data arrived later is last written. By counting the viewpoints, data output from the first and second first-in first-out memory 130 and 135 may be synchronized.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications are possible without departing from the scope of the present invention. For example, the present invention can be used to synchronize data received over three or more unsynchronized serial lines. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined not only by the scope of the following claims, but also by those equivalent to the scope of the claims.

In the present invention operating as described in detail above, the effects obtained by the representative ones of the disclosed inventions will be briefly described as follows.

According to the present invention, data received through a plurality of unsynchronized serial lines may be synchronized and converted into parallel data. Therefore, the present invention is not limited to the throughput of the serial matching device, but can communicate with the throughput of the processor and can increase the communication capacity.

Claims (7)

A synchronization device using a first-in, first-out memory, A serial matching unit matched to a plurality of serial lines each transmitting serial data; A plurality of serial / parallel converters for converting serial data received through the serial matching unit into parallel and storing the parallel data in a first-in first-out memory among a plurality of first-in first-out memories corresponding to one serial line; A plurality of counters that count start and end points of serial data corresponding to the serial / parallel converters; A plurality of endpoint searchers for searching for endpoints of corresponding serial data in response to a counting result of each of the counters; A synchronization counter for determining a synchronization point in response to an endpoint search result of the endpoint searchers; And a parallel matching unit for outputting data simultaneously output from the plurality of first-in first-out memories in parallel at the determined synchronization time point. The method of claim 1, further comprising write control logic to provide a write signal for each of the plurality of first-in first-out memories to the plurality of first-in first-out memories in response to a counting result of each of the counters. Device. 2. The apparatus of claim 1, further comprising read control logic for simultaneously providing a read signal to the plurality of first-in, first-out memories at a synchronization time determined by the synchronization counter. The method of claim 1, wherein the synchronization counter generates a plurality of signals including pulses starting from a corresponding endpoint and lasting for a predetermined time in response to each endpoint search result of the endpoint searchers. A device characterized in that for determining the synchronization point in the overlap section. A synchronization device using a first-in, first-out memory, A plurality of serial / parallel matching units for receiving serial data from a plurality of serial lines which are not synchronized with each other and converting them in parallel; A plurality of first-in first-out memories each corresponding to one serial line and receiving and storing the converted parallel data; A synchronization counter for determining a synchronization point by searching and comparing end points of serial data received through the plurality of serial lines; And a parallel matching unit for simultaneously reading out data stored in the plurality of first-in first-out memories at the determined synchronization point and outputting the data as parallel data. In the first-in-first-out synchronization method, Receiving serial data from a plurality of serial lines which are not synchronized with each other, and storing the serial data in a corresponding first-in first-out memory among a plurality of first-in first-out memories corresponding to one serial line, respectively; Determining a synchronization time point of serial data received through the plurality of serial lines; And simultaneously reading out data stored in the plurality of first-in first-out memories at the determined synchronization point and outputting the data as parallel data. The method of claim 6, wherein the determining of the synchronization time point comprises: Searching for an end point of each serial data received through the plurality of serial lines; And comparing the retrieved end points to determine a time point at which reception of serial data is completed in all serial lines as a synchronization time point.