KR920003268B1 - Address generating system - Google Patents

Abstract

The address generating system for using a hardware to access the data corresponding to an address adding a specific offset to a sequential address, comprises an address generator (100) for accessing memory data longitudinally and an address feedback unit (200) for adding the number of longitudinal addresses to the output address to feedback the resulted address signal to the address generator and a clock generator (300) for providing a ref. clock signal to the units (200,300). The address generator includes a ltch (1) for latching the number of transverse data to be accessed, an up-counter (2) and a buffer (3) for generating a first longitudinal address, a latch (4) for latching the number of longitudinal data, and an address generating counter (6).

Description

Address generation system

1 is a block diagram of an address generation system of the present invention.

2a to i are a waveform diagram of each part of FIG.

3 is an exemplary table of scanning pixel data.

4 is a mapping table of pixel data and memory addresses.

* Explanation of symbols for main parts of the drawings

1, 4: Latch 2, 9: Up counter

3, 8: Buffer 5: Down Counter

6: address generation counter 7: adder

10: comparator 11: flip-flop

100: address generator 200: address feedback unit

300: clock generator OR1, OR2: oragate

AD1, AD2: Andgate I1, I2: Inverter.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to address generation during memory access, and more particularly, to an address generation system suitable for accessing data of an address plus a specific offset in a state where data is stored in a sequential address.

In a general memory control system, processing time is required because software is used to access data of an address plus a specific offset on a sequential address in which data is stored.

In order to solve this problem, the present invention has been made so that data of an address plus a specific offset can be accessed using hardware, which will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram of the address generation system of the present invention, as shown therein, a latch 1 for latching data horizontally to be accessed, and up to generate first data horizontally for accessing a memory. A counter 2, a buffer 3 for buffering the output data of the up counter 2, a latch 4 for latching data to the species to be accessed, and an output data of the latch 4 A down counter 5 for generating data to the species, an address generation counter 6 for inputting output data of the buffer 3 and a buffer 8 to be described later to generate an address to the species, and the latch ( When the adder 7 adds the output data of 1) and the output address of the address generation counter 6, the buffer 8 buffering the output data of the adder 7, and the horizontal data increases one by one. The up counter 9 which counts every time, and the said Comparator 10 for outputting a low potential when the output data of the device 7 and the up counter 9 are equal to each other and the high comparator is normally output using the pulse of the input / output port IO3 as a clock signal. A flip-flop 11 to be cleared when a low potential is inputted from the input signal, an AND gate AD2 for outputting the flip-flop 11 and the clock signal? C as a control signal of each part of the system, and a load signal to each part of the system. The waveforms of the parts shown in FIG. 1 illustrate the operation and effect of the present invention, which is composed of an AND gate AD1, an OR gate OR1, OR2, and an inverter I1, I2 provided as an out enable signal, a clock signal, and the like. Referring to FIG. 2, FIG. 3, which is an exemplary table of scanning pixel data, and FIG. 4, which illustrates mapping of pixel data and memory addresses, are described in detail as follows.

The data input from the scanner is sequentially input laterally as in FIG. 3, and they are sequentially stored in the memory from the start address (offset) as in FIG.

When accessing (reading) the stored data in this way, the longitudinal directions (1, 5, 10, ..., 30),... , (4, 9, 14,..., 34) may be accessed. Hereinafter, the scanning pixel data may be generated by hardware according to the present invention. Will be explained.

)에 제2c도와 같은 저전위의 로드신호를 인가하면 제2g도와 같은 기준클럭신호에 의해 제2d도와 같이 억세스할 데이터의 첫 번째 어드레스가 그 업카운터(2)에 로드된다.First, when a user outputs a low potential signal as shown in FIG. 2a to the input / output port IO1, the number of transverse data (5 pieces) is latched in the latch 1 as shown in FIG. (2) Rod terminal (

When the low potential load signal as shown in FIG.

At the same time, when the low-potential signal as shown in FIG. 2e is output to the clock terminal CK4 of the latch 4 through the input / output port IO3, the number (7) of the species to be accessed through the data bus is the latch (4). At this time, the down counter 5 is also connected to the species input from the latch 4 as shown in FIG. 3f by the low potential load signal input through the input / output port IO3 and the AND gate AD1. It starts counting down the number (7) and outputs the normal high potential to its ripple carry terminal (RC5), and then outputs the low potential when down counting all the numbers to the bell.

Accordingly, the first count value 0 output to the up counter 2 is applied to the input terminal IN6 of the address generation counter 6 through the buffer 3, as shown in FIG. 2G (h). The low potential load signal input through the inverter I1 is output as a start address to the output terminal Q6 of the address generation counter 6.

)에 저전위 신호가 인가되지 않아 상기 어드레스 발생 카운터(6)는 상기 버퍼(8)로부터 입력되는 데이터값(5)을 카운트하여 그 카운트값(5)을 출력단자(Q6)에 출력하게 되며, 이는 두 번째 어드레스로 메모리에 제공됨과 아울러 상기와 같이 가산기(7)에서 상기 래치(5)에 래치된 값(5)과 가산되므로 그 어드레스 발생 카운터(6)의 다음 입력값은 10이 된다.The first address (0) thus generated is provided to the memory and added to the latch value (5) of the latch (1) in the adder (7) and then input of the address generation counter (6) through the buffer (8). The output terminal of the ORA gate OR1 maintains a high potential regardless of the reference clock signal ø1 because the ripple carry is not generated in the down counter 5. ) Does not count the next number (1), but the enable terminal (

Since the low potential signal is not applied to the address generator 6, the address generation counter 6 counts the data value 5 input from the buffer 8, and outputs the count value 5 to the output terminal Q6. This is provided to the memory at the second address and is added with the value 5 latched to the latch 5 in the adder 7 as above, so that the next input value of the address generation counter 6 is 10.

)에 제공된다.In this way, when the address generation counter 6 outputs the address value 30 to the output terminal Q6, the down counter 5 counts? 0 and outputs a low potential to its ripple carry terminal RC5. Therefore, the basic clock signal ø1 output from the AND gate AD2 is connected to the clock terminal of the up counter 2 through the OR gate OR1.

Is provided.

)에 인가되는 반면, 상기 버퍼(3)는 상기 앤드게이트(AD1)를 통하여 다운카운터(5)의 저전위의 리플캐리신호에 의해 아웃인에이블되어 상기 업카운터(2)의 카운트값(1)이 그 버퍼(3)를 통해 상기 어드레스 발생 카운터(6)의 입력단자(IN6)에 제공된다.Accordingly, the up counter 2 counts the next number 1 at the rising edge of the clock signal, and the low potential output to the ripple carry terminal RC5 of the down counter 5 is transferred through the inverter I2. Inverted to a high potential, and then an out enable terminal of the buffer 8 (

The buffer 3 is enabled by the low potential ripple carry signal of the down counter 5 through the AND gate AD1, so that the count value 1 of the up counter 2 is applied. The buffer 3 is provided to the input terminal IN6 of the address generation counter 6.

)에 제 2h도와 같은 신호가 인가될때마다 그의 출력단자(Q6)에 제 2i도 같이 종방향의 어드레스가 순차적으로 출력되고, 상기 어드레스 발생 카운터(6)에 어드레스값(34)이 출력되는 순간 업카운터(9)가 ＂5＂를 카운트하게 되며, 이는 비교기(10)에서 상기 래치(1)의 래치값(5)과 비교되어 그의 출력단자(Q10)에 저전위가 출력되므로 이때 플립플롭(11)이 클리어된다.Accordingly, the counter value (1, 6, 11, 16, 21, 26, 31) is output to the address of the memory by the above process to the output terminal of the address generator (6). Load terminal of the counter 6

Each time a signal like 2h is applied to the output terminal Q6, the longitudinal address is sequentially output as shown in FIG. 2i, and as soon as the address value 34 is output to the address generation counter 6, The counter 9 counts " 5 ", which is compared with the latch value 5 of the latch 1 in the comparator 10 so that a low potential is outputted to the output terminal Q10 thereof. ) Is cleared.

As a result, a clock signal is not generated at the output terminal of the AND gate AD12, so that the address generation operation is stopped.

On the other hand, when the number of clocks corresponding to the number of species to be accessed by the user is applied to the input / output port IO3, the flip-flop 11 is released in a clear state so that the clock signal? C is the AND gate AD2. It is transmitted to the system as the basic clock signal (ø1) as it is.

As described in detail above, the present invention has the advantage that the access time can be shortened to the maximum by accessing a predetermined offset address from the start address using hardware.

Claims (4)

The address generator 100 generates an address for longitudinally accessing data in the memory in accordance with the input data, and the number of longitudinal addresses is added to the output address of the address generator 100, and the address generator 100 is added. Address generation unit (200) for feeding back to the address generator; and a clock generator (300) for providing a reference clock signal (ø1) to the address generator (100) and the address feedback unit (200). system. 2. A latch (1) for latching the number of data horizontally to be accessed, an up counter (2) and a buffer (3) for generating the first address to the species, and the number of data to the species to be accessed. A latch 4 for latching the latch, a down counter 5 for down counting the data latched in the latch 4, and an address generation counter for counting output data of the buffer 3 and generating an address in the longitudinal direction. (6) an address generating system (100) comprising an address generating system (100). An adder (7) for adding the value latched in the latch (1) and the output address of the address generation counter (6), and an output value of the adder (7). And an address feedback unit (200) comprising a buffer (8) provided as an input of the address generation counter (6) under the control of the ripple carry signal and the reference clock signal (ø1). The comparator according to claim 1, wherein an up counter (9) for counting each time data increases horizontally and a comparator for outputting a low potential when the output value of the latch (1) and the count value of the up counter (9) are equal to each other. (10) and the flip-flop 11, which is normally outputted at high potential and then cleared by the output signal of the comparator 10, the clock signal? C and the output signal of the flip-flop 11 are logically An AND gate (AD2) for generating the reference clock signal (ø1) comprises a clock generator (300).

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